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    • Simulation of Thermal Behavior for Networks-on-Chip Tim Wegner, Claas Cornelius, Martin Gag, Andreas Tockhorn, Adelinde Uhrmacher Institute of Applied Microelectronics and Computer Engineering, University of Rostock, Richard-Wagner-Str. 31, 18119 Rostock-Warnemuende, Germany tim.wegner@uni-rostock.de, www.networks-on-chip.com Abstract—Due to increasing integration densities and the it is the foundation for efficient measurements for thermalemergence of nanotechnology, especially reliability and power management, that have to be taken in order to reduce tem-related design aspects become critical for chip design. Since the perature and thermal stress. The basic idea proposed in thisarising problems are enforced by high circuit temperatures, theneed for a possibility to model thermal behavior of a system in paper is to model the dynamic thermal behavior of ICs byan accurate and physically correct way becomes inevitable. using an equivalent electrical RC circuit. Inside this circuitHence, in this paper VulcaNoCs, a SystemC-based simulation heat flow can be described as a current passing through aenvironment for systems based on NoCs, is introduced. Vul- thermal resistance and leading to a temperature differencecaNoCs is designed to enable simultaneous execution of both analogous to a voltage. Within this model capacitors representhigh-level system simulation and dynamic modeling of tempera-ture distributions in NoC-based systems. To emulate a system’s the thermal capacity of a component and resistors represent thethermal properties equivalent RC-circuits are used, exploiting thermal resistivity for heat flow to and from that componentthe dualism between heat flow and electrical phenomena. To in a certain direction [5]. Model generation is done by usingverify the temperature model, VulcaNoCs is compared to a more the SystemC Analog Mixed Signal (AMS) library [7] in ordercommonly used SPICE-based approach, exhibiting significant to integrate the model into a simulation environment for NoC-increases in simulation performance of up to 98,5 % for modelinga 2×2 NoC, for example. based systems. The resulting simulation environment is called Index Terms—Network-on-Chip, Temperature Modeling, Inte- VulcaNoCs and supports simultaneous simulation of high-levelgrated Circuits system behavior and dynamic thermal behavior. Temperature modeling can be done at different levels of granularity having I. I NTRODUCTION major influence on the trade-off between modeling accuracy The increasing integration density and the emergence of and complexity or performance respectively. The long-termnanotechnology lead to rising complexity as well as computing objective of this project is to enable real-time modeling andpower of modern multi- and many-core systems. A com- near-term prediction of temperature gradients in NoC-basedmunication architecture meeting the communication require- SoCs instead of using cost-intensive physical sensors to mon-ments of such increasingly complex systems is provided by itor temperature. Thereby, slow reactive countermeasures canNetworks-on-Chip (NoCs). However, the shrinking of device be replaced by proactive measurements to prevent predictedsizes causes issues related to reliability and robustness to temperature rises in advance. However, in this paper we focusbecome dominant factors for system design. On the course on the introduction of VulcaNoCs.of miniaturization, transistor count per die increases, giving The remainder of this paper is organized as follows. Inrise to a generally higher probability of system failures. Section II we give an overview over existing work done onAdditionally, the probability for a single transistor to fail is thermal modeling and analysis of on-chip systems and outlinealso raised, since the decreasing structural size of Integrated the advantages of concurrent simulation of system behaviorCircuits (ICs) leads to higher susceptibility to environmental and dynamic thermal modeling. In Section III, functionalityinfluences and deterioration. Several physical mechanisms and features of VulcaNoCs are described. Subsequently, incontributing to these effects are known to be abetted by Section IV first results of the comparison between VulcaNoCshigh temperatures. This leads to temperature having major and an equivalent SPICE model are presented. Finally, ininfluence on various parameters of ICs like long-term fail- Section V conclusions are drawn and future work is outlined.ure rate, lifetime, performance and power consumption. Therelationship between temperature and reliability is given by II. R ELATED W ORK AND D ISCUSSIONthe Arrhenius model, describing the influence of temperature Due to the great importance of modeling thermal behaviorchanges on the velocity of chemical reactions [1]. Thus, of ICs much work has already been done in this field. [5]lifetime of ICs depending exponentially on temperature can be proposes to use equivalent electrical RC-circuits in order topredicted. Two of the most important mechanisms accounting model thermal behavior of an arbitrary chip and its coolingfor deterioration are Electromigration [2] and Time Dependent package defined by a given floorplan. Modeling can be doneDielectric Breakdown [3] [4]. The stated facts emphasize that on various granularity levels resulting in different degrees ofaccurate temperature modeling for ICs is indispensable, since accuracy and speed. The modeling environment uses the aver-978-1-4244-8971-8/10$26.00 c 2010 IEEE
    • age power dissipated by each functional block over a certain supporting simultaneous simulation of system behavior andperiod to compute block temperatures for this period. Power temperature distribution promises to be a good starting point.profiles are provided by Wattch [6] and have to be determined III. T HE S IMULATION E NVIRONMENTin advance by analyzing hardware access statistics gatheredduring system simulation. In [8] the approach of [5] is refined In this section the functionality of VulcaNoCs is described.and used to model thermal behavior of on-chip networks. Additionally, the underlying RC-circuit model as well as theTherefore, the equivalent RC-circuit model is extended by the available modeling parameters and their expected impact oninclusion of heat spreading angles. Similar to [5], a separate modeling speed and accuracy are depicted more detailed.power model called Orion [9] is used to statically determine The cycle accurate NoC simulation environment that provideson-chip power consumption based on a predefined workload. the basis for VulcaNoCs uses both the core SystemC andFor workload determination the actual simulation of the on- the Transaction-Level Modeling (TLM) libraries. It provides achip system has to be performed in advance and the activity high degree of parameterization permitting for example deter-profiles have to be captured. In [10] Liu et al. generate a mination of NoC size, link width, simulation duration, sampleSPICE netlist in order to model the equivalent thermal RC- period and individual configuration of Intellectual Propertynetwork of a chip on the granularity level of standard cells Cores (IPCs) regarding load factors and packet lengths forfor application in thermal-aware placement and scheduling instance. Furthermore, it includes a comprehensive set oftools. To model on-chip temperature distribution, the average monitoring functions to trace network health (e.g. blockedpower consumption is estimated based on annotated switching paths or deadlocks), latencies and activity profiles. Every timeactivity of random generated vectors and is then delivered the aforementioned sample period expires, all statistics areto the simulation environment. The methodology presented captured and reset until simulation has finished. To preserveby Tockhorn et al. focuses on modeling the dynamic nature the integrity of the whole simulation environment VulcaNoCsof temperature distribution in many-core systems based on was developed by using the novel SystemC AMS library [7].NoCs [11]. For this purpose, the thermal properties of accord- This has the advantage that thermal behavior can be modeleding systems are modeled by equivalent RC-circuits, exploiting without dependence on external tools for estimation of powerthe dualism between electrical and thermal flows of energy. consumption. Since such tools usually require activity infor-After a SPICE netlist is generated representing the RC-circuit mation for the whole simulation time, power calculation duringof the underlying NoC, current sources are attached to the system simulation is not feasible preventing parallel executionRC-network incorporating sources of thermal energy. During of system simulation and thermal modeling. For the purposecircuit simulation current values, calculated from previously of modeling thermal behavior of NoCs, VulcaNoCs revertscaptured activity statistics, are fed into the network. to the well-known dualism of electrical and thermal energyAs a consequence of all models relying on data for power flows at which heat flow can be described as an electricalconsumption, that has to be provided by anticipant, simulation current passing through a thermal resistance and leading to aof thermal behavior can only be accomplished after the actual temperature difference analogous to a voltage [5].system simulation. This is due to the fact that all approaches R Rrevert to external tools for the extraction of values regarding Current IPC IPC Sourcepower consumption, which in turn depend on availabilityof component activity. On the one hand, this allows for R Rapplication of such models during design phase (e.g. for IPC IPCthermal-aware mapping and placement). On the other hand, thepossibility for thermal modeling and temperature monitoringof NoC-based systems during operation is excluded a priori. Fig. 1. 2×2 NoC mapped on a grid of 4×4 RC-tiles (Block model)For this reason we introduce VulcaNoCs, a SystemC-basedsimulation environment to account for simultaneous simulation Fig. 1 shows a 2×2 NoC mapped on a grid of 4×4 RC-tiles.of system behavior and temperature distribution. Unlike the Each tile consists of one vertical and 4 lateral thermal resistors,aforementioned methodologies, VulcaNoCs does not rely on a current source and a thermal capacitor. During simulationany external tools. This independency is achieved by using the temperature of a RC-tile is represented by the voltagethe Analog Mixed Signal (AMS) library recently released drop over the associated capacitor. The vertical resistor modelsby the Open SystemC Initiative (OSCI) [7]. Thereby, the the connection to the cooling package of the chip. Thermalopportunity to model the thermal properties of a system within capacitors are used in order to account for the delay before athe actual simulation environment is provided. In addition change in power results in temperature variation. Besides theto thermal-aware design, VulcaNoCs will be deployable to rather coarse-grained block modeling, VulcaNoCs supports 2a much wider range of applications including modeling of more precise models in which a functional block is resolvedtemperature distributions and proactive thermal management into multiple RC-tiles. This results in a more accurate but alsoduring system operation. Admittedly, a multiplicity of modifi- more complex model of the temperature distribution acrosscations and optimizations still has to be performed to achieve the chip. For high resolution models only the central RC-this objective, but the current implementation of VulcaNoCs tile of a block is assigned a current source. In addition to
    • modeling the chip, VulcaNoCs models the cooling package modules and checked for solvability (4). Hence, depending onconsisting of a heat spreader and a heat sink, following the NoC size and desired model resolution, elaboration takes aapproach in [5]. This contributes to a more realistic model more or less big fraction of the overall simulation runtime.behavior because most of the heat is dissipated along the path After elaboration has finished, simulation is started by settingthrough spreader and sink to the ambience. Both, spreader the initial conditions of all instantiated ELN primitives (5)and sink are resolved in 5 RC-tiles omitting current sources, followed by the actual simulation of the NoC and its thermalsince the cooling package does not produce heat itself. Due behavior (6). Corresponding to the sample period, the ELNto poor thermal conductivity heat dissipation into the die’s equation system is solved numerically and for each period theceramic insulating cap is neglected. To account for differ- newly calculated currents are injected into the network. Resultsent SoC and cooling package configurations, VulcaNoCs is for temperature are reported periodically as well.highly parameterized. Amongst others, parameters for model The essential advantage of VulcaNoCs is that it combines theresolution (Block; Res1: 1 Tile/Router; Res2: 4 Tiles/Router), assets of both SPICE-based netlist simulation and SystemC-thermal conductivity and capacitance, geometrical dimensions based NoC modeling. On the one hand, the ELN computation(die, spreader, sink thickness; edge length of IPCs and routers) model provides the same physically correct electrical primi-and power consumption per flit (for IPCs, routers and links) tives that SPICE offers. Thereby, accurate modeling of thermalare defined. Die size is calculated by means of the edge length behavior is ensured. On the other hand, the static nature of aof IPCs and routers as well as NoC size. Heat spreader size SPICE netlist is eliminated making it possible to inject stimuliamounts to die size multiplied by 1,5, while heat sink size is and to monitor temperature gradients during simulation. Ad-defined as spreader size multiplied by 2. The sample period ditionally, temperature modeling no longer relies on externalcontrols the time of simulation after which the voltage drops tools for the provision of values for power consumption.over the capacitors are captured and the newly calculatedcurrents are fed into the RC-network, depending on the activity IV. E XPERIMENTS AND R ESULTSof the functional blocks during the previously passed period. In this section first results concerning modeling accuracy and simulation performance of VulcaNoCs are presented. To NoC Geometry, Chip Geometry, provide for comparable values, simulations are additionally Simulation Model Accuracy Parameters performed using an equivalent HSPICE model like it is pro- Sample Period posed in [11]. Note that the HSPICE model does not support 1 block model resolution. NoC Setup ELN Setup 2 For our experiments we assume die, spreader and sink thick- Run Prede- ness to be 0,6 mm, 1 mm and 6,8 mm. The edge lengths of fined Time Time Step ELN IPC and router are 1,85 mm and 0,141 mm resulting in a die Calculation & 3 Elaboration Periodic NoC Propagation of about 4×4 mm for an 2×2 NoC. Values for thermal con- Simulation 6 Equation Setup & 4 ductivity are 100 W/m∗K for the die (i.e. silicon), 400 W/m∗K Solvability Check for heat spreader and sink (i.e. copper) and 2 W/m∗K for Initialization 5 the die package (i.e. ceramics). Thermal capacitance is set to Periodic Output: ELN Time- Component Activity Periodic Equation domain 1,75∗106 J/3 ∗K for silicon and 3,55∗106 J/3 ∗K for copper. Solving 6 Simulation Ambience is assumed to be at a fixed temperature of 45 ∘ C. Periodic Ouput: Temperature Profile NoC configuration is a regular mesh topology with a clock frequency of 1 GHz and a router buffer depth of 6 flits. During Fig. 2. Simulation flow of VulcaNoCs simulation all IPCs generate packets with a probability of 50 % using random destination addresses. With the given parameter values for NoC geometry and To estimate simulation performance and accuracy of differentsimulation VulcaNoCs is executed according to the flow model resolutions a 2×2 NoC was simulated over 1 ms to com-depicted in Fig. 2. First, the NoC topology is set up (1) pare VulcaNoCs and the HSPICE-based temperature model.whereas the IPCs are represented as sending and receiving As expected, within both models different resolutions haveunits. Subsequently, the equivalent RC-network is established only negligible impact on average temperature (see Fig. 3).according to the defined parameters. The required descriptions With values of 0,009 ∘ C (Block) and 0,006 ∘ C (Res1 and Res2)for the electrical components (i.e. resistors, capacitors, current for average deviation with respect to the HSPICE-based modelsources) are extracted from the SystemC AMS library using using Res2, discrepancy between both modeling approachesthe Electrical Linear Networks (ELN) model of computation. is vanishingly small. However, these differences apparentlyExecution of an ELN model is divided into elaboration and increase over time and originate from the disparate implemen-time-domain simulation. During elaboration electrical primi- tation of the used current sources. HSPICE uses Piecewisetives are declared and instantiated (2). Additionally, sample Linear Sources (PWL), which model currents by pairs ofperiod for all ELN primitives is defined and propagated points in time and according current values. Therefore, currentthroughout the network (3). Furthermore, the differential equa- between 2 points in time follows a linear function. By contrast,tion system is composed from all contributing ELN primitive current sources applied for VulcaNoCs use these pairs to form
    • a continuous-time signal. Since this is a more lifelike way of V. C ONCLUSION AND F UTURE W ORKmodeling current flows, we hold that deviations in temperature In this paper we presented VulcaNoCs, a SystemC-basedbetween VulcaNoCs and HSPICE are at most a sign of higher environment for simultaneous simulation of system behavioraccuracy for VulcaNoCs. Performance results for temperature and temperature distribution in NoC-based Systems-on-Chip.modeling have to be examined more differentiated as modeling A wide range of topological, geometrical and technologicalin VulcaNoCs is divided into phases of elaboration and sim- parameters allows for a flexible and detailed description ofulation. For the purpose of comparison, only the overall time the targeted chip and the associated cooling package. Bytaken for HSPICE is considered because simulation cannot comparing VulcaNoCs to an equivalent HSPICE model thebe divided in similar sub-phases. Table I shows the results benefits of VulcaNoCs regarding performance of the actualregarding time spent for elaboration and the actual mod- simulation were highlighted.eling of temperature ,ℎ . As expected, elaboration Nevertheless, it would be desirable to avoid the strongly timetime for VulcaNoCs increases drastically with rising model consuming part of elaboration whenever possible. This wouldresolution yielding 1,817 s for Block resolution (16 RC-tiles), be of convenience if multiple simulations of the same SoC73,438 s for Res1 resolution (784 RC-tiles) and 5005,276 s for (i.e. with identical modeling parameters) shall be performedRes2 resolution (3136 RC-tiles). Despite the fact that high or if a running simulation is interrupted and then resumed.resolutions cause a serious penalty to overall performance, Since it is planned to modify VulcaNoCs for the purpose ofthey are still valuable if a detailed and fine-grained depiction of thermal monitoring and management during system operation,temperature profiles is required at all costs. Thus, performance it is conceivable to equip VulcaNoCs with a set of differ-has to be traded off against detailedness of modeling. However, ent pre-elaborated SoC models so that only the appropiateVulcaNoCs’ model resolution has almost no impact on the model has to be selected and temperature modeling can betime taken for simulation, while HSPICE simulation runtime started directly. Another possibility is to use a save-and-is significantly affected by high resolutions. This results in restore technique following the approach in [12] for example.VulcaNoCs needing only 37,2 % (for Res1) and 1,5 % (for The storage of elaboration state is already proposed in theRes2) of the time that is required by HSPICE. For this reason, SystemC Language Reference Manual [13]. However, theif elaboration is excluded, VulcaNoCs clearly outperforms the ultimate objective is to enhance VulcaNoCs for the deploymentHSPICE model especially for high resolutions. This behavior in near-term prediction of thermal behavior. Thereby, the needis anticipated to be enforced with growing NoC sizes, but for comparatively slow and expensive physical temperaturecan only be exploited if the nonrecurring elaboration phase sensors could be eliminated and reactive thermal managementis somehow backed up. For repeated temperature modeling of measurements could be replaced by proactive alternatives.identical NoC configurations, this backup might be restored.Thereby, unnecessary repetition of elaboration can be avoided ACKNOWLEDGMENTand computation overhead can be reduced. The authors would like to thank Sven Poeggel for his contribution to this research project. 45,35 VulcaNoCs Block 45,3 VulcaNoCs Res1 R EFERENCES VulcaNoCs Res2 HSpice Res1 HSpice Res2 [1] J. Srinivasan, et al., ”RAMP: A Model for Reliability Aware Micropro- 45,25 cessor Design”, IBM Research Report, RC23048, 2003Avera temperature [°C] [2] J. Lienig, ”Introduction to Electromigration-Aware Physical Design”, in 45,2 Proc. of ISPD 2006 45,15 [3] J. Stathis, et al., ”Reliability Limits for the Gate Insulator in CMOS Technology”, IBM Journal of Research and Development, 2002 45,1 [4] E. Vogel, et al., ”Reliability of Ultra-Thin Silicon Dioxide Under age Combined Substrate Hot Electron and Constant Voltage Tunnel Stress”, 45,05 in Trans. of Electron Devices, vol. 47, no. 6, 2000 [5] K. Skadron, et al., ”Temperature-Aware Microarchitecture”, in Proc. of 45 ISCA 2003 [6] D. Brooks, et al., ”Wattch: A framework for architectural-level power 44,95 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 analysis and optimizations”, in Proc. of ISCA 2000 Simulated time [μs] [7] Open SystemC Initiative, Standard SystemC Analog/Mixed-Signal Ex- tensions 1.0, http://www.systemc.org/downloads/standards/ams10 [8] L. Shang, et al., ”Thermal Modeling, Characterization and Management Fig. 3. Average temperature in the RC-network of On-Chip Networks”, in Proc. of MICRO 2004 [9] H.-S. Wang, et al., ”Orion: A power-performance simulator for inter- connection networks”, in Proc. of MICRO 2002 TABLE I [10] W. Liu, et al., ”On-chip Thermal Modeling Based on SPICE Simula- S IMULATION PERFORMANCE FOR TEMPERATURE MODELING tion”, in Proc. of PATMOS 2009 [11] A. Tockhorn, et al., ”Modeling Temperature Distribution in Networks- VulcaNoCs HSPICE on-Chip using RC-Circuits”, in Proc. of DDECS 2010 Model [12] M. Mont´ n, et al., ”Checkpoint and Restore for SystemC Models”, in o Block Res1 Res2 Res1 Res2 [s] 1,817 73,438 5005,276 / / Proc. of FDL 2009 ,ℎ [s] 8,464 8,92 7,261 24 492 [13] IEEE Standard SystemC Language Reference Manual, http://standards.ieee.org/getieee/1666/download/1666-2005.pdf