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  • 1. A Novel Simple And High Performance Structure For Improving CMRR: Application to Current Buffers and Folded Cascode Ampilifier Amir Hossein Miremadi Hassan Faraji Baghtash Islamic Azad University, West Tehran branch Iran University of science and technology (IUST) electrical Tehran, Iran and electronic engineering faculty/ Electronics research amirh_miremadi@yahoo.com center Tehran, Iran hfarajii@gmail.comAbstract—A novel and simple structure for improving CMRR is process signals in differential form rather than ground-introduced. This structure can be added to the circuits like folded reference form. Another advantage of differential operationcascode amplifier, telescopic amplifier, current buffers, .etc to over the single-ended case is that the amplitude of the signalimprove the CMRR of these circuits. This simple and effective increases by the factor of 2[2]. An important parameter ofcircuit uses common mode deviating technique to improve differential active structures is the CMRR. Differential signalsCMRR at least 12dB while preserves CMRR bandwidth which is have the advantage of canceling common-mode interferencea novel technique in order to improve CMRR. Application of this from unwanted signals and/ or noise. So CMRR is one of thestructure in both current buffer and folded cascode structures most significant parameters in many of the circuits which areare shown. Simulation results in TSMC 0.18µm CMOS processing differential signals; such as Op-amps, OTAs,technology with HSPICE are presented to demonstrate thevalidity of the proposed circuit. In addition Monte Carlo analysis current buffers, etc; hence its improving is a critical issue inis performed to simulate the fabrication condition. these circuits. Any variation of the input stage tail current source in these circuits can significantly harm both Keywords- High cmrr; current buffer; analog circuits; mixed deterministic and random components of the CMRR [3], [4].mode; low voltag;, low power There have been numerous attempts to improve CMRR [5]-[7]. Most of these references used schemes to increase tail output impedance such as using cascode current mirror. However I. INTRODUCTION most of these structures cause to increase minimum voltage Todays Digital Signal Processing (DSP) is extremely on requirement. Some other structures that used techniques whichdemand because of its natural benefits like reduced sensitivity didn’t need high output impedance tail need complicatedto analog noise, enhanced functionality and flexibility, implementation. On the other hand these structures need moreautomated design and test, shorter design cycle, direct benefit power consumption and cause reduction in CMRR bandwidth.from the scaling of VLSI technology, etc. But real world In this paper we proposed a simple and high effective cellsignals are analog; hence mixed-mode ICs are becoming which can be added to the circuits like folded cascode structureprogressively dominant i.e. System On Chip (SOC). In other and it cause improvement in CMRR and PSRR; whereas itwords Mixed-mode signal processing attracts increasing preserves CMRR bandwidths. This structure is composed ofattention since it simplifies design, enables compactness and only four transistors and increases power consumption slightly.reduces cost. However signal interference from the digital tothe analog part remains a serious problem to overcome [1]; this II. PROPOSED HIGH PERFORMANCE COMMON MODEis due to the fact that in a SOC, both analog and digital parts of DEVIATING CELLcircuit have the same substrate. In these circuits, analog partsmust be resistant to the power supply interference coming from Fig .1 shows the conceptual schematic of the proposeddigital part. These variations which are caused by transient common mode deviating cell. The main idea is using a circuitcurrents of digital circuits can cause undesired effects on power in parallel with signal path which has infinitive input resistancesupply rails or analog circuits’ inputs as common mode. Hence to the differential currents and zero to the commons. By usingboth CMRR and PSRR play important roles in analog circuits. this idea we can deviates common mode currents and preventOn the other hand, technology scaling imposes power supply to them from going to the output. On the other hand differentialbe lowered. Decreasing power supply imposes some currents cannot flow in this block because of infinite resistancerestrictions on design procedure and harms common-mode to these signals ideally. Fig.2 shows transistor levelrejection ratio (CMRR) and power supply rejection ratio implementing of this idea. This structure is composed of n-type(PSRR). Hence, for such circuits differential building blocks transistors M1, M2, p-type transistors Md1, Md2 and currentare accepted as a good solution. Therefore it is desired to source of Ib. transistors Md1, Md2, and current source of Ib 978-1-4244-8971-8/10$26.00 c 2010 IEEE
  • 2. which form the differential pair, and transistors M1 and M2 From (1) and (2) we can obtain common mode inputmake the deviation path for the common mode signals. impedance Rind and differential input impedance Rinc of theAveraging property of differential pair is used to control gates proposed circuit as follows.of M1 and M2. When a differential signal is applied to theinputs of differential pair, its source voltage remains constant;but when its input signal is common, the circuit acts as a ⎛ 1 ⎞voltage follower and the source voltage follows its inputs. Rinc = ⎜ ro1,2 ⎟ ⎜ α g m1,2 ⎟Using this property of differential pair we can control gate ⎝ ⎠voltages of M1 and M2 so that, when the common signals are Rind = ro1,2applied to the inputs of the proposed cell, voltage following (3)property of differential pair aids a) transistors M1 and M2 to actas a diode and sink common mode currents; b) input Where gm1,2 and ro1,2 are transconductance and outputimpedance of Md1 and Md2 to increase because their VGS resistance of M1 (or M2) respectively.remains constant. On the other hand when a differential signalis applied to the cell inputs, gate voltage of transistors M1 andM2 doesn’t change and these transistors show no action to thistype of signals; this means resistivity of circuit to thedifferential signals is high significantly. ∞ 0r rd = rd = rc = c = 0 ∞ Figure 2. Transistor implementation of proposed common mode alienates cellFigure 1. A conceptual schematic of proposed common mode alienates cell Any deviation from ideal case leads to a decrease inCMRR. Here we used a simple current mirror to provide tailcurrent of Ib. If considering small signal condition, Voutcm canbe obtained from (1): voutcm = ( ) g md 1,2 rod 1,2 2rotail vincm = (1 − α ) vincm ( 1 + g md 1,2 rod 1,2 2rotail ) (1) (a) where Voutcm, Vincm, gmd1,2, rod1,2,rotail are common modeoutput voltage, common mode input voltage, transconductanceof Md1 (or Md2 ), output resistance of Md1 (or Md2 ), outputresistance of tail current source respectively, and α is 1attenuation factor we defined here as α = 1 + g md 1, 2 ( rod 1, 2 2 rotail )where for differential mode input voltage Vindm and differentialoutput voltage Voutdm , equal zero. (b) voutdm = 0 (2) Figure 3. (a) Conventional current buffer. (b) Proposed High CMRR current buffer.
  • 3. III. APPLICATIONS IV. SIMULATION RESULTS The proposed structure is very simple, power efficient, and HSPICE simulation were performed using TSMC 0.18µmhas low transistor number. This structure can be applied to the CMOS technology at 1.8 V power supply. The transistors W/Lprevalent structures such as current buffers, folded cascode are shown in table .1. Two circuits are simulated at the samestructures and cause significant improvement in CMRR and condition to make comparison. Fig .5 shows frequencyPSRR in these structures. Here we applied our proposed circuit response of conventional and proposed current buffer.to the current buffer and folded cascode OTA and compared Differential and common mode input currents are applied tothe CMRR of them both. Fig .3 (a) shows a simple current the both simple and proposed current buffer from in+ and in-buffer; differential input currents are applied to the Iin1 and Iin2 and output currents are taken from Io1 and Io2. The figureas shown in the fig .3 (a) and the output taken from Io1 and Io2. exhibits about 12 dB CMRR for proposed current buffer this isApplying proposed cell to the simple current buffer, the significant enhancement in CMRR value compared to its valuemodified current buffer is obtained (See fig .3 (b)). For simple in simple one.current buffer both differential and common mode inputimpedances are obtained from rin=1/gmc where for proposedcurrent buffer we can obtain input impedance to the differentialand common mode signals as rind=1/gmc and rinc =α/gmc||rocwhere gmc and roc are transconductance and output impedanceof Mc1 (or Mc2) respectively. A conventional folded cascode input stage is shown in fig.4 (a). Modified version of this is shown in fig .4 (b)(proposed). Differential and common mode input impedancefor proposed OTA are the same as proposed buffer. Figure 5. CMRR of the proposed and conventional current buffer Fig .6 shows the frequency response of the conventional and proposed folded cascode OTA. Differential and common mode input currents are applied to the both simple and proposed current buffer from in+ and in- and output currents are taken from Io1 and Io2. As shown in fig .6, the proposed circuit increases (up to 12 dB) the CMRR whereas it preserves CMRR bandwidth. Preserving CMRR bandwidth is very interesting feature of this circuit which is not accessible in other similar works. (a) Figure 6. CMRR of the proposed and conventional folded cascode OTA Monte Carlo analysis is performed by 3% variation on transistors aspect ratio to simulate fabrication condition. Fig .7 shows Mont Carlo analysis for both simple and proposed (b) current buffer. Comparison of Mont Carlo analysis for simple and proposed folded cascode OTA is shown in fig .8. As Figure 4. Conventional folded cascode OTA. (b) Proposed High CMRR shown, CMRR of proposed circuits increased at least 10 dB in folded cascode OTA. comparison with the conventional structures.
  • 4. TABLE I. TRANSISTORS ASPECT RATIO OTA Current Buffer ELEMENT Proposed conventional Proposed conventional W L W L W L W L M1 0.36 µm 0.18 µm NA NA NA NA NA NA M2 0.36 µm 0.18 µm NA NA NA NA NA NA Md1 27 µm 0.18 µm NA NA NA NA NA NA Md2 27 µm 0.18 µm NA NA NA NA NA NA Mc1 5.4 µm 0.54 µm 5.4 µm 0.54 µm 5.4 µm 0.54 µm 5.4 µm 0.54 µm Mc2 5.4 µm 0.54 µm 5.4 µm 0.54 µm 5.4 µm 0.54 µm 5.4 µm 0.54 µm Mm1 3.6 µm 0.54 µm 3.6 µm 0.54 µm 3.6 µm 0.54 µm 3.6 µm 0.54 µm Mm2 3.6 µm 0.54 µm 3.6 µm 0.54 µm 3.6 µm 0.54 µm 3.6 µm 0.54 µm MI1 3.6 µm 0.18 µm 3.6 µm 0.18 µm NA NA NA NA MI2 3.6 µm 0.18 µm 3.6 µm 0.18 µm NA NA NA NA Mmp1 2.7 µm 0.54 µm 2.7 µm 0.54 µm NA NA NA NA Mmp2 2.7 µm 0.54 µm 2.7 µm 0.54 µm NA NA NA NA and cause CMRR to improve in these circuits. This simple and high effective circuit uses common mode deviating technique to improve CMRR while preserves CMRR bandwidth which is a novel technique in order to improve CMRR. Application of this structure on both current buffer and folded cascode structures are shown. Simulation results in TSMC 0.18µm CMOS technology with HSPICE are presented to demonstrate the validity of the proposed circuit. Mont Carlo analysis is performed for simulating fabrication condition and corroborated the appropriate performance of the proposed circuit. ACKNOWLEDGMENT This work is supported by Islamic Azad University, West Tehran branch.Figure 7. Monte Carlo analysis of conventional and proposed current buffer. REFERENCES - -) Simple. - ) Proposed [1] Shahram Minaei ,I. Cem. Go¨ knar, Oguzhan Cicekoglu, "A new differential configuration suitable for realization of high CMRR, all- pass/notch filters," Springer-Verlag, p. 317–326, May 2005. [2] Allen PE, Holberg DR, CMOS analog circuit design, 2, Ed. New York: Oxford University Press, 2002. [3] C.-G. Yu and R. L. Geiger, "Nonideality consideration for high- precision amplifiers—Analysis of random common-mode rejection ratio," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 40, no. 1, p. 1–12, Jan. 1993. [4] F. You, S. H. K. Embabi, and E. Sanchez-Sinencio, "On the commonmode rejection ratio in low voltage operational amplifiers with complementary N-P input pairs," IEEE Trans. Circuits Syst. II, Analog Digit.Signal Process., vol. 44, no. 8, p. 678–683, 1997. [5] Vadim Ivanov, Junlin Zhou, and Igor M. Filanovsky, "A 100-dB CMRR CMOS Operational Amplifier With Single-Supply Capability," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, vol. 54, no. 5, pp. 397-401, May 2005. [6] Vadim Ivanov, Junlin Zhou, Igor Filanovsky, "A 100 dB CMRR CMOSFigure 8. Monte Carlo analyses of conventional and proposed folded OTA. - Operational Amplifier With Single-Supply Capability," IEEE., pp. 9-12, -) Simple. - ) Proposed 2004. [7] Jaime Rámirez-Angulo, Sandhana Balasubramanian, Antonio J. López- Martin, and Ramón G. Carvajal, "Low Voltage Differential Input Stage I. CONCLUSION With Improved CMRR and True Rail-to-Rail Common Mode Input A novel and simple structure for improving CMRR was Range," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, vol. 55, no. 12, pp. 1229-1233, Dec. 2008introduced. As shown, this structure can be added to thecircuitries like folded cascode amplifier, current buffers, etc.;

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