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  1. 1. On CMOS Scaling and A/D-Converter Performance Bengt E. Jonsson ADMS Design AB Gåsbackavägen 33 S-820 60 Delsbo, Sweden bengt.e.jonsson@admsdesign.comAbstract— The influence of CMOS scaling on A/D-converterperformance is investigated by observing the entire body of II. ABOUT THIS WORKexperimental CMOS ADCs reported in IEEE journals and The purpose of this work is to derive an understanding ofconferences central to the field from 1976 to 2010. Based on the how practical ADC performance limits are influenced bynear-exhaustive set of scientific data, empirically observed CMOS technology scaling through analysis of experimentalscaling trends are derived for performance in terms of noise- data from a very large number of attempts. For simplicity, it isfloor, speed and resolution, as well as for power efficiency assumed that the documented state-of-the-art performance afterexpressed by two commonly used figures-of-merit. The trends areused to estimate limits on the achievable ADC performance in a large number of attempts will approach the practicalnanometer CMOS technologies, with implications for LTE and performance limits at any given CMOS node during a maturingWCDMA infrastructure applications particularly highlighted. process. As pointed out in [4] and [13], the formulation of a universal and accurate theory is a considerable challenge, Keywords— Analog-digital conversion, ADC, CMOS, VLSI particularly when it comes to the power vs. performancetechnology, Telecommunication, LTE, WCDMA, SoC tradeoff. The latter has a considerable variation with respect to ADC classes such as - and Nyquist, and between I. INTRODUCTION architectures within such classes [3]-[4], [13]. Additionally, the options within individual architectures include the use of A/D-converter performance is often limited by the available different partitioning, circuit topologies, error compensationdevice technology. While recent designs may benefit from techniques, etc., that may or may not influence how the designscaled device geometries and higher bandwidth, there is a loss copes with the effects of scaling. As an example, digitalin dynamic range and sampling linearity due to reduced supply calibration of pipeline ADCs can compensate for the difficultyvoltages and available swing. With the increasing interest in to achieve sufficient OP-amp gain in scaled CMOS [14], andone-chip solutions, the demand for SoC-compatible ADCs thus allow the architecture to withstand the negative effects ofimplemented in current digital processes is high [1]. It is scaling better than predicted by circuit analysis alone. A mainlytherefore important to understand the impact of technology empirical approach is therefore chosen as a starting point, and ascaling on ADC performance. Such understanding can be first step towards describing the observed experimental data.acquired either by theoretical analysis, empirical observations, Future work may study the differences with respect toor a combination of both. While there have been surveys on architecture, calibration techniques, etc.ADC performance evolution over time [2]-[5], it has not beenobserved on a large data set how ADC performance correlates III. CMOS TECHNOLOGYwith technology. Merkel [6] observes power dissipation vs.CMOS node and supply voltage for a subset of 150 ADCs with Scaling of CMOS technology is often described by thefs 1 MHz, and at least 12-b resolution. Chiu [7] discusses minimum MOS transistor channel length (or “node”) Lmin, butvarious scaling issues, and observe the correlation between a has an impact on several other parameters in the design space.figure-of-merit (FOM) vs. supply voltage in a data set of 100 Shrinking geometries has the benefit of higher bandwidthADCs. Uyttenhove [8] has a mainly theoretical approach but because device cutoff frequency (fT) increases with scaling [8].observe a small set of empirical data. Other relevant work is At the same time, scaling implies a lower supply voltagefound in [9]-[12]. To the best of the author’s knowledge, (VDD) [13], which limits the available signal swing. Even ifprevious observations on ADC performance vs. technology the absolute noise-level is approximately constant with scalingscaling thus did not use a subset larger than 10–20% of all [15], the relative noise-floor will still increase due to the loweravailable data. The study presented in this paper is based on a swing. Simply scaling the swing by 1/5 raises the relativelarge data set extracted from more than 1100 scientific noise-floor by as much as 14 dB – all other conditionspublications published from 1976 to present day (March 2010), unchanged. The available swing is further reduced by the factand therefore represents nearly all the experimental ADC data that the threshold voltage (VT) in nanometer technologies doesreported in major IEEE publications. Data was collected from not necessarily scale proportionally to VDD, if it is optimizedthe IEEE J. of Solid-State Circuits and IEEE Transactions on for gate leakage power [13] in digital circuits. Because neitherCircuits and Systems, as well as seven major conferences, and fT, VT nor VDD maps one-to-one with Lmin, and swing is notis the CMOS subset of the data in [5]. As far as the author is defined by VDD alone, all of these parameters should beaware, this makes it the largest and most comprehensive study considered for a complete view. For simplicity, scaling isof CMOS ADC performance vs. scaling to this date. Figure 1 described by the single parameter Lmin in this paper, with theshows the distribution of the data set over CMOS nodes. motivation that Lmin implicitly captures a large part of the 978-1-4244-8971-8/10$26.00 c 2010 IEEE
  2. 2. effects on fT and VDD. It should however be noted that 300reported VDD can vary as much as one order of magnitudewithin each CMOS node as shown in Fig. 2. Future work may 250include this VDD-variation as a second dimension of scaling. 200 IV. MATURING OF CMOS NODES count 150 The underlying data set reveals that new CMOS nodes havebeen adopted for ADC design at a steady rate [5], and that each 100node can easily have a 10-year lifespan in publications. 50Performance vs. Lmin (studied here) is therefore not the same asevolution over time analyzed elsewhere [2]-[5], even if there is 0a degree of correlation. An important aspect of time for this 0.065 0.045 6 5 4 3.5 3 2.5 2.4 2 1.6 1.5 1.4 1.3 1.2 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 10 1.75 0.72 0.65 0.35 0.25 0.21 0.18 0.15 0.13 0.12 0.11 0.09 0.04study is that ADC performance always has a tendency to drop Figure 1. Number of scientific publications per CMOS node.for the most recent nodes, but over time the performancematures before the node is finally abandoned for newer 10technology. Figure 3 illustrates such a maturing process: Thestate-of-the-art envelope for relative noise-floor vs. CMOSnode is shown for every 5th year between 1990 and 2010. Supply Voltage (V)Relative noise floor (nr) is defined by signal-to-noise-ratio(SNR) and Nyquist bandwidth (BW = fs/2) as 1 nr = (SNR + 10 log10 BW ) (1) Figure 3 illustrates both the evolution of CMOS technology(horizontal progress), and the maturing process within each 0.1 10000 3000 2000 1000 500 350 250 180 130 90 65 45 32node (vertical progress). As an example, noise performance in Technology Node (nm)0.25 m CMOS, being in a pioneering phase 1990 [16], has Figure 2. Correlation between supply voltage and CMOS node.matured from –110 to –160 dB/Hz, where it has remained since2005 [17]. Looking at the progress in Fig. 3, and the reported −90number of attempts per node in Fig. 1, it seems that the state- −100 maturing technology evolutionof-the-art envelope down to 0.25 m has reached its “final” −110state, while it is likely that ADCs in 45 nm and below will be Noise Floor (dB/Hz)improved upon due to the current lack of attempts. Regarding −120 1990intermediate nodes, Fig. 1 shows that both 90 and 130 nm have −130as many reported attempts as any other mature nodes (50–100 −140publications), and that 180 nm ADC implementations has been 2010 −150reported in over 250 publications. It is therefore concluded thatthese nodes have also reached, or are close to their final state −160with respect to noise floor. ADCs in 65 nm have been reported −170in almost 50 publications, and should therefore be reasonably 10000 3000 2000 1000 500 350 250 180 130 90 65 CMOS Node (nm) 45 32mature as well. Note that the relative noise floor values are not Figure 3. Relative noise floor vs. CMOS node. State-of-the-artstrictly final, since they can be improved on by lowering the envelopes at 1990 ( ), 1995 ( ), 2000 ( ), 2005 (+), andabsolute noise floor or by increasing the signal swing. For 2010 ( ) illustrate the evolution of CMOS.nodes down to 90 or 65 nm, most of such improvement hasalready taken place – as a part of the maturing process – and resolutions 8 and 12-b suggest that the amount of performancethe observed state-of-the-art is therefore believed to be close to gain or loss vs. scaling depend on the resolution.practical limits with respect to voltage swing and acceptablepower dissipation. A. Scaling limits To further investigate how ADC performance evolves under V. PERFORMANCE VS. CMOS NODE process scaling, the location of the peaks in Fig. 4 over time is This section looks at the raw performance described by the plotted in Fig. 5. By including only the years when state-of-the-simultaneous combination of effective resolution (ENOB) and art fs was actually advanced or matched, the curves show thesampling rate (fs), irrespective of power dissipation (P). In evolution trajectories with respect to fs and CMOS node fororder to understand how scaling affects the performance of each resolution grade. Expectedly, low-resolution ADCs withlow-, medium-, and high-resolution ADCs, the current state-of- ENOB 4 keep improving their speed while continuouslythe-art sampling rate achieved at fixed minimum ENOB of migrating to newer nodes. Interestingly, high-resolution ADCsrespectively 4, 8, 12, and 14-b is observed vs. CMOS node. As with ENOB 14 do that as well, only with a greater lag in Lmin.expected, Fig. 4 shows that high-resolution ADCs suffer more Hence, not even ADCs with 14-b ENOB appear to havefrom scaling, and the current peak fs at ENOB 14 (12.5 MHz) reached their scaling limit, where fs can no longer be improvedwas achieved in a 0.25 m process [18]. Low-resolution ADCs or matched in newer CMOS nodes. In fact, there are noon the other hand seem to improve with every step of scaling, obvious signs of scaling fatigue in any of the four trajectories inand the highest sampling rate with ENOB 4 (29 GHz) was Fig. 5. The noise floor is therefore used to estimate possiblereported for a 65 nm design [19]. The curves for intermediate scaling limits. Even if fT increases with scaling, fs can only
  3. 3. increase until the noise integrated over fs/2 becomes too large. 6 10Assuming that ENOB is entirely noise-limited, Eq. 1 therefore ENOB ≥ 4yields the highest possible sampling rate: 4 10 ( nr + SNR ) ( nr + 6.02 ENOB+1.76 ) 2 10 fs (MHz) fs = 2BW = 2 10 10 = 2 10 10 (2) 0 10The empirically observed values for nr vs. Lmin in Fig. 3 areused to calculate the limits on fs under the assumption that nr −2 10will not improve. These limits have been included in Fig. 5 for ENOB ≥ 14ENOB = 12 and 14. Although the evolution trajectories in −4 10 10000 3000 2000 1000 500 350 250 180 130 90 65 45 32Fig. 5 show no sign of scaling fatigue, the 12 and 14-b ADCs CMOS Node (nm)are actually about to hit the noise floor limit where fs cannot be Figure 4. Peak fs at fixed effective resolution vs. CMOS nodeimproved, or even maintained, in newer technologies. With when ENOB 4 ( ), 8 ( ), 12 ( ), and 14 bits ( ).nr = -160 dB/Hz in 0.25 m, fs,max = 50 MHz for ENOB = 14.In 180 and 65 nm, fs,max is respectively 23 and 2.2 MHz. Limits Table I, the possibility for monolithic integration of widebandon fs at other ENOB levels are shown in Table I. ADCs with digital signal processing for LTE and multi-carrier WCDMA is limited to nodes older than 90–180 nm due to TABLE I. SAMPLING RATE LIMITS VS. CMOS NODE noise, and it is therefore not likely to happen. In fact, even the availability of stand-alone “14” and “16-b” ADCs at several ENOB (bits) hundred MHz, seems to rely on the continued use of 0.18– Node 8 12 12.6 13 14 0.35 m processing unless a further increase in power is Lmin (nm) nr (dB/Hz) fs (GHz) fs (MHz) accepted in order to lower the noise floor. 250 –160 200 800 350 200 50 180 -156.7 95 370 160 93 23 VI. POWER EFFICIENCY (FIGURE-OF-MERIT) While raw performance is the critical parameter in certain 90 -150 20 80 35 20 5 applications, power efficiency can be as important in others. 65 -146.5 9.1 35 15 8.9 2.2 Power efficiency will be observed by two commonly used figures-of-merit, F1 and F2:B. Consequences for telecommunications P P (3)The values in Table I were chosen with telecommunication F1 = , F2 =infrastructure in mind. Commercial “14-b” ADCs with 2 ENOB fs 2 2 ENOB fsfs 100 MHz typically have an ENOB between 12 and 12.6,and “16-b” ADCs have 12.6 to 13 effective bits. Such ADCs Both F1 and F2 relate the ADC power dissipation to itswith sampling rates of 125, 250 and 500 MS/s are of interest performance in terms of conversion rate and conversion error.for the RX chain in multi-carrier WCDMA and LTE base F1 considers error amplitude, whereas F2 use error power. Bothstations, and their future availability is important for the FOM are included in this work since F1 tend to favor lowtelecommunications industry. Furthermore, a high level of power, while F2 favors high resolution [1], [4], [20]. Theintegration is desirable for miniaturization of future products, current state-of-the-art envelopes for F1 and F2 vs. CMOS nodeand the potential for implementing such ADCs in nanometer are shown in Fig. 6 and 7. Additional evolution trajectoriestechnologies is therefore evaluated: While a 500 MS/s ADC (dashed) show data points for every year that the state-of-the-with ENOB = 12 is possible in 0.25 m CMOS, the theoretical art was advanced or matched. It is evident from Fig. 6 that F1limit based on observed noise floor is 370 MS/s in 180 nm, has improved with every new CMOS node having reached80 MS/s in 90 nm, and a mere 35 MS/s in 65 nm. The peak maturity, and there is no sign of saturation. Current state-of-sampling rate is reduced 4X per increased bit of resolution, and the-art [21] is therefore likely to be improved upon in 45 nmthen further reduced with every node of scaling. According to and below. Figure 7, on the other hand, shows that F2 was 5 3 3 2 10 10 2009 2006 10 10 ENOB ≥ 4 2010 ENOB ≥ 8 2005 ENOB ≥ 12 ENOB ≥ 14 2008 2004 2003 2003 2002 2009 4 2 1997 2 2010 10 10 1996 10 1 2001 2002 1992 2004 10 1991 2003 2001 2003 2001 2001 3 1 1990 1 2000 10 2000 10 10 2000 1997 f (MHz) 1996 1999 1987 1998 0 1989 10 1995 1996 s 2 1993 0 0 10 1992 10 10 1993 1989 1991 1995 1990 1989 1985 1986 1990 −1 1 −1 −1 1989 10 10 10 10 1988 1984 1987 1984 1987 1980 0 −2 −2 −2 10 4 3 2 1 10 4 3 2 1 10 4 3 2 1 10 4 3 2 1 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 CMOS Node (nm) CMOS Node (nm) CMOS Node (nm) CMOS Node (nm) Figure 5. Evolution trajectories ( ) for CMOS node and peak sampling rate achieved at fixed minimum resolutions ENOB {4, 8, 12, 14}. Noise-floor limits on fs have been indicated for 12 and 14-b ENOB, assuming the noise floor values in Fig. 4.
  4. 4. never (seen over any full year) improved upon by going below 4 100.65 m. It also shows a trend to degrade with Lmin similar to 1980 state-of-the-art evolution trajectorythat of nr in Fig. 3. This can be explained by nr being thedenominator of F2. The current state-of-the-art [22] from year 2 10 1984 19872000 is therefore not likely to be improved upon in recent and 1986 1988 1990 1991 FOM (pJ)future nanometer technologies. 0 1994 1993 1995 1999 10 1997 2000 1996 2002 2004 VII. CONCLUSIONS −2 10 The influence of CMOS scaling on ADC performance was 2008empirically analyzed using experimental data from a near- state-of-the-art envelopeexhaustive search of scientific publications. It was shown that, −4 10 10000 3000 2000 1000 500 350 250 180 130 90 65 45 32while new CMOS technologies allow higher bandwidths, the CMOS Node (nm)simultaneous combination of SNR and bandwidth is degraded Figure 6. State-of-the-art F1 FOM vs. CMOS node (solid).due to the increase in relative noise floor. High-resolution State-of-the-art trajectory (dashed) illustrates evolution path.ADCs are seriously challenged by CMOS scaling, both withrespect to raw performance and power efficiency. Although 2 10this was an expected result, the study was also able to extract 1980 state-of-the-art evolution trajectoryquantitative noise-floor limits vs. CMOS node based on thelarge number of recorded attempts. Achievable peak sampling 0 10rates at different target resolutions and CMOS nodes were FOM (pJ)estimated from observed noise-floor values, and it was −2 1984 1986 10concluded that high-performance ADCs suitable for LTE and 1987multi-carrier WCDMA infrastructure suffer from CMOS state-of-the-art envelopescaling to the extent that they are unlikely to be implemented 1993 1990 −4 1991 10below 90 nm. 1994 1997 −6 2000 10 ACKNOWLEDGMENT 10000 3000 2000 1000 500 350 250 180 130 90 65 45 32 CMOS Node (nm) The author thanks Dr. Nick Tan of AnaLutions, Inc., Figure 7. State-of-the-art F2 FOM vs. CMOS node (solid).Laguna Niguel, CA, USA, and Tekn. Lic. Per Ingelhag of State-of-the-art trajectory (dashed) illustrates evolution path.Ericsson AB, Gothenburg, Sweden, for many valuablecomments and suggestions. [13] System drivers, International Technology Review for Semiconductors, 2009 Update [Online]. Available: http://www.itrs.net REFERENCES [14] H. Van de Vel, B. Buter, H. van der Ploeg, M. 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