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  • 1. DRV401 SBVS070B − JUNE 2006 − REVISED MAY 2009 Sensor Signal Conditioning IC for Closed-Loop Magnetic Current SensorFEATURES DESCRIPTIOND DESIGNED FOR SENSORS FROM The DRV401 is designed to control and process signals VACUUMSCHMELZE (VAC) from specific magnetic current sensors made byD SINGLE SUPPLY: 5V Vacuumschmelze GmbH & Co. KG (VAC). A variety ofD POWER OUTPUT: H-Bridge current ranges and mechanical configurations areD DESIGNED FOR DRIVING INDUCTIVE LOADS available. Combined with a VAC sensor, the DRV401 monitors both ac and dc currents to high accuracy.D EXCELLENT DC PRECISIOND WIDE SYSTEM BANDWIDTH Provided functions include: probe excitation, signal conditioning of the probe signal, signal loop amplifier, anD HIGH-RESOLUTION, LOW-TEMPERATURE H-bridge driver for the compensation coil, and an analog DRIFT signal output stage that provides an output voltageD BUILT-IN DEGAUSS SYSTEM proportional to the primary current. It offers overload andD EXTENSIVE FAULT DETECTION fault detection, as well as transient noise suppression.D EXTERNAL HIGH-POWER DRIVER OPTION The DRV401 can directly drive the compensation coil, or connect to external power drivers. Therefore, the DRV401APPLICATIONS combines with sensors to measure small to very large currents.D GENERATOR/ALTERNATOR MONITORING AND CONTROL To maintain the highest accuracy, the DRV401 canD FREQUENCY AND VOLTAGE INVERTERS demagnetize (degauss) the sensor at power-up and on demand.D MOTOR DRIVE CONTROLLERSD SYSTEM POWER CONSUMPTIOND PHOTOVOLTAIC SYSTEMS Patents Pending. Compensation RS PWM PWM ICOMP1 ICOMP2 Compensation Winding Primary Winding DRV401 Diff Magnetic Core Amp Field Probe IS2 IP VOUT IS1 REFIN Probe Integrator H−Bridge Interface Filter Driver Timing, Error Detection, VREF Degauss VREF and Power Control +5V GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Products Copyright  2006−2009, Texas Instruments Incorporatedconform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters. www.ti.com
  • 2. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009 This integrated circuit can be damaged by ESD. TexasABSOLUTE MAXIMUM RATINGS(1) Instruments recommends that all integrated circuits beSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V handled with appropriate precautions. Failure to observeSignal Input Terminals: proper handling and installation procedures can cause damage. Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to VDD + 0.5V ESD damage can range from subtle performance degradation to Differential Amplifier(3) . . . . . . . . . . . . . . . . . . . . . . −10V to +10V complete device failure. Precision integrated circuits may be more Current at IS1 and IS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75mA susceptible to damage because very small parametric changes could Current (pins other than IS1 and IS2)(2) . . . . . . . . . . . . . . ±25mA cause the device not to meet its published specifications.ICOMP Short Circuit(4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +250mAOperating Junction Temperature . . . . . . . . . . . . . −50°C to +150°C ORDERING INFORMATION(1)Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C PACKAGE PACKAGEESD Rating: PRODUCT PACKAGE-LEAD DESIGNATOR MARKING Human Body Model (HBM) QFN-20 Pins IAIN1 and IAIN2 Only . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV DRV401 RGW HAAQ (5mm x 5mm) All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV DRV401 SO-20 DWP DRV401A(1) Stresses above these ratings may cause permanent damage. (1) For the most current package and ordering information see the Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and Package Option Addendum at the end of this document, or see functional operation of the device at these or any other conditions the TI web site at www.ti.com. beyond those specified is not supported.(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must be current limited, except for the differential amplifier input pins.(3) These inputs are not internally protected against over voltage. The differential amplifier input pins must be limited to 5mA, max or ±10V, max.(4) Power-limited; observe maximum junction temperature.2
  • 3. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009ELECTRICAL CHARACTERISTICSBoldface limits apply over the specified temperature range: TJ = −40°C to +125°C.At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, and zero output current ICOMP, unless otherwise noted. DRV401 PARAMETER CONDITIONS MIN TYP MAX UNITSDIFFERENTIAL AMPLIFIER RL = 10kΩ to 2.5V, VREFIN = 2.5VOFFSET VOLTAGEOffset Voltage, RTO(1)(2) VOS Gain 4V/V ±0.01 ±0.1 mV Drift, RTO(2) dVOS/dT ±0.1 ±1(3) µV/°C vs Common-Mode, RTO CMRR −1V to +6V, VREF = 2.5V ±50 ±250 µV/V vs Power-Supply, RTO PSRR VREF not included ±4 ±50 µV/VSIGNAL INPUTCommon-Mode Voltage Range −1 (VDD) + 1 VSIGNAL OUTPUTSignal Over-Range Indication (OVER-RANGE), Delay(2) VIN = 1V Step, See Notes 2 and 3 2.5 to 3.5 µsVoltage Output Swing From Negative Rail(2), I = +2.5mA, CMP Trip Level +48 +85 mV OVER-RANGE Trip LevelVoltage Output Swing From Positive Rail(2), I = −2.5mA, CMP Trip Level VDD − 85 VDD − 48 mV OVER-RANGE Trip LevelShort-Circuit Current(2) ISC VOUT Connected To GND −18 mA VOUT Connected To VDD +20 mAGain, VOUT/VIN_DIFF 4 V/VGain Error ±0.02 ±0.3 %Gain Error Drift ±0.1 ppm/°CLinearity Error RL = 1kΩ 10 ppmFREQUENCY RESPONSEBandwidth(2) BW−3dB 2 MHzSlew Rate(2) SR CMVR = −1V to = +4V 6.5 V/µsSettling Time, Large-Signal(2) dV ± 2V to 1%, No External Filter 0.9 µsSettling Time(2) dV ± 0.4V to 0.01% 14 µsINPUT RESISTANCEDifferential 16.5 20 23.5 kΩCommon-Mode 41 50 59 kΩExternal Reference Input 41 50 59 kΩNOISEOutput Voltage Noise Density, f = 1kHz, RTO(2) en Compensation Loop Disabled 170 nV/√HzCOMPENSATION LOOPDC STABILITY Probe f = 250kHz, RLOAD = 20ΩOffset Error(4) Deviation from 50% PWM, Pin Gain = L 0.03 %Offset Error Drift(2) Deviation from 50% PWM, Pin Gain = L 7.5 ppm/°CGain, Pin Gain = L(2) |VICOMP1| − |VICOMP2| −200 25 200 ppm/VPower-Supply Rejection Ratio PSRR Probe Loop f = 250kHz 500 ppm/VFREQUENCY RESPONSEOpen-Loop Gain, Two Modes, 7.8kHz Pin Gain H/L 24/32 dBPROBE COIL LOOPInput Voltage Clamp Range Field Probe Current < 50mA −0.7 to VDD + 0.7 VInternal Resistor, IS1 or IS2 to VDD1(2) RHIGH 47 59 71 ΩInternal Resistor, IS1 or IS2 to GND1(2) RLOW 60 75 90 ΩResistance Mismatch Between IS1 and IS2(2) ppm of RHIGH + RLOW 300 1500 ppmTotal Input Resistance(3) 134 200 WComparator Threshold Current(3) 22 28 34 mAMinimum Probe Loop Half-Cycle(2) 250 280 310 nsProbe Loop Minimum Frequency 250 kHzNo Oscillation Detect (Error) Suppression 35 µsCOMPENSATION COIL DRIVER, H-BRIDGEPeak Current(2) VICOMP1 − VICOMP2 = 4.0VPP 250 mAVoltage Swing 20Ω Load 4.2 VPPOutput Common-Mode Voltage VDD2/2 VWire Break Detect, Threshold Current(5) ICOMP1 and ICOMP2 Railed 33 57 mA 3
  • 4. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009ELECTRICAL CHARACTERISTICS (continued)Boldface limits apply over the specified temperature range, TJ = −40°C to +125°C, with zero output current ICOMP.At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. DRV401 PARAMETER CONDITIONS MIN TYP MAX UNITSVOLTAGE REFERENCEVoltage(2) No Load 2.495 2.5 2.505 V Drift(2) No Load ±5 ±50 ppm/°CPSRR(2) ±15 ±200 µV/VLoad Regulation(2) Load to GND/VDD, dI = 0mA to 5mA 0.15 mV/mAShort-Circuit Current ISC REFOUT Connected to VDD +20 mA REFOUT Connected to GND −18 mADEMAGNETIZATIONDuration See Timing Diagram 106 130(3) msDIGITAL I/OLOGIC INPUTS (DEMAG, GAIN, and CCdiag Pins) CMOS Type LevelsPull-Up High Current (CCdiag) 3.5 < VIN < VDD 160 µAPull-Up Low Current (CCdiag) 0 < VIN < 1.5 5 µALogic Input Leakage Current 0 < VIN < VDD 0.01 5 µALogic Level, Input: L/H 2.1/2.8 V Hysteresis 0.7 VOUTPUTS (ERROR AND OVER-RANGE Pins)Logic Level, Output: L 4mA Sink 0.3 VLogic Level, Output: H No Internal Pull-UpOUTPUTS (PWM and PWM Pins) Push-Pull TypeLogic Level L 4mA Sink 0.2 VLogic Level H 4mA Source (VDD) − 0.4 VPOWER SUPPLYSpecified Voltage Range VDD 4.5 5 5.5 VPower-On Reset Threshold VRST 1.8 VQuiescent Current [I(VDD1) + I(VDD2)] IQ ICOMP = 0mA, Sensor Not Connected 6.8 mABrownout Voltage Level(2) 4 VBrownout Indication Delay 135 µsTEMPERATURE RANGESpecified Range TJ −40 +125 °COperating Range TJ −50 +150 °CPackage Thermal Resistance QFN Surface-Mount qJA See Note 6 40 °C/W SO PowerPAD Surface-Mount qJA See Note 6 27 °C/W(1) Parameter value referred to output (RTO).(2) See Typical Characteristic curves.(3) Total input resistance and comparator threshold current are inversely related. See Figure 2a.(4) For VAC sensors, 0.2% of PWM offset approximately corresponds to 10mA primary current offset per winding.(5) See Compensation Driver section in Applications Information.(6) See Applications Information section for information on power dissipation, layout considerations, and proper PCB soldering and heat-sinking technique.4
  • 5. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009PIN CONFIGURATIONSTop View RGW Top View DWP GND1 PWM PWM PWM 1 20 IS1 IS1 IS2 PWM 2 19 GND1 20 19 18 17 16 ERROR 3 18 IS2 ERROR 1 15 VDD1 DEMAG 4 17 VDD1 DEMAG 2 Exposed 14 OVER−RANGE Exposed Thermal Pad GAIN 5 Thermal Pad 16 OVER−RANGE GAIN 3 on Underside, 13 CCdiag on Underside, Connect REFOUT 6 Connect 15 CCdiag REFOUT 4 to GND1 12 VDD2 to GND1 REFIN 7 14 VDD2 REFIN 5 11 ICOMP1 VOUT 8 13 ICOMP1 10 6 7 8 9 IAIN2 9 12 ICOMP2 VOUT IAIN2 IAIN1 ICOMP2 GND2 IAIN1 10 11 GND2 QFN−20 (5mm x 5mm) Wide−Body SO−20 PIN ASSIGNMENTS NAME RGW DWP DESCRIPTION ERROR 1 3 Error flag: open-drain output, see the Error Conditions section. DEMAG 2 4 Control input, see the Demagnetization section. GAIN 3 5 Control input for open-loop gain: low = normal, high = −8dB. REFOUT 4 6 Output for internal 2.5V reference voltage. REFIN 5 7 Input for zero reference to differential amplifier. VOUT 6 8 Output for differential amplifier. IAIN2 7 9 Noninverting input of differential amplifier. IAIN1 8 10 Inverting input of differential amplifier. GND2 9 11 Ground connection. Connect to GND1. ICOMP2 10 12 Output 2 of compensation coil driver. ICOMP1 11 13 Output 1 of compensation coil driver. VDD2 12 14 Supply voltage. Connect to VDD1. CCdiag 13 15 Control input for wire-break detection: high = enable. OVER−RANGE 14 16 Open-drain output for over-range indication: low = over-range. VDD1 15 17 Supply voltage. IS2 16 18 Probe connection 2. GND1 17 19 Ground connection. IS1 18 20 Probe connection 1. PWM 19 1 PWM output from probe circuit (inverted). PWM 20 2 PWM output from probe circuit.Exposed Thermal Pad — — Connect to GND1. 5
  • 6. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009TYPICAL CHARACTERISTICSAt TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. DRV401 AND SENSOR: DRV401 AND SENSOR: OUTPUT VOLTAGE NOISE DENSITY OFFSET vs SUPPLY VOLTAGE (Sensor M4645−X080, RSHUNT = 10Ω, Mode = Low) 0.04 100 0.03 60Hz Line Frequency and Multiples (measured in a 60Hz environment) 0.02 M4645−X211 M4645−X211 VN (µV/√Hz) 0.01 Divided FieldIPRIM (A) Probe Frequency 0 10 M4645−X080 −0.01 −0.02 −0.03 −0.04 0.1 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 0.1 1 10 100 1k 10k 100k VDD (V) Frequency (Hz) DRV401 AND SENSOR: ABSOLUTE ERROR (Soldered DWP−20 with 1 Square−Inch Copper Pad) GAIN FLATNESS vs FREQUENCY (Measurements by Vacuumschmelza GmbH) (Measurements by Vacuumschmelze GmbH) 0.3 1.20 T = −50_ C DRV401 with M4645−X600 Sensor T = +25_C 1.15 DRV401 with M4645−X211 Sensor 0.2 T = +85_C DRV401 with M4645−X080 Sensor T = +125_ C 1.10 Absolute Error (A) Normalized Gain 0.1 1.05 0 1.00 0.95 −0.1 0.90 −0.2 0.85 TC (RSHUNT) ±25ppm/_ C. −0.3 0.80 −300 −200 −100 0 100 200 300 10 100 1k 10k 100k 1M Primary Current (A) Frequency (Hz) DIFFERENTIAL AMPLIFIER: 3A ICOMP OVERLOAD RECOVERY VOLTAGE OFFSET PRODUCTION DISTRIBUTION (Measurements by Vacuumschmelze GmbH) RTO Over−RangeOver−Range Population VOUT 2000A/div 2V/div VOUT ERROR ERROR IPRIM IPRIM NOTE: IPRIM = 3000A corresponds to ICOMP = 3A. −50 −45 −40 −35 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 160 180 200 Time (µs) Voltage Offset (µV)6
  • 7. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009TYPICAL CHARACTERISTICS (Continued)At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. DIFFERENTIAL AMPLIFIER: DIFFERENTIAL AMPLIFIER: OFFSET VOLTAGE vs TEMPERATURE, RTO GAIN vs FREQUENCY 20 20 16 15 12 10 8 Input VOS (µV) 5 Gain (dB) 4 Sample Average 0 0 −4 −5 −8 −10 −12 −16 −15 −20 −20 −50 −25 0 25 50 75 100 125 150 10 100 1k 10k 100k 1M 10M Temperature (_C) Frequency (Hz) DIFFERENTIAL AMPLIFIER: DIFFERENTIAL AMPLIFIER: PSRR AND CMRR vs FREQUENCY OUTPUT VOLTAGE vs OUTPUT CURRENT 120 5.0 PSRR −40_ C +25_C 100 4.9 +125_ C PSRR and CMRR (dB) 4.8 Output Voltage (V) CMRR 80 +85_ C 4.7 60 0.3 +125_C +85_C 40 0.2 20 0.1 +25_ C −40_C 0 0 10 100 1k 10k 100k 1M 2M 0 1 2 3 4 5 6 7 8 9 10 Frequency (Hz) Load Current (mA) DIFFERENTIAL AMPLIFIER: DIFFERENTIAL AMPLIFIER: OUTPUT NOISE DENSITY SHORT−CIRCUIT CURRENT vs TEMPERATURE 1000 25 VOUT Shorted to 5V 20 Short−Circuit Current (mA) 15 Noise Density (nV/√Hz) 10 5 100 0 −5 −10 Autozero Frequency = 69kHz −15 Sensor Not Running −20 en = 162nV/√Hz (average over 250Hz to 50kHz) VOUT Shorted to 0V 10 −25 100 1k 10k 100k 1M −50 −25 0 25 50 75 100 125 150 Frequency (Hz) Temperature (_ C) 7
  • 8. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009TYPICAL CHARACTERISTICS (Continued)At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. DIFFERENTIAL AMPLIFIER: DIFFERENTIAL AMPLIFIER: TA = −50_C LARGE−SIGNAL STEP RESPONSE TA = +25_C LARGE−SIGNAL STEP RESPONSE 3.8 3.8 3.6 3.6 3.4 3.4 3.2 3.2 3.0 3.0 Voltage (V) Voltage (V) 2.8 2.8 2.6 2.6 2.4 2.4 2.2 2.2 2.0 2.0 1.8 1.8 1.6 1.6 1.4 1.4 1µs/div 1µs/div DIFFERENTIAL AMPLIFIER: DIFFERENTIAL AMPLIFIER: TA = +150_C LARGE−SIGNAL STEP RESPONSE OVER−RANGE DELAY vs TEMPERATURE 3.8 3.5 At 5.0V 3.6 3.4 VIN Step 0V to ±1V 3.4 3.3 Over−Range Delay (µs) 3.2 3.0 3.2 Negative Over−Range Voltage (V) 2.8 3.1 2.6 3.0 2.4 2.9 2.2 Positive Over−Range 2.8 2.0 2.7 1.8 1.6 2.6 1.4 2.5 1µs/div −50 −25 0 25 50 75 100 125 150 Temperature (_ C) DIFFERENTIAL AMPLIFIER: DIFFERENTIAL AMPLIFIER: POSITIVE SLEW RATE vs TEMPERATURE NEGATIVE SLEW RATE vs TEMPERATURE 7.5 −6.5 At 5.0V At 5.0V 7.4 −6.6 7.3 −6.7 7.2 −6.8 Slew Rate (V/µs) Slew Rate (V/µs) 7.1 −6.9 7.0 −7.0 6.9 −7.1 6.8 −7.2 6.7 −7.3 6.6 −7.4 6.5 −7.5 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 Temperature (_ C) Temperature (_ C)8
  • 9. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009TYPICAL CHARACTERISTICS (Continued)At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. DIFFERENTIAL AMPLIFIER: COMPENSATION LOOP: REFIN RESISTANCE vs TEMPERATURE SMALL−SIGNAL GAIN Gain VPWMAVERAGE /(VICOMP1, VICOMP2) (dB) 50.250 70 60 50.125 50 RREF IN (kΩ ) Pin Gain = Low 50.000 40 Pin Gain = High 49.875 30 20 49.750 10 49.625 0 −50 −25 0 25 50 75 100 125 150 100 1k 10k 100k Temperature (_ C) Frequency (Hz) COMPENSATION LOOP: COMPENSATION LOOP: DUTY CYCLE ERROR vs TEMPERATURE DC GAIN: DUTY CYCLE ERROR CHANGE 2000 VICOMP1 − VICOMP2 = 4.2V 1500 ILOAD = 210mA Gain Pin Low Duty Cycle Error (ppm) 1000 500 Population 0 At 250kHz, 5.0V −500 −1000 At 400kHz, 5.0V −1500 −2000 −50 −25 −200 −180 −160 −140 −120 −100 −80 −60 −40 −20 0 25 50 75 100 125 150 0 20 40 60 80 100 120 140 160 180 200 Temperature (_ C) Gain (ppm/V) ICOMP OUTPUT SWING TO RAIL PROBE COMPARATOR THRESHOLD vs OUTPUT CURRENT CURRENT vs TEMPERATURE Probe Comparator Threshold Current (mA) 5.00 35.0 4.75 +125_C +25_ C −50_ C 4.50 32.5 Output Swing (V) 4.25 4.00 30.0 1.00 0.75 0.50 27.5 +125_C +25_ C −50_ C 0.25 0 25.0 0 50 100 150 200 250 300 −50 −25 0 25 50 75 100 125 150 Output Current (mA) Temperature (_ C) 9
  • 10. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009TYPICAL CHARACTERISTICS (Continued)At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. PROBE DRIVER: OUTPUT IMPEDANCE MISMATCH OF IS1 AND IS2 INTERNAL RESISTOR vs TEMPERATURE vs TEMPERATURE 90 0.10 Output Impedance Mismatch (Ω ) 85 80 0.08 Driver L 75 Resistance (Ω) 0.06 70 65 0.04 60 Driver H 55 0.02 50 45 0 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 Temperature (_ C) Temperature (_ C) VOLTAGE REFERENCE vs LOAD CURRENT VOLTAGE REFERENCE PRODUCTION DISTRIBUTION 2.5010 2.5008 2.5006 2.5004 Population 2.5002 VREF (V) 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 −6 −4 −2 0 2 4 6 2.4950 2.4955 2.4960 2.4965 2.4970 2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 2.5025 2.5030 2.5035 2.5040 2.5045 2.5050 ILOAD (mA) VREF (V) VOLTAGE REFERENCE DRIFT PRODUCTION DISTRIBUTION VOLTAGE REFERENCE vs TEMPERATURE 2.525 2.520 2.515 2.510 Population 2.505 VREF (V) 2.500 2.495 2.490 2.485 2.480 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 40.0 42.5 45.0 47.5 50.0 2.475 −50 −25 0 25 50 75 100 125 150 Voltage Reference Drift (ppm/_ C) Temperature (_ C)10
  • 11. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009TYPICAL CHARACTERISTICS (Continued)At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. VOLTAGE REFERENCE POWER−SUPPLY REJECTION PRODUCTION DISTRIBUTION OSCILLATOR PRODUCTION DISTRIBUTION Population Population 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 −200 −175 −150 −125 −100 −75 −50 −25 0 25 50 75 100 125 150 175 200 PSR (µV/V) Minimum Probe Loop Half−Cycle (ns) OSCILLATOR vs TEMPERATURE OSCILLATOR vs SUPPLY VOLTAGE 310 310 Minimum Probe Loop Half−Cycle (ns) Minimum Probe Loop Half−Cycle (ns) 305 305 300 300 295 295 290 290 285 285 280 280 275 275 270 270 265 265 260 260 255 255 250 250 −50 −25 0 25 50 75 100 125 150 4.3 4.6 4.9 5.2 5.5 5.8 6.0 Temperature (_C) VDD (V) BROWN−OUT VOLTAGE vs TEMPERATURE 4.20 4.15 Brown−Out Voltage (V) 4.10 4.05 4.00 3.95 3.90 3.85 3.80 −50 −25 0 25 50 75 100 125 150 Temperature (_ C) 11
  • 12. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009 probe delivers the signal to the amplifier that drives theAPPLICATIONS INFORMATION current through the compensation coil, bringing the magnetic flux back to zero. This compensation current isFUNCTIONAL PRINCIPLE OF CLOSED-LOOP proportional to the primary current, relative to the windingCURRENT SENSORS WITH MAGNETIC ratio.PROBE USING THE DRV401 In higher frequency ranges, the compensation windingClosed-loop current sensors measure current over wide acts as the secondary winding in the current transformer,frequency ranges, including dc. These types of devices while the H-bridge compensation driver is rolled off andoffer a contact-free method as well as excellent galvanic provides low output impedance.isolation performance combined with high resolution,accuracy, and reliability. A difference amplifier senses the voltage across a small shunt resistor that is connected to the compensation loop.At dc and in low-frequency ranges, the magnetic field This difference amplifier generates the output voltage thatinduced from the current in the primary winding is is referenced to REFIN and is proportional to the primarycompensated by a current flowing through a current. Figure 1 shows the DRV401 used as acompensation winding. A magnetic field probe, located in compensation current sensor.the magnetic core loop, detects the magnetic flux. This Compensation RS ICOMP1 ICOMP2 Compensation Winding Primary Winding DRV401 Diff Magnetic Core Amp Field Probe IS2 IP VOUT IS1 REFIN Probe Integrator H−Bridge Interface Filter Driver Timing, Error Detection, VREF Degauss VREF and Power Control +5V GND Figure 1. Principle of Compensation Current Sensor with the DRV40112
  • 13. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009FUNCTIONAL DESCRIPTION The probe core reaches saturation at a current of typically 28mA (see Figure 2a). The comparator is connected toThe DRV401 operates from a single +5V supply. It is a VREF by approximately 0.5V. A current comparator detectscomplete sensor signal conditioning circuit that directly the saturation and inverts the excitation voltage polarity,connects to the current sensor, providing all necessary causing the probe circuit to oscillate in a frequency rangefunctions for the sensor operation. The DRV401 provides of 250kHz to 550kHz. The oscillating frequency is amagnetic field probe excitation, signal conditioning, and function of the magnetic properties of the probe core andcompensation coil driver amplification. In addition, it its coil.detects error conditions and handles overload situations.A precise differential amplifier allows translation of the The current rise rate is a function of the coil inductance:compensation current into an output voltage using a small dI = L × V × dT. However, the inductance of the field probeshunt resistor. A buffered voltage reference can be used is low while its core material is in saturation (the horizontalfor comparator, analog-to-digital converter (ADC), or part of the hysteresis curve) and is high at the vertical partbipolar zero reference voltages. of the hysteresis curve. The resulting inductance and the series resistance determine the output voltage and currentDynamic error correction ensures high dc precision over versus time performance characteristic.temperature and long-term accuracy. The DRV401 usesanalog signal conditioning; the internal loop filter and Without external magnetic influence, the duty cycle isintegrator are switched capacitor-based circuits. exactly 50% because of the inherent symmetry of theTherefore, the DRV401 allows combination with magnetic hysteresis; the probe inductor is driven from −Bhigh-precision sensors for exceptional accuracy and saturation through the high inductance range to +Bresolution. The typical characteristic curve, DRV401 and saturation and back again in a time-symmetric mannerSensor Linearity, shows an example of the linearity and (see Figure 2b).temperature stability achieved by the device. If the core material is magnetized in one direction, a longA demagnetization cycle can be initiated on demand or on and a short charge time result because the probe currentpower-up. This cycle reduces offset and restores high through the inductors generates a field that eitherperformance after a strong overload condition. An internal subtracts or adds to the flux in the probe core, either drivingclock and counter logic generate the degauss function. the probe core out of saturation or further into saturationThe same clock controls power-up, overload detection and (see Figure 2c). The current into the probe is limited by therecovery, error, and time-out conditions. voltage drops across the probe driver resistors.The DRV401 is built on a highly reliable CMOS process. The DRV401 continuously monitors the logic magnetic fluxUnique protection cells at critical connections enable the polarity state. In the case of distortion noise and excessivedesign to handle inductive energy. overload that could fully saturate the probe, the overload control circuit recovers the probe loop. During an overload condition, the probe oscillation frequency increases toMAGNETIC PROBE (SENSOR) INTERFACE approximately 1.6MHz until limited by the internal timing control.The magnetic field probe consists of an inductor wound on In an overload condition, the compensation current (ICOMP)a soft magnetic core. The probe is connected between driver cannot deliver enough current into the sensorpins IS1 and IS2 of the probe driver that applies secondary winding, and the magnetic flux in the sensorapproximately +5V (the supply voltage) through resistors main core becomes uncompensated.across the probe coil (see Figure 2a). 13
  • 14. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009 VDD1 Probe 55Ω 55Ω IS2 IS1 18Ω CMP PWM VREF = 0.5V NOTE: MOS components function as switches only. a) Simplified probe interface circuit. The probe is connected between S1 and S2. B B H H 2V/div 2V/div V (IS1) V (IS1) 500mV/div 500mV/div V (PWM)/10 V (PWM)/10 500ns/div 500ns/div b) Without an external magnetic field, the hysteresis curve is c) An external magnetic flux (H) generated from the primary current symmetrical and the probe loop generates 50% duty cycle. (IPRIM) shifts the hysteresis curve of the magnetic field probe in the H-axis and the probe loop generates a nonsymmetrical duty cycle. Figure 2. Magnetic Probe, Hysteresis, and Duty Cycle14
  • 15. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009The transition from normal operation to overload happens protected against coupled energy from the magnetic core.relatively slowly, because the inherent sensor transformer Wiring between probe and IC inputs should be short andcharacteristics induce the initial primary current step, as guarded against interference; see Layout Considerations.shown in Figure 3. As the transformer-induced secondary For reliable operation, error detection circuits monitor thecurrent starts to decay, the compensation feedback driver probe operation:increases its output voltage to maintain the sensor coreflux compensation at zero. 1. If the probe driver comparator (CMP) output stays lowWhen the system compensation loop reaches its driving longer than 32µs, the ERROR flag asserts active, andlimit, the rising magnetic flux causes one of the probe the compensation current (ICOMP) is set to zero.PWM half-periods to become shorter. The minimum 2. If the probe driver period is less than 275ns on threehalf-period of the probe oscillation is limited by the internal consecutive pulses, the ERROR flag asserts active.timing to 280ns, based on the properties of the VAC See the Error Conditions section for more details.magnetic sensors. After three consecutive cycles of thesame half-period being shorter than 280ns, the DRV401goes into overload-latch mode. The device stores the PWM PROCESSINGICOMP driver output signal polarity and continues producingthe skewed-duty cycle PWM signal. This action prevents The outputs PWM and PWM represent the probe outputthe loss of compensation signal polarity information during signal as a differential PWM signal. It can drive externalvery strong overloads. In this case, both PWM half-periods circuitry or be used for synchronous ripple reduction. Theare short and approximately equal, because the field PWM signal from the probe excitation and sense stage isprobe stays completely in one of the saturated regions. internally connected to a high-performance,The overload-latch condition is removed after the primary switched-capacitor integrator followed by ancurrent goes low enough for the ICOMP driver to integrating-differentiating filter. This filter converts thecompensate, and both half-periods of the probe driver PWM signal into a filtered delta signal and prepares it foroscillation become longer than 280ns (the field probe driving the analog compensation coil driver. The gaincomes out of the saturated region). roll-off frequency of the filter stage is set to provide high dcPeak voltages and currents can be generated during gain and loop stability. If additional gain is added fromnormal operations as well as overload conditions. external circuitry, the internal gain can be reduced by 8dB,Therefore, both probe connection pins are internally asserting the GAIN pin high (see the External Compensation Coil Driver section). Sensor: 4 x 100 V(1Ω× IPRIM/10) RSH = 10Ω 1 I COMP1 Step Response 2kHz In 3 V(Gain) = Low 4 ICOMP2 Channel 1: 2V/div Channels 2−4: 500mV/div VOUT 2 50µs/div A current pulse of 0A to 18A (Ch 1) generates the two ICOMP signals (Ch 3 and Ch 4). Ch 2 shows the resulting output signal, VOUT. This test uses the M4645-X030 sensor, no bandwidth limitation, but a 20-sample average. Figure 3. Primary Current Step Response 15
  • 16. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009COMPENSATION DRIVER For sensors with high winding resistance (compensation coil resistance + RSHUNT) or connected to an externalThe compensation coil driver provides the driving current compensation driver, this function should be disabled byfor the compensation coil. A fully differential driver stage pulling the CCdiag pin low.offers high signal voltages to overcome the wire resistance V OUTof the coil with only +5V supply. The compensation coil is R MAX +connected between ICOMP1 and ICOMP2, both generating an 65mA (1)analog voltage across the coil (see Figure 3) that turns into Where:current from the wire resistance (and eventually from theinductance). The compensation current represents the VOUT equals the peak voltage between ICOMP1 and ICOMP2primary current transformed by the turns ratio. A shunt at a 65mA drive current.resistor is connected in this loop and the high-precision RMAX equals the sum of the coil and the shunt resistance.difference amplifier translates the voltage from this shuntto an output voltage.Both compensation driver outputs provide low impedance EXTERNAL COMPENSATION COIL DRIVERover a wide frequency range to insure smooth transitions An external driver for the compensation coil can bebetween the closed-loop compensation frequency range connected to the ICOMP1 and ICOMP2 outputs. To prevent aand the high-frequency range, where the primary winding wire break indication, CCdiag has to be asserted low.directly couples the primary current into the compensationcoil at a rate set by the winding ratio. An external driver can provide both a higher drive voltage and more drive current. It also moves the powerThe two compensation driver outputs are designed with dissipation to the external transistors, thereby allowing aprotection circuitry to handle inductive energy. However, higher winding resistance in the compensation coil andadditional external protection diodes might be necessary more current. Figure 4 shows a block diagram of anfor high current sensors. external compensation coil driver. To drive the buffer,For reliable operation, a wire break in the compensation either one or both ICOMP outputs can be used. Note,circuit can be detected. If the feedback loop is broken, the however, that the additional voltage gain could causeintegrating filter drives the outputs ICOMP1 and ICOMP2 to the instability of the loop. Therefore, the internal gain can beopposite rails. With one of these pins coming within 300mV reduced by approximately 8dB by asserting the GAIN pinto ground, a comparator tests for a minimum current flowing high. RSHUNT is connected to GND to allow for abetween ICOMP1 and ICOMP2. If this current stays below the single-ended external compensation driver. Thethreshold current level for at least 100µs, the ERROR pin is differential amplifier can continue to sense the voltage,asserted active (low). The threshold current level for this test and used for the gain and over-range comparator oris less than 57mA at 25°C and 65mA at −40°C, if the ICOMP ERROR flag.pins are fully railed (see the Typical Characteristics). V+ DRV401 ICOMP1 External Buffer Compensation ICOMP2 Coil RSHUNT V− Figure 4. DRV401 with External Compensation Coil Driver and RSHUNT Connected to GND16
  • 17. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009SHUNT SENSE AMPLIFIER Typically, the gain error resulting from the resistance of RSHUNT is negligible; for 70dB of common-mode rejection,The differential (H-bridge) driver arrangement for the however, the match of both divider ratios needs to be bettercompensation coil requires a differential sense amplifier than 1/3000.for the shunt voltage. This differential amplifier offers widebandwidth and a high slew rate for fast current sensors. The amplifier output can drive close to the supply rails, andExcellent dc stability and accuracy result from an is designed to drive the input of a SAR-type ADC; addingauto-zero technique. The voltage gain is 4V/V, set by an RC low-pass filter stage between the DRV401 and theprecisely matched and stable internal SiCr resistors. ADC is recommended. This filter not only limits the signal bandwidth but also decouples the high-frequencyBoth inputs of the differential amplifier are normally component of the converter input sampling noise from theconnected to the current shunt resistor. This resistor adds amplifier output. For RF and CF values, refer to the specificto the internal (10kΩ) resistor, slightly reducing the gain in converter recommendations in the specific product datathis leg. For best common-mode rejection (CMR), a sheet. Empirical evaluation may be necessary to obtaindummy shunt resistor (R5) is placed in series with the optimum results.REFIN pin to restore matching of both resistor dividers, asshown in Figure 5a. The output can drive 100pF directly and shows 50% overshoot with approximately 1nF capacitance. Adding RFFor gains of 4V/V: allows much larger capacitive loads, as shown in R2 R4 ) R5 Figure 5b and Figure 5c. Note that with RF of only 20Ω, the 4+ + load capacitor should be either smaller than 1nF or larger R1 RSHUNT ) R3 (2) than 33nF to avoid overshoot; with RF of 50Ω this transientWith R2/R1 = R4/R3 = 4; R5 = RSHUNT × 4 area is avoided. ICOMP2 DRV401 Differential Amplifier Section R1 R2 10kΩ 40kΩ Decoupling, Low−Pass Filter RF 50Ω VOUT R SHUNT ADC CF Differential 10nF Amplifier R5 R3 R4 Dummy 10kΩ 40kΩ REFIN Shunt Compensated REFIN NOTE: R5 is a dummy shunt resistor equal to 4x RSHUNT to compensate for RSHUNT and provide best CMR. K2 a) Internal difference amplifier with an example of a decoupling filter. 20mV/div 20mV/div 10µs/div 10µs/div b) VOUT of Figure 5a with R5 = 20Ω and CD = 100nF. c) VOUT of Figure 5a with R5 = 50Ω and CD = 10nF. Figure 5. Internal Difference Amplifier with Example of a Decoupling Filter 17
  • 18. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009The reference input (REFIN) is the reference node for the The over-range condition is internally detected as soon asexact output signal (VOUT). Connecting REFIN to the the amplifier exceeds its linear operating range, not just areference output (REFOUT) results in a live zero reference set voltage level. Therefore, the error or the over-rangevoltage of 2.5V. Using the same reference for REFIN and comparator level is reliably indicated in fault conditionsthe ADC avoids mismatch errors that exist between two such as output shorts, low load or low supply conditions.reference sources. As soon as the output cannot drive the voltage higher, the flag is activated. This configuration is a safety improvement over a voltage level comparator.OVER-RANGE COMPARATOR NOTE: The internal resistance of the compensation coilHigh peak current can overload the differential amplifier may prevent high compensation current from flowingconnected to the shunt. The OVER-RANGE pin, an because of ICOMP driver overload. Therefore, theopen-drain output, indicates an over-voltage condition for differential amplifier may not overload with this current.the differential amplifier by pulling low. The output of this However, a fast rate of change of the primary current wouldflag is suppressed for 3µs, preventing unwanted triggering be transmitted through transformer action and safelyfrom transients and noise. This pin returns to high as soon trigger the overload flag.as the overload condition is removed (external pull-uprequired to return the pin high). VOLTAGE REFERENCEThis ERROR flag not only provides a warning about asignal clipping condition, but is also a window comparator The precision 2.5V reference circuit offers low driftoutput for actively shutting off circuits in the system. The (typically 10ppm/K) and is used for internal biasing; it isvalue of the shunt resistor defines the operating window for also connected to the REFOUT pin. The circuit is intendedthe current. It sets the ratio between the nominal signal and as the reference point of the output signal to allow a bipolarthe trip level of the Over-Range flag. The trip current of this signal around it. This output is buffered for low impedancewindow comparator is calculated using the following and tolerates sink and source currents of ±5mA.example: Capacitive loads can be directly connected, but generate ringing on fast load transients. A small series resistor of a With a 5V supply, the output voltage swing is few ohms improves the response, especially for a approximately ±2.45V (load and supply capacitive load in the range of 1µF. Figure 6 shows the voltage-dependent). transient load regulation with 1nF direct load. The gain of 4V/V allows an input swing of ±0.6125V. The reference source is part of the integrated circuit and Thus, the clipping current is IMAX = 0.6125V/RSHUNT. referenced to GND2. Large current pulses driving the compensation coil can generate a voltage drop in the GNDSee the differential amplifier curve of the Typical connection that would add on to the reference voltage.Characteristics, Output Voltage vs Output Current. Therefore, a low impedance GND layout is critical to handle the currents and the high bandwidth of this IC. Test Circuit: 10kΩ REFOUT 10mV/div 1nF ±5V +2.5V 2.5µs/div Figure 6. Pulse Response Test Circuit and Scope Shot of Reference18
  • 19. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009DEMAGNETIZATION power-up. If no probe error conditions are detected within four full cycles (that is, the probe half-periods are shorterIron cores are not immune to residual (remanence) than 32µs and longer than 280ns), the compensationmagnetism. The residual remanence can produce a signal driver starts and the ERROR pin indicates the readyoffset error, especially after strong current overload, which condition by going high, typically about 42µs aftergoes along with high magnetic field density. Therefore, the power-up.DRV401 includes a signal generator for a demagnetizationcycle. The digital control pin, DEMAG, starts this cycle on NOTE: an external pull-up resistor is required to pull thedemand after this pin is held high for at least 25.6µs. ERROR pin high.Shorter pulses are ignored. The cycle lasts for Both supply pins (VDD1 and VDD2) should not differ by moreapproximately 110ms. During this time, the Error flag is than 100mV for proper device operation. They areasserted low to indicate that the output is not valid. When normally connected together or separately filtered (seeDEMAG is high during power-on, a demagnetization cycle Layout Considerations).immediately initiates (12µs) after power-on (VDD > 4V).Holding DEMAG low avoids this cycle at power-up (see The DRV401 tests for low supply voltage with a brown-outthe Power-On and Brownout section). voltage level of +4V; proper power conditions must be supplied. Good power-supply and low ESR bypassThe probe circuit is in normal operation and oscillates capacitors are required to maintain the supply voltageduring the demagnetization cycle. The outputs PWM and during the large current pulses that the DRV401 can drive.PWM are active accordingly. A critical voltage level is derived from the proper operationA demagnetization cycle can be aborted by pulling of the probe driver. The probe interface relies on a peakDEMAG low, filtered by 25µs to ignore glitches (see current flowing through the probe to trip the comparator.Figure 7). In a typical circuit, the DEMAG pin may be The probe resistance plus the internal resistance of theconnected to the positive supply, which enables a degauss driver (see Electrical Characteristics specification, Probecycle every time the unit is powered on. Coil Loop, Internal Resistor) sets the lower limit for theThe degauss cycle is based on an internal clock and acceptable supply voltage. Voltage drops lasting less thancounter logic. The maximum current is limited by the 31µs are ignored. The probe error detection activates theresistance of the connected coil in series with the shunt ERROR pin as soon as proper oscillation fails for moreresistor. The DEMAG logic input requires a +5V than 32µs.CMOS-compatible signal. A low supply voltage condition, or brown-out, is detected at +4V. Short and light voltage drops of less than 100µs are ignored, provided the probe circuit continues to operate. IfPOWER-ON AND BROWNOUT the probe no longer operates, the ERROR pin goes active. Signal overload recovery is only provided if the probe loopPower-on is detected with the supply voltage going higher was not discontinued.than 4V at VDD1. When DEMAG is high, a degauss cycleis started (see Figure 7a). During this time the ERROR flag A supply drop lasting longer than 100µs generatesremains low, indicating the not ready condition. power-on reset. A voltage dip down to +1.8V (for VDD1)Maintaining DEMAG low prevents this cycle, and the also initiates a power-on reset.DRV401 starts operation approximately 32µs after 19
  • 20. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009 VDD1 1 106ms V(ERROR) 5V/div 4 V(ICOMP2) RSH = 10Ω 2V/div 2 VOUT 3 20ms/div a) Demagnetization cycle on power-up. With power-up, the VOUT across the compensation coil centers around half the supply and then starts the cycle after the 4V threshold is exceeded. The ERROR flag resets to H after the cycle is completed. VDD1 V(DEMAG) 42µs 1 1 5V/div 106ms V(ERROR) V(ERROR) 4 5V/div 4 V(IS1) V(ICOMP2) 2 2 RSH = 10Ω 2V/div 2V/div V(ICOMP2) Initial setting upon VOUT 3 closing of feedback loop. 3 20ms/div 20ms/div b) Power-up without demagnetization. The probe oscillation V(IS1) c) Demagnetization cycle on command. starts just before ERROR resets—15µs after the supply voltage cross- es the 4V threshold. V(DEMAG) 1 5V/div V(ERROR) 4 V(ICOMP2) RSH = 10Ω 2 3.4ms VOUT 2V/div 3 500µs/div d) Abort of demagnetization cycle. The ERROR flag resets to H (as shown) and the output settles back to normal opera- tion. Figure 7. Demagnetization and Power-On Timing20
  • 21. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009ERROR CONDITIONS 4. An open compensation coil is detected (longer than 100µs). Note: the probe driver, the PWM signalIn addition to the Over-Range flag that indicates signal filter and the ICOMP driver continue to function inclipping in the output amplifier (differential amplifier), a normal mode—only the ERROR flag is asserted insystem error flag is provided. The ERROR flag indicates this case. This condition indicates that not enoughconditions when the output voltage does not represent the current is flowing in the ICOMP driver output; thisprimary current. It is active during a demagnetization condition might be the result of a high-resistancecycle, during a power-fail or brown-out. It also goes active compensation coil or the connection of an externalwith an open or short-circuit in the probe loop. As soon as driver. Detection of this condition can be disabledthe error condition is no longer present and the circuit hasreturned to normal operation, the flag resets. by setting the CCdiag pin low.Both the ERROR and Over-Range flags are open-drain 5. At power-on after VDD1 crosses the +4V threshold,logic outputs. They can be connected together for a the ERROR flag is low for approximately 42µs.wired-OR and require an external pull-up resistor for 6. A supply voltage low (brown-out) condition lastsproper operation. longer than 100µs. Recovery is the same asThe following conditions result in ERROR flag activation power-up, either with or without a demag cycle.(ERROR asserts low):1. The probe comparator stays low for more than 32µs. PROTECTION RECOMMENDATIONS This condition occurs either if the probe coil connection is open or if the supply voltage dips to the The inputs IAIN1 and IAIN2 require external protection to level where the required saturation current cannot be limit the voltage swing beyond 10V of the supply voltage. reached. During the 32µs timeout, the ICOMP driver The driver outputs ICOMP1 and ICOMP2 can handle high remains active but goes inactive thereafter. In case of current pulses protected by internal clamp circuits to the recovery, ERROR is low and the ICOMP driver remains supply voltage. If repeated over-currents of large in reset for another 3.3ms. magnitudes are expected, connect external Schottky diodes to the supply rails. This external protection2. The probe driver pulse-width is less than 280ns for prevents current flowing into the die. three consecutive periods. This condition indicates The probe connections IS1 and IS2 are protected with either a shorted field probe coil or a fully-saturated diode clamps to the supply rails. In normal applications, no sensor at start-up. If this condition persists longer external protection is required. The maximum current must than 25µs and then recovers, the ERROR flag be limited to ±75mA. remains low and ICOMP is in reset for another 3.3ms. If the condition lasts less than 25µs, the ERROR flag All other pins offer standard protection—see the Absolute recovers immediately and the ICOMP driver is not Maximum Ratings table. interrupted.3. During demagnetization, if the cycle is aborted early by pulling DEMAG low, the ERROR flag stays low for another 3.3ms (ICOMP is disabled during this time). 21
  • 22. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009BASIC CONNECTION EXAMPLEThe circuit shown in Figure 8 offers an axample of a fully-connected current sensor system. IP Primary Winding Probe Current Sensor Module Main Core Core Probe Coil Compensation Coil S1 S2 K1 K2 +5V IS2 ICOMP R3 R4 C4 D1 C3 R2 R1 D2 +5V IS1 IS2 PWM PWM GAIN CCdiag ICOMP1 ICOMP2 IAIN2 IAIN1 (PWM is in phase with IS1.) Amp +5V V=4 +5V R6 VDD1 Integrator Probe Coil H−Bridge OVER−RANGE C2 Driver and VSW Comparator Driver VOUT R5 GND1 VSW REFIN Bandgap 2.5V REFOUT Reference 10MHz DEMAG Logic: Timing, Error Detection, and Demagnetize Oscillator Reset Power Valid DRV401 R7 ERROR VDD2 GND2 +5V C4 +5V Figure 8. Basic Connection Circuit22
  • 23. DRV401 www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009The connection example in Figure 8 illustrates the few LAYOUT CONSIDERATIONSexternal components required for optimal performance.Each component is described in the following list: The DRV401 operates with relatively large currents and fast current pulses, and offers wide-bandwidth IP is the primary current to be measured; K1 and K2 performance. It is often exposed to large distortion energy connect to the compensation coil. S1 and S2 from both the primary signal and the operating connect to the magnetic field probe. The dots environment. Therefore, the wiring layout must provide indicate the winding direction on the sensor main shielding and low-impedance connections between core. critical points. R1 and R2 form the shunt resistor RSHUNT. This Use low ESR capacitors for power-supply decoupling. Use resistance is split into two to allow for adjustments a combination of a small capacitor and a large capacitor of to the required RSHUNT value. The accuracy and 1µF or larger. Use low-impedance tracks to connect the temperature stability of these resistors are part of capacitors to the pins. the final system performance. Both grounds should be connected to a local ground plane. R3 and R4, together with C3 and C4, form a network Both supplies can be connected together; however, best that reduces the remaining probe oscillator ripple in results are achieved with separate decoupling (to the local the output signal. The component values depend GND plane) and ferrite beads in series with the main on the sensor type and are tailored for best results. supply. The ferrite beads decouple the DRV401, reducing This network is not required for normal operation. interaction with other circuits powered from the same supply voltage source. R5 is the dummy shunt (RD) resistor used to restore The reference output is referred to GND2. A the symmetry of both differential amplifier inputs. low-impedance, star-type connection is required to avoid R5 = 4 × RSHUNT, but the accuracy is less important. the driver current and the probe current modulating the R6 and R7 are pull-up resistors connected to the voltage drop on the ground track. logic outputs. The connection wires of the difference amplifier to the C1 and C2 are decoupling capacitors. Use low shunt must be low resistance and of equal length. For best ESR-type capacitors connected close to the pins. accuracy, avoid current in this connection. Consider using Use low impedance printed circuit board (PCB) a Kelvin Contact-type connection. The required resistance traces, either avoiding vias (plated-through holes) value can be set using two resistors. or using multiple vias. A combination of a large Wires and PCB traces for S1 and S2 should be very close (> 1µF) and a small (< 4.7nF) capacitor are or twisted. ICOMP1 and ICOMP2 should also be wired close suggested. When selecting capacitors, make sure together. To avoid capacitive coupling, run a ground shield to consider the large pulse currents handled from between the S1/S2 and ICOMP wire pair or keep them the DRV401. distant from each other. D1 and D2 are protection diodes for the differential The compensation driver outputs (ICOMP) are low amplifier input. They are only needed if the voltage frequency only; however, the primary signal (with drop at RSHUNT exceeds 10V at the maximum high-frequency content present) is coupled into the possible peak current. compensation winding, the shunt, and the difference amplifier. Therefore, careful layout is recommended. The output of REFOUT and VOUT can drive some capacitive loads, but avoid large direct capacitive loads; these loads increase internal pulse currents. Given the wide bandwidth of the differential amplifier, isolate any large capacitive load with a small series resistor. A small capacitor in the pF range can improve the transient response on a high resistive load. The exposed thermal pad on the bottom of the package must be soldered to GND because it is internally connected to the substrate, which must be connected to the most negative potential. It is also necessary to solder the exposed pad to the PCB to provide structural integrity and long-term reliability. 23
  • 24. DRV401 www.ti.comSBVS070B − JUNE 2006 − REVISED MAY 2009POWER DISSIPATION Specifications JESD51-0 to 7, QFN/SON PCB Attachment (SLUA271), and Quad Flatpack No-LeadUsing the thermally-enhanced PowerPAD SO and QFN Logic Packages (SCBA017). These documents arepackages dramatically reduces the thermal impedance available for download at www.ti.com.from junction to case. These packages are constructedusing a down-set lead frame upon which the die is Table 1. qJA/JP Estimations According Tomounted, as shown in Figure 9a and Figure 9b. This EIA/JED51-7arrangement results in the lead frame being exposed as athermal pad on the underside of the package. Figure 9 QFN-20 SO-20shows the SO-20 package as an example. Because this qJP 9 9thermal pad has direct thermal contact with the die, qJA Still Air 40 35excellent thermal performance can be achieved by qJA with Forced Airflow (150lfm) 38 32providing a good thermal path away from the thermal pad.The two outputs ICOMP1 and ICOMP2 are linear outputs. qJA = junction-to-ambient thermal resistance,Therefore, the power dissipation on each output is qJP = junction-to-pad thermal resistance, lfm = linear foot per minute.proportional to the current multiplied by the internal voltagedrop on the active transistor. For ICOMP1 and ICOMP2, this NOTE: All thermal models have an accuracy ≈ 20%.internal voltage drop is the voltage drop to VDD2 or GND,according to the current-conducting side of the output. Measuring the temperature as close as possible to the exposed thermal pad is recommended. The relatively lowOutput short-circuits are particularly critical for the driver thermal impedance, qJP, of less than 10°C/W (with somebecause the full supply voltage can be seen across the additional °C/W to the temperature test point on the PCB)conducting transistor, and the current is not limited by allows good estimation of the junction temperature in theanything other than the current density limitation of the application.FET. Permanent damage to the device can occur. The thermal pad on the PCB should contain nine or moreThe DRV401 does not include temperature protection or vias for the QFN package. The same applies for the SOthermal shut-down. package, where the solder pad on the PCB can be larger than the exposed pad (for example, 6.6mm × 18mm) asTHERMAL PAD recommended in the application literature notedPackages with an exposed thermal pad are specifically previously.designed to provide excellent power dissipation, but board Component population, layout of traces, layers, and airlayout greatly influences overall heat dissipation. Table 1 flow strongly influence heat dissipation. Worst-case loadshows the thermal resistance (TJA) for the two packages conditions should be tested in the real environment towith the exposed thermal pad soldered to a normal PCB, ensure proper thermal conditions. Minimize thermal stressas described in Technical Brief SLMA002, PowerPAD for proper long-term operation with a junction temperatureThermally-Enhanced Package. See also EIA/JEDEC well below +125°C. DIE Side View (a) Exposed Thermal Pad DIE Bottom View (c) End View (b) Figure 9. SO-20 Package Example of Thermally-Enhanced PowerPAD24
  • 25. www.ti.com SBVS070B − JUNE 2006 − REVISED MAY 2009 Revision History DATE REV PAGE SECTION DESCRIPTION 1 Front Page Updated front page appearance. 5/09 B 5 Pin Configurations Added DWP pinout information to the Pin Assignments table.NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 25
  • 26. PACKAGE OPTION ADDENDUMwww.ti.com 16-Mar-2010PACKAGING INFORMATION Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Type Drawing Qty DRV401AIDWP ACTIVE SO DWP 20 25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR Power no Sb/Br) PAD DRV401AIDWPG4 ACTIVE SO DWP 20 25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR Power no Sb/Br) PAD DRV401AIDWPR ACTIVE SO DWP 20 1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR Power no Sb/Br) PAD DRV401AIDWPRG4 ACTIVE SO DWP 20 1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR Power no Sb/Br) PAD DRV401AIRGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR no Sb/Br) DRV401AIRGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR no Sb/Br) DRV401AIRGWT ACTIVE VQFN RGW 20 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR no Sb/Br) DRV401AIRGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR no Sb/Br)(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TIs terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.Important Information and Disclaimer:The information provided on this page represents TIs knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.In no event shall TIs liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis. Addendum-Page 1
  • 27. PACKAGE OPTION ADDENDUMwww.ti.com 16-Mar-2010OTHER QUALIFIED VERSIONS OF DRV401 :• Enhanced Product: DRV401-EPNOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2
  • 28. PACKAGE MATERIALS INFORMATIONwww.ti.com 17-Jul-2012TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) DRV401AIDWPR SO DWP 20 1000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 Power PAD DRV401AIRGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 DRV401AIRGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1
  • 29. PACKAGE MATERIALS INFORMATIONwww.ti.com 17-Jul-2012*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV401AIDWPR SO PowerPAD DWP 20 1000 367.0 367.0 45.0 DRV401AIRGWR VQFN RGW 20 3000 367.0 367.0 35.0 DRV401AIRGWT VQFN RGW 20 250 210.0 185.0 35.0 Pack Materials-Page 2
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