Dynamic&p t-logic

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Dynamic&p t-logic

  1. 1. Dynamic and Pass- Transistor Logic Prof. Vojin G. OklobdzijaReferences (used for creation of the presentation material):1. Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE Circuits and Devices Magazine, November 1992.2. Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with CMOS”, IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.3. V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOS- Domino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April 1986.
  2. 2. References: 4. Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures”, IEEE Journal of Solid-State Circuits, Vol. SC-18, No 3, June 1983. 5. L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential CMOS Logic Family”, in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984. 6. L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits, Vol. SC- 20, No 5, October 1985. 7. K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 2
  3. 3. References: Pass-Transistor Logic: 8. S. Whitaker, “Pass-transistor networks optimize n-MOS logic”, Electronics, September 1983. 9. K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, Vol. 25, No 2, April 1990. 10. K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994. 11. M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double Pass-Transistor Logic”, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993. 12. N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using Pass- transistor Multiplexer”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 3
  4. 4. References: 13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For Low-Power CMOS,” Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995. 14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with the Pass- Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems”, Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995 15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994. 16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 4
  5. 5. Dynamic CMOS LogicProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 5
  6. 6. (a) Dynamic CMOS Latch (a), Dynamic CMOS Master-Slave Latch (b) Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 6
  7. 7. Dynamic Manchester Carry ChainProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 7
  8. 8. Radiation induced chargeProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 8
  9. 9. Accidental charge caused by capacitive or inductive coupling between the signallines Y and Z. (a)Prevention by inserting and inverter between the affected line and the pass-transistor switch (b) Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 9
  10. 10. CMOS Domino Logic CMOS logic block (a), Domino Logic (b)Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 10
  11. 11. CMOS Domino LogicProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 11
  12. 12. CMOS Domino Logic Operation 0 1 1 1 1 0 1 0 1 1 0 110 Dominos Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 12
  13. 13. CMOS Domino Logic: Charge Re-DistributionProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 13
  14. 14. Variations of CMOS Domino Logic: NORA LogicProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 14
  15. 15. CVS and DCVS Logic IBM (Heller et al. 1984)Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 15
  16. 16. Cascode Voltage Switch Logic CVSIBMProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 16
  17. 17. DCVS Logic (IBM)Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 17
  18. 18. DCVS Logic (IBM) (a) (b) Differential Cascode Voltage Switch Logic: (a) Static DCVLS (b) Dynamic DCVSLProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 18
  19. 19. DCVS Logic vs CMOSDCVS Logic consisting of two shared CMOS consisting of two separate:nMOS transistor switching networks nMOS and pMOS transistor switching networksProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 19
  20. 20. Transistor sharing in DCVS Logic: Implementation of 3-input XOR function Q Q A A A A B B B B C C Q=a ⊕ b ⊕ cProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 20
  21. 21. Switching Asymmetry in DCVSL This asymmetry causes current spikes and increased power consumption !Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 21
  22. 22. Pass-Transistor LogicProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 22
  23. 23. Pass-Transistor Logic (a) (b) (a) XOR function implemented with pass-transistor circuit, (b) Karnaough map showing derivation of the XOR functionProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 23
  24. 24. Pass-Transistor Logic General topology of pass-transistor function generatorKarnaough map of 16 possiblefunctions that can be realized Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 24
  25. 25. Pass-Transistor LogicFunction generatorimplemented with pass-transistor logic Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 25
  26. 26. Pass-Transistor LogicThreshold voltage drop at the Voltage drop does not exceed Vthoutput of the pass-transistor when there are multiplegate transistors in the path Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 26
  27. 27. Pass-Transistor Logic Elimination of the threshold voltage drop by: (a) pairing nMOS transistor with a pMOS (b) using a swing-restoring inverterProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 27
  28. 28. Complementary Pass-Transistor Logic (CPL)Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 28
  29. 29. Basic logic functions in CPL A B B A A B A A A A A BB BB B A B B A A B A B B A A C B C BC BC Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 29
  30. 30. CPL Logic A A A A B n1 n2B B n3 n4B C Q Qb C S S (a) (b) S S XOR gate Sum circuit CPL provides an efficient implementation of XOR function Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 30
  31. 31. CPL InverterProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 31
  32. 32. Double Pass-Transistor Logic (DPL): VDD A B B A AND/NAND A BB BA A O O A B A B A B A B XOR/XNORB A A BA BB AA B O O Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 32
  33. 33. Double Pass-Transistor Logic (DPL): XOR One bit full-adder: Sum circuitProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 33
  34. 34. Double Pass-Transistor Logic (DPL): DPL Full Adder The critical path traverses two transistors only (not counting the buffer)Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 34
  35. 35. Formal Method for CPL Logic Derivation Markovic et al. 2000 (a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed) (b) Express the value of the function in each cube in terms of input signals (c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one common node, which is the output of NMOS pass-transistor network Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 35
  36. 36. Formal Method for P-T Logic DerivationComplementary function can be implemented from the same circuit structure by applying complementarity principle:Complementarity Principle: Using the same circuit topology, with pass signals inverted, complementary logic function is constructed in CPL.By applying duality principle, a dual function is synthesized:Duality Principle: Using the same circuit topology, with gate signals inverted, dual logic function is constructed.Following pairs of basic functions are dual: AND-OR (and vice-versa) NAND-NOR (and vice-versa) XOR and XNOR are self-dual (dual to itself) Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 36
  37. 37. Derivation of P-T Logic A AND A NAND B B A OR A OR B B B B B 0 1 0 1 0 1 0 0 0 0 1 1 A 0 1 1 A 1 0 1 A 1 1 0 1 1 0 L 1 L 2 L 1 L 2 L 1 L 2 A B A B A B L 2 L 1 L 2 L 1 L 1 L 2 B B B B B B AND NAND (OR) OR Copmplementarity: AND  NAND; Duality: AND  ORProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 37
  38. 38. Derivation of CPL Logic Complementarity: AND  NAND B B A 0 1 A B A B A B A B L 2 L 1 0 0 0 B B B BA 1 0 1 L 1 L 2 AND NAND OR NOR (a) (b) (c) Duality: AND  OR NAND  NOR Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 38
  39. 39. Derivation of CPL Logic B B A 0 1 A A A A L 2 L 1 0 0 1 B BA 1 1 0 L 1 L 2 XOR XNOR (a) (b) (a) XOR function Karnaugh map, (b) XOR/XNOR circuit Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 39
  40. 40. Synthesis of three-input CPL logic A C B A C B BC C L 1 L 2 L 3 A 00 01 11 10 A L 1 0 0 0 0 0 A B L 2A 1 0 0 1 0 B L 3 B AND NAND (a) (b) (a) AND function Karnaugh map, (b) AND/NAND circuit Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 40
  41. 41. Double Pass-Transistor Logic (DPL): Synthesis Rules 1. Two NMOS branches can not be overlapped covering logic 1s.Similarly, two PMOS branches can not be overlapped covering logic0s. 2. Pass signals are expressed in terms of input signals or supply.Every input vector has to be covered with exactly two branches. 3. At any time, excluding transitions, exactly two transistorbranches are active (any of the pairs NMOS/PMOS, NMOS/NMOSand PMOS/PMOS are possible), i.e. they both provide output current. Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 41
  42. 42. Double Pass-Transistor Logic (DPL): Synthesis Rules Complementarity Principle: Complementary logic function inDPL is generated after the following modifications: • Exchange PMOS and NMOS devices. Invert all pass and gatesignals Duality Principle: Dual logic function in DPL is generatedwhen: • PMOS and NMOS devices are exchanged, and VDD and GNDsignals are exchanged. Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 42
  43. 43. DPL Synthesis: B A B A B B L 4 L 2 A 0 1 L 3 A B A B 0 0 0 L 4 AND NANDA 1 0 1 A B A B L 3 L 1 L 1 L 2 GND GND +V DD +V DD (a) (b) (a) AND function Karnaugh map (b) AND/NAND circuit Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 43
  44. 44. DPL Synthesis: OR/NOR circuit +V DD +V DD B AA B A B OR NORA B A B B A GND GNDProf. V.G. Oklobdzija Advanced Digital Integrated Circuits 44
  45. 45. DPL Synthesis: B A B A B Complementarity B L 4 L 2 A 0 1 Principle: L 3 A B A B Exchange PMOS 0 0 0 and NMOS L 4 AND NAND devices. InvertA 1 0 1 A B all pass and gate A B L 3 L 1 signals L 1 L 2 AND  NAND GND GND +V DD +V DD (a) AND function Karnaugh map (b) AND/NAND circuit +V DD +V DD B A Duality Principle: A B A B PMOS and NMOS devices OR NOR are exchanged, and VDD and A B A B GND signals are exchanged: B A GND GND AND  OR NAND  NOR Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 45

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