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  • 1. SOVERAN S. DHAKAD Asst. Asst Professor Electronics & Communication Engg. Deptt. (M-Tech- Embedded System & VLSI Design) Tech- Email-Id- Contact- Contact- 09685396020 ,0751-2387520(O) ,0751- NAGAJI INSTITUTE OF TECHNOLOGY & MANAGEMENT,THAKUR BABA CAMPUS ,JHANSI ROAD , NH-75 ,SITHOLI ,GWALIOR-474001E-Mail – ,website:- @ g, gContact No. -0751-2410201 ,2387520 ,9685396020
  • 3. MemoryOperationSense Amplifier pCache MemoryLeakage In SRAM CellWhy 5T SRAM CellStructure Diagram Of 5T SRAMOperation in 5T SRAM CellImplementation & ResultConclusion & Future WorkReference
  • 4. A memory in terms of computer hardware is a storage unit. unit Storage devices such as magnetic device, hard disk, CDs,DVDs etc The memory of a computer stores the programs and datawhile being processed. gp It is built up of small units called bits which can hold onebinary symbol of data (referred to as a ’1’ or a ’0’). Also it helps to boot the system. Memory directly accessible by CPU CPU. There are Various types of basic operations that have tobe supported by a RAM. These are the writing and reading pp y g gof ’0’ and ’1’ respectively . NITM , GWALIOR
  • 5. MEMORY RAM ROMRAM (Random Access Memory)- Random Access Memory, a memory where informationcan be stored and retrieved in non-sequential order non sequential order.ROM (Read Only Memory)- ROM, l ROM also k known as fi firmware, i an i t is integrated circuit t d i itprogrammed with specific data when it is manufactured.ROM chips are used not only in computers, but in most otherelectronic items as well. NITM , GWALIOR
  • 6. It is an array of elementswhich can either store 1 or 0. It is dynamic in nature. It is volatile . It is made either ofsemiconductors or capacitors i d ias required. NITM , GWALIOR
  • 7. bitline conditioning wordlines row decoder bitlines memory cells: 2n-k rows x 2m+k columns rn-k k column circuitry n column decoder 2m bits NITM , GWALIOR
  • 8. The memory cells in a SRAM are organized in rows andcolumns. Memory Cell = 2n-k Row Ҳ 2m+k Columns In the I th write operation , th W d li i i active state, i it ti the Word line is in ti t t inthat cause each data bit to be stored in a selected cell in theassociated column. In the read operation the read line is in active state in operation, state,that cause the data bits stored in the selected row to appearon th D t I/O li the Data lines. NITM , GWALIOR
  • 10. The 6T SRAM cell has a differential read operation. Thismeans that both the stored value and its inverse are used inevaluation to determine the stored value. Before the onset ofa read operation, th W d li d ti the Word line i h ld l is held low and th t d the twobitlines connected to the cell through transistors M5 and M6are precharged high . Since the gates of M5 and M6 are heldlow, these access transistors are off and the cross-coupledlatch is isolated from the bitlines. NITM , GWALIOR
  • 11. A_b bit_b 1.5 1.0 word bit 0.5 A 0.0 00 0 100 200 300 400 500 600 time (ps)NITM , GWALIOR
  • 12. Read Operation:- If the value is a 1, stored at Q. The read cycle is started by pre charging both the bitlines to a logical 1, then asserting the word line WL,enabling both the access transistors. The Th second step occurs when th values stored i Q and d t h the l t d in dQ are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to a g g g glogical 0. On the BL side, the transistors M4 and M6 pull the bit linetoward VDD, a logical 1 1. If the content of the memory was a 0, the opposite wouldhappen and BL would be pulled toward 1 and BL toward 0. NITM , GWALIOR
  • 13. A_b Ab 1.5 A bit_b bit b 1.0 0.5 word 0.0 0 100 200 300 400 500 600 700 time (ps)NITM , GWALIOR
  • 14. Write Operation:- The start of a write cycle begins by applying the value to bewritten t th bit li itt to the lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e.setting BL to 1 and BL to 0.This is similar to applying a reset pulse to a SR-latch , whichcauses the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL isthen asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line input-drivers are d id i designed t b much stronger th d to be h t than th relatively the l ti lweak transistors in the cell itself, so that they can easilyoverride the previous state of the cross-coupled inverters. NITM , GWALIOR
  • 15. It is practically embedded in every application thatrequires electronic use interface such as digital cameras cameras,cell phones, etc. Internal CPU caches , h d di k b ff I t l h hard disk buffers, router b ff t buffers,LCD screens and printers also normally employ static RAMto hold the image displayed . Small SRAM buffers are also found in CDROM and CDRWdrives; usually 256 kB. NITM , GWALIOR
  • 16. A Sense Amplifier is an essential S A lifi i i lcircuit in designing memory chips. The resulting signal in the event of a signal,Read operation, has a much lowervoltage swing. To compensate for thatswing a sense amplifier is used toamplify voltage coming off Bit Line. The lt Th voltage coming out of th sense i t f theamplifier typically has a fully swing (0 -2.5V) voltage. ) g Sense amplifier also helps reduce thedelay times and power dissipation inthe overall SRAM chip. NITM , GWALIOR
  • 17. There are many versions of senseamplifiers used in memory chips :- The one that we will use in ourdesign is called a Cross-coupledSense Amplifier demonstrated on a pblock diagram below. During a read sequence, Bit Lineand Bit Line are directed into X andX inputs. Once SE has been set tologic 1, the amplifier turns on, andgives Y and Y as its outputs. NITM , GWALIOR
  • 18. Cache memory is basically a cost-effective method ofimproving system performance. Cache memory is a relatively small, high-speed memorythat stores the most recently used instructions or data. Cache memory ca al o use d a ic RAM (DRAM) e o can also e dynamic (DRAM). Cache memory stored information to the microprocessormuch faster than if only high-capacity DRAM is used used. Cache memory used to store data or instructions likely tobe used soon by the CPU. Its purpose is to speed upoperation by bridging the performance gap between theCPU and the main memory. NITM , GWALIOR
  • 19. Two types of cache level are used in cache memory: memory:-L1 :- It usually integrated into the processor chip and has avery limited storage capacity. y g p y It gives an extremely short access time, and thereforeprovides the highest performance This cache usually runs at the same clock frequency asthe CPUL2 :-It is separate memory chip or set of chips external tothe processor and usually has a larger storage capacitythan L1 h This is connected to CPU through an internal bus Some higher-level caches (L3. L4, .), but L1 and L2 are themost common. NITM , GWALIOR
  • 20. There are some very important requirements for a memorywhen it is to be embedded as on-chip cache: It has to be reliable and stable. This is of course true forall memories, but is specially important for cache due tothe more extreme performance requirements and arealimitations. Memory provide high performance gap between mainmemory and the CPU. Another important p requirement q is low p powerconsumption. NITM , GWALIOR
  • 21. Low power design is important from three differentreasons- Technology driven forces Minimum feature size, Minimize parasitic capacitance Higher operating speed Design driven forces Power consumption in digital circuits p g Power consumption in analog circuits Market driven forces The growing demand for long life portable equipment. NITM , GWALIOR
  • 22. There are various types of applications of low power- Battery-powered portable systems, for example laptops,CDs, ,DVDs Electronic packet communication products such as;cordless and cellular telephones, PDAs (Personal DigitalAssistants), pagers. Sub-GHz S b GH processors f hi h for high-performance workstations f k t tiand computers. Other applications such as WLANs (Wireless Local AreaNetwork) and electronic goals (calculators, hearing aids,watches, etc.). NITM , GWALIOR
  • 23. The supply voltage must be reduced. The threshold voltage (VT) must be reduced proportionallywith the supply voltage so th t a sufficient gate overdrive is ith th l lt that ffi i t t d i imaintained. Reduction in the threshold voltage causes increase inleakage current. NITM , GWALIOR
  • 24. During an idle phase, the word lines are deselected (WL = phase‘0’) and the bit lines are precharged (BL = ‘1’ and BL = ‘1’). The memory cell data either transistors N4 P1 N2 (for bit data, N4, P1,= ‘1’) or N3, P2, N1 (for bit = ‘0’) will be leaking . The transistors in the off state in bold for bit = ‘0’. In thiscase N3,N1 and P2 are off and will be leaking. The leakagecurrent in the memory cell would be as shown in equation: ImemcellIdle = IDsub(N1) + IDsub(N3) + IDsub(P2) where, IDsub is the sub threshold leakage current ofthe MOSFET , which is given by the equation :- IDsub = Is e VGS/(nKT)/q [1-VDS/eKT/q ]where, Is and n are imperial parameters with n ≥ 1. NITM , GWALIOR
  • 25. The sub threshold leakage in the whole memory core is given by equation . ImemcoreIdle = Nrows. Cools . ImemcellIdlewhere, Nrows and Ncols are the number of rows and columns respectively in the memory core. Thus to reduce the leakage of a memory cell we have to t concentrate on t t t two components of l k t f leakage :-1. one is the leakage inside the cell .2. Second is leakage to bit lines. NITM , GWALIOR
  • 26. Techniques are used to reduce the leakage current is:-T h i d d h l k iDual VT :- This technique requires no additional control circuitry and can substantially reduce the leakage current when compared to low VT devices devices. No data are discarded and no additional caches misses are incurred. However , high- transistors have high slower switching speed and lower current drive.ABC-MTCMOS :- It can reduce the leakage current significantly using a simple circuit while in the sleep mode. NITM , GWALIOR
  • 27. In order to reduce undesirable leakage current in the I d d d i bl l k i hsleep mode, the back gate bias is automaticallycontrolled to increase the threshold voltage. g NITM , GWALIOR
  • 28. DVS (Dynamic Voltage Scaling):-In this method to reduce the leakage power of SRAM cells,in active mode. When cells are not intended to be accessed for a time period, the a e placed i a sleep mode. e iod they are laced in lee ode In a sleep mode the leakage power is significantly reduced due to the decreases in both leakage current and supply voltage. NITM , GWALIOR
  • 29. We have to used Two PMOS transistor P1,P2, to control the supply voltage of the memory cell based on the p g operating.1. Active Mode 2. Sleep Mode If cell is active mode , P1 supplies a standard supply voltage, and P2 supplies a standby voltage. If cell is Sleep mode, P1 and P2 are controlled by complementary supply voltage control signals. NITM , GWALIOR
  • 30. Embedded memory-E b dd d Easy to implement in generic CMOS process. Easy to design as logic circuit. Easy to test by finite-state machine.Compliable design- Fixed cell size to a ow us ded cat g in peripheral c cu t ed ce s e allow dedicating pe p e a circuitdesign Synchronous interface since 0.35µm generation simplifies 0 35µmthe design A larger number of instances required NITM , GWALIOR
  • 31. NITM , GWALIOR
  • 32. In the 5T SRAM cell differs fundamentally from the cellused in 2PMOS & 3 NMOS Transistors. The latch of the cell is disconnected from the gnd supply tofacilitate itf ilit t write. This requires an additional metal wire and also destabilizes qall cells on the bit line during write. The design and all simulations are carried out at 100nmtechnology. NITM , GWALIOR
  • 33. Read Operation-The operation scheme when reading a 5Tcell is very similar to the 6T SRAM. Before the onset of a read operation, the word line is heldlow and the bitline is precharged. The bitline is not precharged to VCC, So another value iscarefully chosen according to stability and performancerequirements. If reading a ’0’ BL will now b pulled d di ’0’, ill be ll d down th through th h thetransistor combination. If instead a ’1’ is to be read, thesituation is slightly different from the 6T case. NITM , GWALIOR
  • 34. Write Operation-Writing in the 5T SRAM cell differs fromthe 6T cell mainly by the fact that it is done from only onebitline. In the 5T cell the value to be written is held on the bitline,and the word line is asserted. The 6T cell was sized so that a ’1’ could not be written by 1a high voltage on the bitline, the 5T cell has to be sizeddifferently. NITM , GWALIOR
  • 35. The difference between the 5T SRAM and the 6T SRAM ishow the sensing of the stored value is done. The 6T cell has two bit lines and the stored value is senseddifferentially. The 5T cell only has one bitline. Depending on the valuestored, the 5T bitline is either raised or lowered. A few different techniques can be used for this. One ideamight be to use a type of sample and hold circuit that wouldSample the value before the read and then use this value as areference in a differential sense amplifier. NITM , GWALIOR
  • 36. NITM , GWALIOR
  • 37. NITM , GWALIOR
  • 38. NITM , GWALIOR
  • 39. Table 5.1: Leakage power and performance of 6T cell Metrics Standard 6T cellRead time (WL high up to 100mV difference in bit lines) 336psWrite time (WL high up to node flips) 76psLeakage Power/cell 2.03nW NITM , GWALIOR
  • 40. Table 5.2: Comparison of leakage power reductiontechniquesLeakage Reduction Leakage Power PercentageTechnique Dissipation/Cell (in Reduction n W) Conventional 2.030 - DVS 0.230 88.7 Gated-VDD G t d VDD 0.033 0 033 98.3 98 3 NITM , GWALIOR
  • 41. Table 5.3: Leakage power and performance of 5T cell 5 3: Metrics Standard 6T cellRead time (WL high up to 100mV difference in bit lines) 365psWrite time (WL high up to node flips) 102psLeakage Power/cell 1.79nW Table 5.4: Comparison of leakage power dissipation in 6T and 5T cellLeakage Reduction Leakage Power Percentage Technique Dissipation/Cell (in nW) Reduction 6T 5T Conventional 2.030 1.790 11.8 DVS 0.230 . 0.170 . 7 26.0 Gated-VDD 0.033 0.029 12.1 NITM , GWALIOR
  • 42. NITM , GWALIOR
  • 43. NITM , GWALIOR
  • 44. NITM , GWALIOR
  • 45. NITM , GWALIOR
  • 46. NITM , GWALIOR
  • 47. NITM , GWALIOR
  • 48. Various circuit level techniques have been applied to 6Tand designed 5T SRAM cell for leakage power reductionand compared. Out of all the techniques discussed DVS hasfound t b th b t as it reduces l kf d to be the best d leakage comparable t bl toGated VDD as well as retain the cell information. It has been found that in conventional 6T SRAM cell upto 98% reduction in leakage power can be achieved usingthese techniques. With conventional 5T cell about 11.8%leakage power reduction has been achieved thanconventional 6T cell. Further applying the leakagereduction t h i d ti techniques t th 5T cell h shown 26% more to the ll has hreduction in leakage than in the case of 6T cell. NITM , GWALIOR
  • 49. In this thesis various circuit level leakage pg powerreduction techniques have been analyzed with 6T and 5TSRAM cell at 180nm technology. A large reduction inleakage has been observed As memory cells being observed.discussed have to be used in cache memory their stability isalso very important. So stability analysis of both 6T and 5Tcells after applying leakage reduction techniques can be f i i ianalyzed. Device level techniques such as retrograde well; Halo q g ;doping and LDD (Light Doped Drain) implantation can beemployed for leakage reduction in individual MOSFETswhich eventually will reduce in large reduction As leakage reduction.will be more significant beyond 100nm technology so thiswork should be extended to higher technologies such as90nm, 7090 70nm or b beyond. d NITM , GWALIOR
  • 50. [1] Soveran Singh Dhakad, Shyam Akashe, “CMOS VLSI S Si h Dh k d Sh Ak hDesign” National Conference in NEE ,Gwalior , Ist Oct. 2009.[ ][2] Soveran Singh Dhakad, Shyam Akashe, “Cache g yMemory cell for Leakage Power ” National Conference inNEE , Gwalior ,26th June . 2010. NITM , GWALIOR
  • 51. [1[. H. Tran, “Demonstration of 5T SRAM and 6T Dual Port RAM Cell Arrays, Symposium on VLSI Circuits, pp. Demonstration Dual-Port Arrays,”74-79, Jun. 2005.[2]. V. De and S. Borkar, “Technology and design challenges for low power and high performance”, InternationalSymposium Low Power Electronics and Design, pp.167- 170, 2000.[3]. S. Borkar, “Technology trends and design challenges for microprocessor design”,ESSIRC, pp. 10-18, Sep. 1995.[4]. S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, “Scaling of stack effect and its application forleakage reduction,” in Proc. IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 175– g y g182, Aug.2006.[5].T. Floyd, “Digital Fundamentals”, Prentice Hall, ninth edition, 2007.[6]. J. M. Rabaey, A. Chandrakasan,[6] J M Rabaey A Chandrakasan and B Nikolic “Digital Integrated Circuits: A Design Perspective”, Prentice Hall B. Nikolic, Digital Perspectiveseries in electronics and VLSI, Prentice Hall,second edition, 2006.[7].I. Carlson, S. Anderson, S. Natarajan and A. Alvandpour, “ A high density, low leakage, 5T SRAM for embeddedcaches”, Proceedings of the 30th Solid State Circuits Conference, ESSCIRC, pp. 220-230, December 2002.[8].M. Mamidipaka, K. Khouri, N.Dutt, and M. Abadir, “Analytical models for leakagepower estimation of memoryarray structures”, International Conference on Hardware/Software and Co-design and System Synthesis pp. 149-167,2001.[9].J. T. Koa and A. P. Chandrakasan, “Dual threshold voltage techniques for low-power digital circuits”, in IEEEJournal of solid state Circuits, Vol. 37, No.10, pp.1119-1218,March 2006. NITM , GWALIOR
  • 52. [[ ][[10].B. Amelifard, F. Fallah, M. Pedram, “Reducing the sub-threshold and g , , , g gate-tunneling leakage of SRAM cells g gusing dual-vt and dual-tox assessment”, in IEEE Proceedings of Design, Automation and Test, Vol. 2, pp. 5-7, 2001.[11].C. H. Kim and K. Roy, “A leakage tolerant cache memory for low voltage microprocessors,” Proceedings of the1998 International Symposium on Low-Power Electronics and Design, pp. 271-280, 2000.[12].M. Powell, S. Yang, B. Falsafi, K. Roy, and T. Vijaykumar, “Gated-VDD: A circuit technique to reduce leakagein deep-submicron cache memories”, Proceedings IEEE/ACM International Symposium on Low Power Electronicsand Design, 2002, pp. 98–100.[13].S. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar, “An integratedcircuit/architecture approach toreducing leakage in deep-submicron high-performance I-caches”, in Proc. IEEE/ACM International Symposium onHigh-Performance Computer Architecture, 2005, pp. 157–162.[14].S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu,[14] S Mutoh T Douseki Y Matsuya T Aoki S Shigematsu and J Yamada “1-V power supply high-speed digital J. Yamada, 1-Vcircuit technology with Multi-threshold-voltage CMOS,” IEEE Journal Solid-State Circuits, vol. 34, pp. 1007-1025,Aug. 2000.[15].K. Nii, H. Makino, Y. Tujihashi, C. Morishima, Y. Hayakawa, H. Nunogami, T.Arakawa, and H. Hamano, “A lowpower SRAM using Auto-Backgate-Controlled MT-CMOS”, in Proceedings IEEE/ACM International Symposium onLow Power Electronic Devices, 2007, pp. 296–300.[16].H. Makino et al., “An Auto-Backgate-Controlled MTCMOS Circuit”, submitted to Symposium on VLSICircuits, June 2000. NITM , GWALIOR
  • 53. [17].N. S. Kim, K. Flautner, D. Blaauw and T. Mudge, “Circuit and Micro-architectural techniques for reducingcache leakage power”, IEEE Transaction on VLSI systems Vol. 12, No. 4, pp. 168-198, Feb. 2008.[18].K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy caches: Simple techniques for reducingleakage power”, in Proc IEEE/ACM International Symposium on Computer Architecture 2005 pp 142 157 power Proc. Architecture, 2005, pp. 142–157.[19].X. Chen and H. Bajwa, “Energy-efficient dual-port cache architecture with improved performances,” IEEJournal of Electronic Letters, Vol. 43, No. 1, pp. 15-18, Jan.2007.[20].H. Tran, “Demonstration of 5T SRAM and 6T Dual-Port RAM Cell Arrays,” Symposium on VLSI Circuits, pp.69-71, Jun. 1994.[21].S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, “Optimizing leakage energy consumption in cachebitlinesbitlines” Journal of Design Automation for Embedded Systems Mar 2005 Systems, Mar. 2005.[22].A. Karandikar and K. K. Parhi, “Low power SRAM design using hierarchical divided bitline approach”, inProceedings International Conference on Computer Design: VLSI in computers and Processors, pp. 82-100, 2000.[23] B.D. Yong and L.-S. Kim, “A l d i low power SRAM using hi i hierarchical bi li and l l sense amplifier”, i IEEE hi l bitline d local lifi inJournal of Solid State Circuits, Vol. 41, No. 7, pp. 1388- 1400, Jun. 2005.[24]. E. Seevinck, F. J. List and J. Lohsttoh, “Static-Noise Margin Analysis of MOS SRAM Cells,”IEEE JSSC,VOL. SC-22, NOS, pp.848-854, Oct.1998. , , pp , NITM , GWALIOR
  • 54. [25]. J. Lohstroh, E. Seevinck and J. de Groot, “Worst-Case Static Noise Margin Criteria for Logic Circuits andTheir Mathematical Equivalence,”IEEE JSSC, VOL. SC-18, NO. 6, pp. 801-807, Dec.1999.[26]. A. Alvandpour, D. Somasekhar, R. Krishnamurthy, V. De, S. Borkar and C. Svensson, “Bitline leakageequalization for sub - lOOnm caches,” European Solid state Circuits 2003 ESSCIRC’03 Conference on caches Solid-state Circuits, 2003, ESSCIRC 03. on,pp. 420-425, Sept. 2004.[27] Soveran Singh Dhakad, Shyam Akashe, Sanjay Sharma “Cache Leakage : A Leakage aware cachesimulator” International Journals of Computing and Applications, vol 5 no.2 (july-Dec-2010).[28] Soveran Singh Dhakad, Shyam Akashe, Sanjay Sharma “Dynamic Zero compression for CacheEnergy Reduction ” International Journals of power engineering ,vol 2 no.2 (july-Dec-2010).[29] Soveran Singh Dhakad, Shyam Akashe, “CMOS VLSI Design National Conference in NEE Gwalior, Dhakad Akashe CMOS Design” NEE, GwaliorIst Oct. 2009.[30] Soveran Singh Dhakad, Shyam Akashe, “Cache Memory cell for Leakage Power” NationalConference in NEE, Gwalior, 26th June. 2010. NITM , GWALIOR