VLSI Technology <ul><li>Scaling </li></ul><ul><li>Moore’s Law </li></ul><ul><li>3D  VLSI </li></ul>
The beginning Microprocessors are essential to many of the products we use every day such as TVs, cars, radios, home appli...
Transistor Size Scaling MOSFET  performance improves as size is decreased: shorter switching time, lower power consumption...
Significant Breakthroughs Transistor size : Intel’s research labs have recently shown the world’s smallest transistor, wit...
Major Design Challenges <ul><li>Microscopic issues </li></ul><ul><ul><li>ultra-high speeds </li></ul></ul><ul><ul><li>powe...
Integrated Circuits <ul><li>Digital logic is implemented using  transistors  in  integrated circuits  containing many gate...
<ul><li>What are shown on previous diagrams cover only the so called front‑end  </li></ul><ul><li>processing ‑ fabrication...
Moore’s  Law <ul><li>Gordon E. Moore - Chairman Emeritus of Intel Corporation </li></ul><ul><li>1965 - observed trends in ...
<ul><li>In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every ...
Moore’s Law <ul><li>From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond </li></ul>Relati...
Ever since the invention of integrated circuit, the smallest feature size has been reducing every year. Currently (2002) t...
Limits of Moore’s Law? <ul><li>Growth expected until 30 nm gate length (currently: 180 nm) </li></ul><ul><ul><li>size halv...
Technological Background of the Moore’s Law <ul><li>To accommodate this change, the size of the silicon wafers on which th...
Recurring Costs <ul><ul><li>  cost of die + cost of die test + cost of packaging </li></ul></ul><ul><ul><li>variable cost ...
Yield Example <ul><li>Example </li></ul><ul><ul><li>wafer size of 12 inches, die size of 2.5 cm 2 , 1 defects/cm 2 ,    =...
Intel 4004 Microprocessor
Intel Pentium (IV) Microprocessor
Die Size Growth Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel 4004 8008 8080 8085 8086 286 386 486 Pentium ...
Clock Frequency Lead microprocessors frequency doubles every 2 years P6 Pentium  ® proc 486 386 286 8086 8085 8080 8008 40...
Examples of Cost Metrics (1994) $417 9% 40 296 1.5 $1500 0.80 3 Pentium $272 13% 48 256 1.6 $1700 0.70 3 Super SPARC $149 ...
VLSI <ul><li>Very Large Scale Integration </li></ul><ul><ul><li>design/manufacturing of extremely small, complex circuitry...
Origins of VLSI <ul><li>Much development motivated by WWII need for improved electronics, especially for radar </li></ul><...
Origins of VLSI  (Cont.) <ul><li>1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 componen...
Three Dimensional VLSI <ul><li>The fabrication of a single integrated circuit whose functional parts (transistors, etc) ex...
Advantages of 3D VLSI <ul><li>Speed - the time required for a signal to travel between the functional circuit blocks in a ...
Advantages of 3D VLSI <ul><li>Noise - unwanted disturbances on a useful signal </li></ul><ul><ul><li>reflection noise (var...
Advantages of 3D VLSI <ul><li>Power consumption </li></ul><ul><ul><li>power used charging an interconnect capacitance </li...
Advantages of 3D VLSI <ul><li>Interconnect capacity (connectivity) </li></ul><ul><ul><li>more connections between chips </...
Advantages of 3D VLSI <ul><li>Printed circuit board size/weight </li></ul><ul><ul><li>planar size of PCB reduced with negl...
3D VLSI - Challenges and Solutions <ul><li>Challenge: Thermal management </li></ul><ul><ul><li>smaller packages </li></ul>...
Influential Participants - Industry <ul><li>Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others.....
Three Dimensional VLSI <ul><li>Moore’s Law approaching physical limit </li></ul><ul><li>Increased performance expected by ...
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  • Staffing costs computed at $150K/staff year (in 1997 dollars)
  • While the cost of producing a single transistor has dropped exponentially over the past few decades, the basic cost equation hasn’t changed. Cost of a circuit is dependent upon the chip area. Alpha depends upon the complexity of the manufacturing process (and is roughly proportional to the number of masks). A good estimate for today’s complex CMOS process is alpha = 3. Defects per unit area is a measure of the material and process-induced faults. A value between 0.5 and 1 defects/cm**2 is typical today but strongly depends upon the maturity of the process.
  • While the cost of producing a single transistor has dropped exponentially over the past few decades, the basic cost equation hasn’t changed. Cost of a circuit is dependent upon the chip area. Alpha depends upon the complexity of the manufacturing process (and is roughly proportional to the number of masks). A good estimate for today’s complex CMOS process is alpha = 3. Defects per unit area is a measure of the material and process-induced faults. A value between 0.5 and 1 defects/cm**2 is typical today but strongly depends upon the maturity of the process.
  • introduced in 1971 versus 8086 introduced in 1978 1 MHz clock rate 10 MHz clock rate 5volt VDD (?) 5volt VDD 10 micron (?) 3 micron 5K transistors (?) 29K transistors
  • P5 introduced in 1994 versus P6 (Pentium Pro) in 1996 75 to 100 MHz clock rate 150 to 200 MHz clock rate 91 mm**2 196 mm**2 3.3M transistors 5.5M transistors (1M in cache) (external cache) 0.35 micron 0.35 micron 4 layers metal 4 layers metal 3.3volt VDD 3.3volt VDD &gt;20W typical power dissipation 387 pins
  • Vlsi

    1. 1. VLSI Technology <ul><li>Scaling </li></ul><ul><li>Moore’s Law </li></ul><ul><li>3D VLSI </li></ul>
    2. 2. The beginning Microprocessors are essential to many of the products we use every day such as TVs, cars, radios, home appliances and of course, computers. Transistors are the main components of microprocessors. At their most basic level, transistors may seem simple. But their development actually required many years of painstaking research. Before transistors, computers relied on slow, inefficient vacuum tubes and mechanical switches to process information. In 1958, engineers managed to put two transistors onto a Silicon crystal and create the first integrated circuit, which subsequently led to the first microprocessor.                                                 
    3. 3. Transistor Size Scaling MOSFET performance improves as size is decreased: shorter switching time, lower power consumption. 2 orders of magnitude reduction in transistor size in 30 years.
    4. 4. Significant Breakthroughs Transistor size : Intel’s research labs have recently shown the world’s smallest transistor, with a gate length of 15nm. We continue to build smaller and smaller transistors that are faster and faster. We've reduced the size from 70 nanometer to 30 nanometer to 20 nanometer, and now to 15 nanometer gates. Manufacturing process : A new manufacturing process called 130 nanometer process technology (a nanometer is a billionth of a meter) allows Intel today to manufacture chips with circuitry so small it would take almost 1,000 of these &quot;wires&quot; placed side-by-side to equal the width of a human hair. This new 130-nanometer process has 60nm gate-length transistors and six layers of copper interconnect. This process is producing microprocessors today with millions of transistors and running at multi-gigahertz clock speeds. Wafer size : Wafers, which are round polished disks made of silicon, provide the base on which chips are manufactured. Use a bigger wafer and you can reduce manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches) diameter silicon wafer size, up from the previous wafer size of 200mm (about 8 inches).
    5. 5. Major Design Challenges <ul><li>Microscopic issues </li></ul><ul><ul><li>ultra-high speeds </li></ul></ul><ul><ul><li>power dissipation and supply rail drop </li></ul></ul><ul><ul><li>growing importance of interconnect </li></ul></ul><ul><ul><li>noise, crosstalk </li></ul></ul><ul><ul><li>reliability, manufacturability </li></ul></ul><ul><ul><li>clock distribution </li></ul></ul><ul><li>Macroscopic issues </li></ul><ul><ul><li>time-to-market </li></ul></ul><ul><ul><li>design complexity (millions of gates) </li></ul></ul><ul><ul><li>high levels of abstractions </li></ul></ul><ul><ul><li>design for test </li></ul></ul><ul><ul><li>reuse and IP, portability </li></ul></ul><ul><ul><li>systems on a chip (SoC) </li></ul></ul><ul><ul><li>tool interoperability </li></ul></ul>$360 M 800 800 MHz 130 M Tr. 0.13 2002 $160 M 360 600 MHz 32 M Tr. 0.18 1999 $120 M 270 500 MHz 20 M Tr. 0.25 1998 $90 M 210 400 MHz 13 M Tr. 0.35 1997 Staff Costs Staff Size Frequency Complexity Tech. Year
    6. 6. Integrated Circuits <ul><li>Digital logic is implemented using transistors in integrated circuits containing many gates. </li></ul><ul><ul><li>small-scale integrated circuits (SSI) contain 10 gates or less </li></ul></ul><ul><ul><li>medium-scale integrated circuits (MSI) contain 10-100 gates </li></ul></ul><ul><ul><li>large-scale integrated circuits (LSI) contain up to 10 4 gates </li></ul></ul><ul><ul><li>very large-scale integrated circuits (VLSI) contain >10 4 gates </li></ul></ul><ul><li>Improvements in manufacturing lead to ever smaller transistors allowing more per chip. </li></ul><ul><ul><li>>10 7 gates/chip now possible; doubles every 18 months or so </li></ul></ul><ul><li>Variety of logic families </li></ul><ul><ul><li>TTL - transistor-transistor logic </li></ul></ul><ul><ul><li>CMOS - complementary metal-oxide semiconductor </li></ul></ul><ul><ul><li>ECL - emitter-coupled logic </li></ul></ul><ul><ul><li>GaAs - gallium arsenide </li></ul></ul>
    7. 7. <ul><li>What are shown on previous diagrams cover only the so called front‑end </li></ul><ul><li>processing ‑ fabrication steps that go towards forming the devices and </li></ul><ul><li>inter‑connections between these devices to produce the functioning IC's. The </li></ul><ul><li>end result are wafers each containing a regular array of the same IC chip or </li></ul><ul><li>die. The wafer then has to be tested and the chips diced up and the good chips </li></ul><ul><li>mounted and wire‑bonded in different types of IC package and tested again </li></ul><ul><li>before being shipped out. </li></ul>From Howe, Sodini: Microelectronics:An Integrated Approach, Prentice Hall
    8. 8. Moore’s Law <ul><li>Gordon E. Moore - Chairman Emeritus of Intel Corporation </li></ul><ul><li>1965 - observed trends in industry - # of transistors on ICs vs. release dates : </li></ul><ul><ul><li>Noticed number of transistors doubling with release of each new IC generation </li></ul></ul><ul><ul><li>release dates (separate generations) were all 18-24 months apart </li></ul></ul><ul><li>Moore’s Law : </li></ul><ul><ul><li>The number of transistors on an integrated circuit will double every 18 months </li></ul></ul><ul><li>The level of integration of silicon technology as measured in terms of number of devices per IC </li></ul><ul><li>This comes about in two ways – size reduction of the individual devices and increase in the chip or dice size </li></ul><ul><li>As an indication of size reduction, it is interesting to note that feature size was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970’s, whereas now all features are measured in mm’s (1 mm = 10 -6 m or 10 -4 cm) </li></ul><ul><li>Semiconductor industry has followed this prediction with surprising accuracy </li></ul>
    9. 9. <ul><li>In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months </li></ul><ul><ul><li>i.e., grow exponentially with time </li></ul></ul><ul><li>Amazing visionary – million transistor/chip barrier was crossed in the 1980’s. </li></ul><ul><ul><li>2300 transistors, 1 MHz clock (Intel 4004) - 1971 </li></ul></ul><ul><ul><li>42 Million, 2 GHz clock (Intel P4) - 2001 </li></ul></ul><ul><ul><li>140 Million transistor (HP PA-8500) </li></ul></ul>Moore’s Law Source: Intel web page (www.intel.com)
    10. 10. Moore’s Law <ul><li>From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond </li></ul>Relative sizes of ICs in graph
    11. 11. Ever since the invention of integrated circuit, the smallest feature size has been reducing every year. Currently (2002) the smallest feature size is about 0.13 micron. At the same time the number transistors per chip is increasing due to feature size reduction and increase in chip area. Classic example is the case of memory chips: Gordon Moore of Intel in early 1970s found that: “density” (bits per chip) growing at the rate of four times in 3 to 4 years - often referred to as Moore’s Law. In subsequent years, the pace slowed down a bit, data density has doubled approximately every 18 months – current definition of Moore’s Law .
    12. 12. Limits of Moore’s Law? <ul><li>Growth expected until 30 nm gate length (currently: 180 nm) </li></ul><ul><ul><li>size halved every 18 mos. - reached in </li></ul></ul><ul><ul><ul><li>2001 + 1.5 log 2 ((180/30) 2 ) = 2009 </li></ul></ul></ul><ul><ul><li>what then? </li></ul></ul><ul><li>Paradigm shift needed in fabrication process </li></ul>
    13. 13. Technological Background of the Moore’s Law <ul><li>To accommodate this change, the size of the silicon wafers on which the integrated circuits are fabricated have also increased by a very significant factor – from the 2 and 3 in diameter wafers to the 8 in (200 mm) and 12 in (300 mm) diameter wafers </li></ul><ul><li>The latest catch phrase in semiconductor technology (as well as in other material science) is nanotechnology – usually referring to GaAs devices based on quantum mechanical phenomena </li></ul><ul><li>These devices have feature size (such as film thickness, line width etc) measured in nanometres or 10 -9 metres </li></ul>
    14. 14. Recurring Costs <ul><ul><li> cost of die + cost of die test + cost of packaging </li></ul></ul><ul><ul><li>variable cost = ---------------------------------------------------------------- </li></ul></ul><ul><ul><li> final test yield </li></ul></ul><ul><ul><li> cost of wafer </li></ul></ul><ul><ul><li>cost of die = ----------------------------------- </li></ul></ul><ul><ul><li> dies per wafer × die yield </li></ul></ul><ul><ul><li> × (wafer diameter/2) 2  × wafer diameter </li></ul></ul><ul><ul><li>dies per wafer = ----------------------------------  --------------------------- </li></ul></ul><ul><ul><li>die area  2 × die area </li></ul></ul><ul><ul><li>die yield = (1 + (defects per unit area × die area)/  ) -  </li></ul></ul>
    15. 15. Yield Example <ul><li>Example </li></ul><ul><ul><li>wafer size of 12 inches, die size of 2.5 cm 2 , 1 defects/cm 2 ,  = 3 (measure of manufacturing process complexity) </li></ul></ul><ul><ul><li>252 dies/wafer (remember, wafers round & dies square) </li></ul></ul><ul><ul><li>die yield of 16% </li></ul></ul><ul><ul><li>252 x 16% = only 40 dies/wafer die yield ! </li></ul></ul><ul><li>Die cost is strong function of die area </li></ul><ul><ul><li>proportional to the third or fourth power of the die area </li></ul></ul>
    16. 16. Intel 4004 Microprocessor
    17. 17. Intel Pentium (IV) Microprocessor
    18. 18. Die Size Growth Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 1970 1980 1990 2000 2010 Year Die size (mm) ~7% growth per year ~2X growth in 10 years
    19. 19. Clock Frequency Lead microprocessors frequency doubles every 2 years P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 1000 10000 1970 1980 1990 2000 2010 Year Frequency (Mhz) 2X every 2 years Courtesy, Intel
    20. 20. Examples of Cost Metrics (1994) $417 9% 40 296 1.5 $1500 0.80 3 Pentium $272 13% 48 256 1.6 $1700 0.70 3 Super SPARC $149 19% 53 234 1.2 $1500 0.70 3 DEC Alpha $73 27% 66 196 1.0 $1300 0.80 3 HP PA 7100 $53 28% 115 121 1.3 $1700 0.80 4 PowerPC 601 $12 54% 181 81 1.0 $1200 0.80 3 486DX2 $4 71% 360 43 1.0 $900 0.90 2 386DX Die cost Yield Dies/wafer Area (mm 2 ) Defects/cm 2 Wafer cost Line width Metal layers Chip
    21. 21. VLSI <ul><li>Very Large Scale Integration </li></ul><ul><ul><li>design/manufacturing of extremely small, complex circuitry using modified semiconductor material </li></ul></ul><ul><ul><li>integrated circuit (IC) may contain millions of transistors, each a few  m in size </li></ul></ul><ul><ul><li>applications wide ranging: most electronic logic devices </li></ul></ul>
    22. 22. Origins of VLSI <ul><li>Much development motivated by WWII need for improved electronics, especially for radar </li></ul><ul><li>1940 - Russell Ohl (Bell Laboratories) - first pn junction </li></ul><ul><li>1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - first transistor </li></ul><ul><ul><li>1956 Nobel Physics Prize </li></ul></ul><ul><li>Late 1950s - purification of Si advances to acceptable levels for use in electronics </li></ul><ul><li>1958 - Seymour Cray (Control Data Corporation) - first transistorized computer - CDC 1604 </li></ul>
    23. 23. Origins of VLSI (Cont.) <ul><li>1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components on 9 mm 2 </li></ul><ul><li>1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated circuit </li></ul><ul><li>1968 - Noyce, Gordon E. Moore found Intel </li></ul><ul><li>1971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300 transistors on 9 mm 2 </li></ul><ul><li>Since then - continued improvement in technology has allowed for increased performance as predicted by Moore’s Law </li></ul>
    24. 24. Three Dimensional VLSI <ul><li>The fabrication of a single integrated circuit whose functional parts (transistors, etc) extend in three dimensions </li></ul><ul><li>The vertical orientation of several bare integrated circuits in a single package </li></ul>
    25. 25. Advantages of 3D VLSI <ul><li>Speed - the time required for a signal to travel between the functional circuit blocks in a system (delay) reduced. </li></ul><ul><ul><li>Delay depends on resistance/capacitance of interconnections </li></ul></ul><ul><ul><li>resistance proportional to interconnection length </li></ul></ul>
    26. 26. Advantages of 3D VLSI <ul><li>Noise - unwanted disturbances on a useful signal </li></ul><ul><ul><li>reflection noise (varying impedance along interconnect) </li></ul></ul><ul><ul><li>crosstalk noise (interference between interconnects) </li></ul></ul><ul><ul><li>electromagnetic interference (EMI) (caused by current in pins) </li></ul></ul><ul><li>3D chips </li></ul><ul><ul><li>fewer, shorter interconnects </li></ul></ul><ul><ul><li>fewer pins </li></ul></ul>
    27. 27. Advantages of 3D VLSI <ul><li>Power consumption </li></ul><ul><ul><li>power used charging an interconnect capacitance </li></ul></ul><ul><ul><ul><li>P = fCV 2 </li></ul></ul></ul><ul><ul><li>power dissipated through resistive material </li></ul></ul><ul><ul><ul><li>P = V 2 /R </li></ul></ul></ul><ul><ul><li>capacitance/resistance proportional to length </li></ul></ul><ul><ul><li>reduced interconnect lengths will reduce power </li></ul></ul>
    28. 28. Advantages of 3D VLSI <ul><li>Interconnect capacity (connectivity) </li></ul><ul><ul><li>more connections between chips </li></ul></ul><ul><ul><li>increased functionality, ease of design </li></ul></ul>
    29. 29. Advantages of 3D VLSI <ul><li>Printed circuit board size/weight </li></ul><ul><ul><li>planar size of PCB reduced with negligible IC height increase </li></ul></ul><ul><ul><li>weight reduction due to more circuitry per package/smaller PCBs </li></ul></ul><ul><ul><li>estimated 40-50 times reduction in size/weight </li></ul></ul>
    30. 30. 3D VLSI - Challenges and Solutions <ul><li>Challenge: Thermal management </li></ul><ul><ul><li>smaller packages </li></ul></ul><ul><ul><li>increased circuit density </li></ul></ul><ul><ul><li>increased power density </li></ul></ul><ul><li>Solutions: </li></ul><ul><ul><li>circuit layout (design stage) </li></ul></ul><ul><ul><ul><li>high power sections uniformly distributed </li></ul></ul></ul><ul><ul><li>advancement in cooling techniques (heat pipes) </li></ul></ul>
    31. 31. Influential Participants - Industry <ul><li>Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others... </li></ul><ul><ul><li>high density memories </li></ul></ul><ul><li>AT&T </li></ul><ul><ul><li>high density “multiprocessor” </li></ul></ul><ul><li>Many other applications/participants </li></ul>
    32. 32. Three Dimensional VLSI <ul><li>Moore’s Law approaching physical limit </li></ul><ul><li>Increased performance expected by market </li></ul><ul><li>Paradigm shift needed - 3D VLSI </li></ul><ul><ul><li>many advantages over 2D VLSI </li></ul></ul><ul><ul><li>economic limitations of fabrication overhaul will be overcome by market demand </li></ul></ul><ul><li>Three Dimensional VLSI may be the savior of Moore’s Law </li></ul>
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