GATE STACK DESIGN<br />BY: OreoluwaOdubela<br />AdemakinwaAdetoro<br />Axel Brugger<br />
Contents<br />Introduction and History of gate stack design<br />Moore’s law and transistor development<br />Gate oxide is...
Introduction <br />Basic CMOS Transistor<br />The gate dielectric is at the heart of every MOS transistor device.<br />MOS...
More Moore’s Law!<br />Moore’s law [1]<br />Transistor Development (1971-2015)<br />Oreoluwa Odubela (200364760)<br />*** ...
Intel’s microprocessors [2]<br />Oreoluwa Odubela (200364760)<br />
ELEC5200: Next Generation Silicon Technologies<br />Gate Stack Design<br />Gate Oxide Issues and High k Material<br />Adem...
Gate Oxide issues and High K Material<br />Introduction<br /><ul><li> Over the past decades, the transistors has continual...
 Intel is leading the race in this area with production of 32nm feature size in late 2009.
The roadmap for semiconductor industry in ITRS set the pace for MOSFET Developments.</li></li></ul><li>Gate Oxide issues a...
Junction depth
Supply voltage</li></li></ul><li>Gate Oxide issues and High K Material<br /> Reasons for Scaling:<br /> Smaller transistor...
Gate Oxide issues and High K Material<br /> Reasons for Scaling:<br />W=width of the channel , L=channel length <br />µ=ch...
Gate Oxide issues and High K Material<br /><ul><li>Make smaller chip with same number of transistors </li></ul>  a. Increa...
Gate Oxide issues and High K Material<br />Challenges of  Scaling:<br /><ul><li>Heat production
Increased gate –oxide leakage
Increased junction leakage
Lower output resistance
Lower transconductance
Interconnect capacitance
Higher sub threshold conduction
Process variation
Modelling Challenges.</li></li></ul><li>Gate Oxide issues and High K Material<br />What is the Problem as transistor are m...
Gate Oxide issues and High K Material<br />Seeking new materials to drive Moore‘s Law<br />Power -industry recognizes that...
Gate Oxide issues and High K Material<br />What is an high k Material?<br /><ul><li>The industry is searching for an SiO2 ...
Gate Oxide issues and High K Material<br />High k Material and it advantage<br />Benefit of using High k material compared...
Gate Oxide issues and High K Material<br />New High k Material <br /><ul><li>As the SiO2 dielectric become so thin, we are...
Without a new dielectric material with increased thickness and a higher K value, Moore’s Law would inevitably hit a wall.
In addition to its dielectric properties, SiO2 has an almost defect-free dielectric interface.</li></li></ul><li>Gate Oxid...
The power and heat issue is huge and industry has been searching for solutions for a long time. Intel has solved a major p...
Intel has achieved world record performance at dramatically reduced leakage with its new transistor .
Intel is on track and has put this new transistor design into production since 2007.</li></li></ul><li>Poly-Si replacement...
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Gatestackdesign updated

  1. 1. GATE STACK DESIGN<br />BY: OreoluwaOdubela<br />AdemakinwaAdetoro<br />Axel Brugger<br />
  2. 2. Contents<br />Introduction and History of gate stack design<br />Moore’s law and transistor development<br />Gate oxide issues and High-k materials<br />Poly-Si replacement and Gate stack processing issues<br />Present gate stack design and future development<br />Summary<br />References and useful websites<br />Questions/Comments....<br />Oreoluwa Odubela (200364760)<br />
  3. 3. Introduction <br />Basic CMOS Transistor<br />The gate dielectric is at the heart of every MOS transistor device.<br />MOS capacitors supply charge that switch the transistor on and off.<br />To maintain/ improve the switching frequency as transistors shrink a smaller channel must carry the same amount of drive current<br />IC manufacturers increase capacitance by making the dielectric thinner.<br />Oreoluwa Odubela (200364760)<br />
  4. 4. More Moore’s Law!<br />Moore’s law [1]<br />Transistor Development (1971-2015)<br />Oreoluwa Odubela (200364760)<br />*** Leakage current limited further scaling.<br />
  5. 5. Intel’s microprocessors [2]<br />Oreoluwa Odubela (200364760)<br />
  6. 6. ELEC5200: Next Generation Silicon Technologies<br />Gate Stack Design<br />Gate Oxide Issues and High k Material<br />Ademakinwa ADETORO/200500789<br />
  7. 7. Gate Oxide issues and High K Material<br />Introduction<br /><ul><li> Over the past decades, the transistors has continually been scaled down in sizes, typical transistor channel length were once several micrometers but modern IC’s are incorporating transistors with channel length of about 10’s of nanometres.
  8. 8. Intel is leading the race in this area with production of 32nm feature size in late 2009.
  9. 9. The roadmap for semiconductor industry in ITRS set the pace for MOSFET Developments.</li></li></ul><li>Gate Oxide issues and High K Material<br /><ul><li>There are identified drawbacks associated with decreasing the size of transistors, such include the need to use very low voltages, fabrication process, and with poorer electrical performance necessitating circuit redesign.</li></ul>What to Scale?:<br /><ul><li>Lithographic dimensions known as critical dimension (CD) </li></ul> a. Gate length and Gate width <br /> b. Contact sizes <br /><ul><li> Oxide thickness
  10. 10. Junction depth
  11. 11. Supply voltage</li></li></ul><li>Gate Oxide issues and High K Material<br /> Reasons for Scaling:<br /> Smaller transistors are desirable for several key reasons:<br /><ul><li>Improve device performance</li></ul> Switching speed increases with shrinking dimensions <br /> a. Shorter transit time <br /> b. Higher capacitance <br />A=capacitor area ,t=thickness of dielectric <br />K=relative dielectric constant of the material <br />EO= permittivity of free space <br />
  12. 12. Gate Oxide issues and High K Material<br /> Reasons for Scaling:<br />W=width of the channel , L=channel length <br />µ=channel carrier mobility , Vg=gate voltage <br />COX =capacitance density associated with gate dielectric when the underlying channel is in the inverted state <br />Vd=drain voltage , Vt=threshold voltage<br />
  13. 13. Gate Oxide issues and High K Material<br /><ul><li>Make smaller chip with same number of transistors </li></ul> a. Increase in number of chips/wafer <br /> b. Increase in chip yield <br />Moore’s Law<br />
  14. 14. Gate Oxide issues and High K Material<br />Challenges of Scaling:<br /><ul><li>Heat production
  15. 15. Increased gate –oxide leakage
  16. 16. Increased junction leakage
  17. 17. Lower output resistance
  18. 18. Lower transconductance
  19. 19. Interconnect capacitance
  20. 20. Higher sub threshold conduction
  21. 21. Process variation
  22. 22. Modelling Challenges.</li></li></ul><li>Gate Oxide issues and High K Material<br />What is the Problem as transistor are made Smaller?<br /><ul><li>Smaller transistor are faster, cheaper, compact , less power hungry but…….</li></ul> Gate dielectrics, traditionally made with Silicon Dioxide (SiO2), are only a few atomic layers thick.<br />SiO2 is ideally an insulator, but at this thinness, current leaks through <br />–Think of a faucet that drips when it should be off.<br />A new material is needed to reduce leakage!<br />
  23. 23. Gate Oxide issues and High K Material<br />Seeking new materials to drive Moore‘s Law<br />Power -industry recognizes that high--k is needed!<br />
  24. 24. Gate Oxide issues and High K Material<br />What is an high k Material?<br /><ul><li>The industry is searching for an SiO2 replacement</li></ul> –Intel has led SiO2 gate oxide scaling for over a decade.<br /><ul><li>This material should be thicker (to reduce leakage) but should have a high “k” value .</li></ul> –“k”, the dielectric constant of a material, “relates directly to the transistor’s performance.<br /> –When the faucet is turned on, water should gush out and vice versa.<br />
  25. 25. Gate Oxide issues and High K Material<br />High k Material and it advantage<br />Benefit of using High k material compared with previous technology<br />
  26. 26. Gate Oxide issues and High K Material<br />New High k Material <br /><ul><li>As the SiO2 dielectric become so thin, we are literally running out of atoms for further scaling.
  27. 27. Without a new dielectric material with increased thickness and a higher K value, Moore’s Law would inevitably hit a wall.
  28. 28. In addition to its dielectric properties, SiO2 has an almost defect-free dielectric interface.</li></li></ul><li>Gate Oxide issues and High K Material<br />Summary and Conclusion:<br /><ul><li>Researchers have removed the industry’s most challenging road block to ensuring Moore’s Law spans into the next decade, ultimately leading to vast, lower cost computing power and enabling applications that cannot be imagined today .
  29. 29. The power and heat issue is huge and industry has been searching for solutions for a long time. Intel has solved a major part of the problem by integrating new materials into transistors.
  30. 30. Intel has achieved world record performance at dramatically reduced leakage with its new transistor .
  31. 31. Intel is on track and has put this new transistor design into production since 2007.</li></li></ul><li>Poly-Si replacement & Gate Stack Design<br />By: Axel Brugger<br />
  32. 32. Poly-Si replacement and Gate stack processing issues<br />Advantages<br /><ul><li> Use of self-aligned structure
  33. 33. Reduction of overlap capacitances (Miller effect)
  34. 34. Reduction of threshold voltage by 1.1V (~30%) due to a lower work function Φ
  35. 35. 3-5x faster and 3-5x less power consumption
  36. 36. Cost effective: SGT uses ~ ½ the silicon area
  37. 37. Higher device reliability: Reduction of junction leakage current</li></li></ul><li>Poly-Si replacement and Gate stack processing issues<br />Disadvantages<br /><ul><li> Weak compatibility with high-ĸ (e.g. HfO2)
  38. 38. Thermal stability requirements to be 1000 °C for 10s (ITRS)
  39. 39. Gate leakage and yield determine performance
  40. 40. Area dependence suggests yield failures for higher gate-leakage
  41. 41. ‘Si indiffusion’ results in leakage paths</li></li></ul><li>Poly-Si replacement and Gate stack processing issues<br />Poly-Si vs. Metal<br /><ul><li> Poly-Si lacks sufficient charge carriers
  42. 42. Result: Depletion at the dielectric interface when transistor channel is in inversion
  43. 43. What to do about it ?
  44. 44. higher inversion capacitance required
  45. 45. Poly-Si has high resistivity  limits drive current</li></li></ul><li>Poly-Si replacement and Gate stack processing issues<br />Gate Stack Processing Issues<br /><ul><li> Multiple drawbacks of high-k
  46. 46. Reduction of electron mobility in metal gate / high-k gate dielectric stacks compared to Poly-Si/SiO2 gate stacks.
  47. 47. Degradation mainly due to ‘Remote Phonon Scattering’</li></li></ul><li>Poly-Si replacement and Gate stack processing issues<br />Solutions ?<br /><ul><li> Silicon Oxide layer between channel within the Si substrate and the high-k gate dielectric
  48. 48. Mobility increases with annealing temperature
  49. 49. Still do not achieve the same results as that of SiO2</li></li></ul><li>Present Gate stack design<br />For many years, Si02 had been the gate dielectric used in MOS devices<br />Current leakage limited further scaling around node 90nm and 65nm<br />The introduction of gate stack design involving high-k/metal gate has enabled the resumption of Moore’s law at 45 & 32nm nodes.<br />In 2009 Intel was the first company to demonstrate a working 32nm node processor<br />They have included this device in the 2010 production of the 2nd generation Intel core computers.<br />IBM and AMD have joined forces to produce a 32nm processor due for production in 2011.<br />Oreoluwa Odubela (200364760)<br />
  50. 50. Future Development<br />According to Moore’ law we should see a trend in transistor development as such:<br />High-k metal gate structures will be more prevalent than Si02<br />There may be a move from planar CMOS to the use of tri-gate (Intel) and FinFET (AMD, IBM, Motorola) transistors<br />Oreoluwa Odubela (200364760)<br />
  51. 51. Oreoluwa Odubela (200364760)<br />Source: Nanotechnology in the Semiconductor Industry by: Hans Stork, PhD.<br />Conclusion: <br /><ul><li>As device structures get smaller , gate stack structures might have to change to ensure that maximum transistor efficiencies are achievable.
  52. 52. The extent at which transistors continue to shrink will be determined by how commercially viable their production remain.</li></li></ul><li>Gate Oxide issues and High K Material<br />References:<br /><ul><li>Gate Stack Technology for Next 25 Years by Hiroshi Iwai
  53. 53. Intel’s High-k/Metal Gate Announcement November 4th, 2003 Presentation Paper.
  54. 54. Seminar on High K Dielectric Solution for MOSFET scaling Final Report by GECKozhikkode
  55. 55. Challenges in gate stack engineering by Robert W. Murto, Mark I. Gardner, George A. Brown, Peter M. Zeitzoff, Howard R. Huff, International Sematech, Austin, Texas
  56. 56. Intel’s Breakthrough in High-K Gate Dielectric Drives Moore’s Law Well into the Future by Robert S. Chau</li></li></ul><li>Oreoluwa Odubela (200364760)<br />Poly-Si replacement and Gate stack processing issues<br />References<br /><ul><li> ‘Electronic Materials and Devices’, S.O. Kasap
  57. 57. ‘High k-dielectrics’, Michel Houssa
  58. 58. ‘On the mobility in high-j/metal gate MOSFETs: Evaluation</li></ul>of the high-j phonon scattering impact’, Olivier Weber, MikaelCasse´, Laurent Thevenod a, Fre´de´riqueDucroquet,<br />Thomas Ernst, Simon Deleonibus<br /><ul><li> ‘Methodofforming metal/high-k GateStackswithhighmobility’, WandaAdreoni, Alessandro Curioni, RajaroJammy</li></li></ul><li>Useful websites<br />[1],[2] www.intel.com<br />http://ewh.ieee.org/r6/san_francisco/nntc/events/HANS%20STORK-IEEENanoTech2010.pdf<br />: http://www.electroiq.com/index/display/semiconductors-article-display/0982114112/articles/solid-state-technology/semiconductors/device-architecture/transistors/2010/november/cmp-for-metal-gate-integration-in-advanced-cmos-transistors.html<br />Oreoluwa Odubela (200364760)<br />
  59. 59. Questions/ Comments<br />OreoluwaOdubela (200364760)<br />Thank You!!!<br />

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