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Melp codec optimization using DSP kit
 

Melp codec optimization using DSP kit

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Because of bandwidth constraint, low bit-rate vocoders have gained increasing prominence in many digital voice communications systems including the Internet. The requirement of secure voice ...

Because of bandwidth constraint, low bit-rate vocoders have gained increasing prominence in many digital voice communications systems including the Internet. The requirement of secure voice transmission by appropriate encryption and decryption has also prompted the widespread use of digital speech coding techniques in various military applications.
This project is about speech compression using MELP codec, stands for Mixed Excitation Linear Predictive encoding. It is based on a new communication standard developed for extremely low bit data rate. The processing time required for MELP is very large limiting its use in real time applications such as handheld radio transceiver, etc. The theme of the project is to reduce MELP processing time using different optimization techniques. Texas instrument also launched a special DSP processor TMS320C55x series which is well suited for MELP codec processing.

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    Melp codec optimization using DSP kit Melp codec optimization using DSP kit Presentation Transcript

    • Digital Baseband Transceiver
    • Digital communication system
    • Digital communication system
    • Digital communication system
    • Digital communication system
    • Digital communication system
    • Digital communication system
    • Digital communication system
    • Digital communication system
    • Audio compression is a form of data compression designed to reduce the size of audio files.
      Speech coding is the application of data compressionof digital audio signals containing speech.
      Source Encoder
    • Mixed Excitation Linear Predictive(MELP)
      A MELP vocoder uses a mixed-excitation model based on a traditional LPC parametric model, but includes the additional features of mixed-excitation, periodic pulses, pulse dispersion and adaptive spectral enhancement.
    • MELP Characteristics
      Sampling rate 8000Hz
      Frame size 180 samples
      Bits/Sample 16bits
      Frame duration 22.5 ms
      Bit Rate 2.4Kbps
    • Project is about speech compression using MELP codec
      MELP is developed for extremely low bit data rate
      Optimization of MELP to reduce its processing time
      The project is designed for HF range communication
      THEME OF PROJECT
    • Features of the SigC55x MELP System include
      Multichannel real-time performance.
      Flexible audio interface.
      Small form-factor for MELP production systems
    • CPU architecture consists of the following four units.
      Instruction buffer unit
      Program flow unit
      Address data flow unit
      Data computation unit
      DSP TMS320C55x CPU ARCHITECTURE
    • Instruction buffer unit
      Decodes instruction
      Decode logic unit
      Maintains constant stream of tasks for computational units
    • Program flow unit
      keeps track of the execution point within the program
      Hardware loop control
      Pipeline protection
    • Address data flow unit
      Provides the address pointers for data accesses
      Dedicated hardware for managing the five data buses
      Increases the instruction level parallelism
    • Data computation unit
      Heart of the DSP
      Performs the arithmetic computations
      It includes
      • The MACs
      • The main ALU
      • The accumulator registers
      • Barrel shifter
      • Rounding & saturation control
    • TMS320C55x Tabular Description
    • Overview of the CPU Architecture
    • Using intrinsic
      Optimization level of compiler
      Assembly language tools
      Parallelism
      Pipelining
      Efficient looping
      Optimization Techniques
    • Using intrinsic
      ETSI functions
      Predefined functions by TEXAS instruments
      GSM.h
      Replacement for ETSI function
    • Three levels of optimization
      O0
      O1
      O2
      O3
      Optimization level of compiler
      • Allocates variables to registers
      • Eliminates unused code
      • Simplifies expressions and statements
      • Expands calls to functions declared inline
      -O0 Optimization level
    • -O1 Optimization level
      Performs all -O0 optimizations
      Performs local copy/constant propagation
      Removes unused assignments
    • -O2 Optimization level
      Performs all -O1 optimizations
      Performs loop optimizations
      Eliminates global unused assignments
      Performs loop unrolling
    • Performs all -O2 optimizations
      Removes all functions that are never called
      Inline calls to small functions.
      Reorders function declarations so that the attributes of called functions are known when the caller is optimized
      -O3 Optimization level
    • Create loops that efficiently use C55x hardware loops, MAC hardware, and dual-MAC hardware.
      Use intrinsics to replace complicated C/C++ code
      Use long accesses to reference 16-bit data in memory
       Refining the C/C++ Code:
    • Parallelism
      Built in parallelism
      Example 
      Dual Mac
      MAC *AR2+, *CDP+, AC0
      :: MAC *AR3+, *CDP+, AC1
      User defined parallel
      AC1 = AC1 + (*AR4+ * coef (*CDP+))
      || repeat (CSR)
      ASSEMBLY LANGUAGE TOOLS
    • Efficient looping
      Loop unrolling
      Single repeat: repeat(CSR/k8/k16)
      Local block repeat: localrepeat{}
      Block repeat: blockrepeat{}
      Branch on auxiliary register not zero
      ASSEMBLY LANGUAGE TOOLS
    • Efficient looping
      Loop unrolling
      Loop unrolling involves structuring computations to exploit the reuse of data among different time or geometric iterations of the algorithm
    • Single repeat
      There are advantages to using CSR for the repeat count:
      • The repeat count can be dynamically computed during runtime and stored to CSR.
      • Using CSR saves outer loop cycles when the single-repeat loop is an inner loop.
      • An optional syntax extension enables the repeat instruction to modify the CSR after copying the content of CSR to RPTC.
      Efficient looping
    • Local block repeat
      Its mechanism provides a way to repeat a block from the instruction buffer queue.
      Advantages
      • Fewer program-memory access pipeline conflicts
      • Overall lower power consumption
      • No repetition of wait-state and access penalties when executing loop code from external RAM
      Efficient looping
    • Block repeat
      Its mechanism always refetches the loop code from memory.
      When you nest a block-repeat loop inside another block-repeat loop, initialize the block-repeat counters (BRC0 and BRC1) in the code outside of both loops.
      Efficient looping
    • Branch on auxiliary register not zero
      This instruction performs a conditional branch (selected auxiliary register content not equal to 0) of the program counter (PC).
      Efficient looping
    • Pipelining
      The C55x CPU uses instruction pipelining.
      Pipeline Phases
      The C55x instruction pipeline is a protected pipeline that has two decoupled segments:
      •   The first segment, referred to as the fetch pipeline, fetches 32-bit instruction packets from memory, places them in the instruction buffer queue (IBQ), and then feeds the second pipeline segment with 48-bit instruction packets.
      • The second segment, referred to as the execution pipeline, decodes instructions and performs data accesses and computations.
       
       
      Assembly language tools
    • Results
    • Muhammad SohaibAslam
      Presented By
    • Special Thanks
      Our special thanks to all those who cooperate and guide. Under there supervision I am able to complete this project.