7493

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7493

  1. 1. INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT93 4-bit binary ripple counterProduct specification December 1990File under Integrated Circuits, IC06
  2. 2. Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93FEATURES divide-by-two section and a the device may be operated in various divide-by-eight section. Each section counting modes. In a 4-bit ripple• Various counting modes has a separate clock input (CP0 and counter the output Q0 must be• Asynchronous master reset CP1) to initiate state changes of the connected externally to input CP1.• Output capability: standard counter on the HIGH-to-LOW clock The input count pulses are applied to transition. State changes of the Qn clock input CP0. Simultaneous• ICC category: MSI outputs do not occur simultaneously frequency divisions of 2, 4, 8 and 16 because of internal ripple delays. are performed at the Q0, Q1, Q2 andGENERAL DESCRIPTION Therefore, decoded output signals Q3 outputs as shown in the function are subject to decoding spikes and table. As a 3-bit ripple counter theThe 74HC/HCT93 are high-speed should not be used for clocks or input count pulses are applied to inputSi-gate CMOS devices and are pin strobes. CP1.compatible with low power Schottky Simultaneous frequency divisions ofTTL (LSTTL). They are specified in A gated AND asynchronous master 2, 4 and 8 are available at the Q1, Q2compliance with JEDEC standard reset (MR1 and MR2) is provided and Q3 outputs. Independent use ofno. 7A. which overrides both clocks and the first flip-flop is available if the reset resets (clears) all flip-flops.The 74HC/HCT93 are 4-bit binary function coincides with reset of theripple counters. The devices consist Since the output from the 3-bit ripple-through counter.of four master-slave flip-flops divide-by-two section is not internallyinternally connected to provide a connected to the succeeding stages,QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICALSYMBOL PARAMETER CONDITIONS UNIT HC HCTtPHL/ tPLH propagation delay CP0 to Q0 12 15 ns CL = 15 pF; VCC = 5 Vfmax maximum clock frequency 100 77 MHzCI input capacitance 3.5 3.5 pFCPD power dissipation capacitance per package notes 1 and 2 22 22 pFNotes1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF; VCC = supply voltage in V2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 VORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.December 1990 2
  3. 3. Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93PIN DESCRIPTIONPIN NO. SYMBOL NAME AND FUNCTION1 CP1 clock input 2nd, 3rd and 4th section (HIGH-to-LOW, edge-triggered)2, 3 MR1, MR2 asynchronous master reset (active HIGH)4, 6, 7, 13 n.c. not connected5 VCC positive supply voltage10 GND ground (0 V)12, 9, 8, 11 Q0 to Q3 flip-flop outputs14 CP0 clock input 1st section (HIGH-to-LOW, edge-triggered) Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.December 1990 3
  4. 4. Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93 FUNCTION TABLE OUTPUTS COUNT Q0 Q1 Q2 Q3 0 L L L L 1 H L L L 2 L H L L 3 H H L L 4 L L H L 5 H L H L 6 L H H L 7 H H H L 8 L L L H 9 H L L H 10 L H L H Fig.4 Functional diagram. 11 H H L H 12 L L H H 13 H L H H 14 L H H H 15 H H H H Notes 1. Output Q0 connected to CP1. H = HIGH voltage level L = LOW voltage level MODE SELECTION RESET OUTPUTS INPUTS MR1 MR2 Q0 Q1 Q2 Q3 H H L L L L L H count H L count L L count Fig.5 Logic diagram.December 1990 4
  5. 5. Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.Output capability: standardICC category: MSIAC CHARACTERISTICS FOR 74HCGND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCSYMBOL PARAMETER UNIT V +25 −40 to +85 −40 to +125 CC WAVEFORMS (V) min. typ. max. min. max. min. max.tPHL/ tPLH propagation delay 41 125 155 190 ns 2.0 Fig.6 CP0 to Q0 15 25 31 38 4.5 12 21 26 32 6.0tPHL/ tPLH propagation delay 49 135 170 205 ns 2.0 Fig.6 CP1 to Q1 16 27 34 41 4.5 13 23 29 35 6.0tPHL/ tPLH propagation delay 61 185 230 280 ns 2.0 Fig.6 CP1 to Q2 22 37 46 56 4.5 18 31 39 48 6.0tPHL/ tPLH propagation delay 80 245 305 370 ns 2.0 Fig.6 CP1 to Q3 29 49 61 71 4.5 23 42 52 63 6.0tPHL propagation delay 50 155 195 235 ns 2.0 Fig.7 MRn to Qn 18 31 39 47 4.5 14 26 33 40 6.0tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Fig.6 7 15 19 22 4.5 6 13 16 19 6.0trem removal time 50 8 65 75 ns 2.0 Fig.7 MRn to CP0, CP1 10 3 13 15 4.5 9 2 11 13 6.0tW pulse width 80 14 100 120 ns 2.0 Fig.6 CP0, CP1 16 5 20 24 4.5 14 4 17 20 6.0tW master reset pulse width 80 14 100 120 ns 2.0 Fig.7 MRn 16 5 20 24 4.5 14 4 17 20 6.0fmax maximum clock pulse 6.0 30 4.8 4.0 MHz 2.0 Fig.6 frequency 30 91 24 20 4.5 CP0, CP1 35 108 28 24 6.0December 1990 5
  6. 6. Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.Output capability: standardICC category: MSINote to HCT typesThe value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.INPUT UNIT LOAD COEFFICIENTCP0, CP1 0.60MRn 0.40AC CHARACTERISTICS FOR 74HCTGND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCTSYMBOL PARAMETER UNIT V +25 −40 to +85 −40 to +125 CC WAVEFORMS (V) min. typ. max. min. max. min. max.tPHL/ tPLH propagation delay 18 34 43 51 ns 4.5 Fig.6 CP0 to Q0tPHL/ tPLH propagation delay 18 34 43 51 ns 4.5 Fig.6 CP1 to Q1tPHL/ tPLH propagation delay 24 46 58 69 ns 4.5 Fig.6 CP1 to Q2tPHL/ tPLH propagation delay 30 58 73 87 ns 4.5 Fig.6 CP1 to Q3tPHL propagation delay 17 33 41 50 ns 4.5 Fig.7 MRn to QntTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6trem removal time 10 3 13 15 ns 4.5 Fig.7 MRn to CP0, CP1tW pulse width 16 7 20 24 ns 4.5 Fig.6 CP0, CP1tW master reset pulse width 16 5 20 24 ns 4.5 Fig.7 MRnfmax maximum clock pulse 30 70 24 20 MHz 4.5 Fig.6 frequency CP0, CP1December 1990 6
  7. 7. Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CPn) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the master reset (MRn) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CPn) removal time.PACKAGE OUTLINESSee “74HC/HCT/HCU/HCMOS Logic Package Outlines”.December 1990 7

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