2008 IEDM presentation

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World record GaAs Esaki reported on a Si substrate

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2008 IEDM presentation

  1. 1. Record PVCR GaAs-based Tunnel Diodes Fabricated on Si Substrates using Aspect Ratio Trapping S. L. Rommel 1 , D. Pawlik 1 , P. Thomas 1 , M. Barth 1 , K. Johnson 1 , S. Kurinec 1 , A. Seabaugh 2 , Z. Cheng 3 , J. Li 3 , J. Park 3 , J. Hydrick 3 , N. Bai 3 , M. Carroll 3 , J. G. Fiorenza 3 , and A. Lochtefeld 3 1 Department of Microelectronic Engineering, Rochester Institute of Technology, Rochester, NY 14623 USA 2 Department of Electrical Engineering, University of Notre Dame, South Bend, IN 46556 USA 3 Amberwave Systems Corporation, Salem, NH 03079-4235 USA
  2. 2. <ul><ul><li>Motivation : </li></ul></ul><ul><ul><ul><li>Why use tunnel diodes? </li></ul></ul></ul><ul><ul><ul><li>Why use III-V tunnel diodes? </li></ul></ul></ul><ul><ul><li>Enabling Technology : “Aspect Ratio Trapping” (ART) </li></ul></ul><ul><ul><ul><li>Developed by AmberWave </li></ul></ul></ul><ul><ul><li>World Record GaAs-based Esaki diodes on a Si Substrate </li></ul></ul><ul><ul><ul><li>Fourth highest PVCR ever reported </li></ul></ul></ul><ul><ul><ul><li>Structures are grown entirely by CVD. </li></ul></ul></ul>Outline
  3. 3. Tunnel Diode Characteristics and Applications V I P I V V P V V <ul><li>Goals: </li></ul><ul><li>Demonstrate GaAs tunnel junctions on Si to enable: </li></ul><ul><li>Tunnel SRAM </li></ul><ul><li>Low-subthreshold- swing III-V tunnel transistors </li></ul>n+ p+   PVCR > 10 desired! <ul><li>Degenerate doping </li></ul><ul><li>Abrupt junction </li></ul>
  4. 4. <ul><li>III-V Tunnel Diodes have larger PVCR than Si </li></ul><ul><li>Extensive literature reports of III-V Esaki diodes </li></ul><ul><li>MOCVD has been demonstrated for III-Vs </li></ul>Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si
  5. 5. <ul><li>III-V Tunnel Diodes have larger PVCR than Si </li></ul><ul><li>Extensive literature reports of III-V Esaki diodes </li></ul><ul><li>MOCVD has been demonstrated for III-Vs </li></ul>Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si High Speed Logic Memory
  6. 6. <ul><li>III-V Tunnel Diodes have larger PVCR than Si </li></ul><ul><li>Extensive literature reports of III-V Esaki diodes </li></ul><ul><li>MOCVD has been demonstrated for III-Vs </li></ul>Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si Si Esaki Diodes III-V Esaki Diodes
  7. 7. Silicon Ge SiO 2 500 nm J.S. Park et al., Appl. Phys. Lett 90 052113 (2007) <ul><li>Aspect Ratio Trapping (ART) </li></ul><ul><ul><li>Enables heterointegration of Ge and III-V on Si </li></ul></ul><ul><ul><li>Traps mismatch dislocations in high aspect ratio trenches </li></ul></ul><ul><li>Advantages of ART </li></ul><ul><ul><li>Works on variety of materials (Ge, GaAs, InP) </li></ul></ul><ul><ul><li>Thin buffer layer (100-400 nm) enables integration in CMOS </li></ul></ul><ul><ul><li>Accommodates high lattice mismatch (up to 8% demonstrated) </li></ul></ul><ul><ul><li>Enables selective integration of different materials </li></ul></ul>Aspect Ratio Trapping (ART) Defect Trapping
  8. 8. Aspect Ratio Trapping (ART) H W Ge Si <ul><li>Important Points: </li></ul><ul><ul><ul><li>High trench aspect ratio is the key to trapping defects </li></ul></ul></ul><ul><ul><ul><li>ART reduces defects by 3 orders of magnitude </li></ul></ul></ul>Aspect Ratio = H/W
  9. 9. <ul><li>Approach used for this study: </li></ul><ul><ul><li> Integrate a III-V device atop a coalesced Ge substrate. </li></ul></ul><ul><ul><ul><li>RP-CVD for Ge </li></ul></ul></ul><ul><ul><ul><li>MOCVD for III-V Growth </li></ul></ul></ul>Aspect Ratio Trapping (ART)
  10. 10. Coalesced Ge InGaAs/GaAs TD Strained InGaAs/top contact (Some layers are all InGaAs) Gold Contact GaAs/Ge heterointerface TEM image of Fabricated Device illustrates strained InGaAs diode layer. GaAs/InGaAs Device Concept Si Substrate Ge filled SiO 2 trenches
  11. 11. 50 nm GaAs n-type (Si) >1x10 19 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥1x10 19 cm -3 80 nm GaAs p-type (C) >1x10 20 cm -3 TD1: Baseline Structure <ul><ul><li>T.A. Richard et. al. Appl. Phys. Lett. 63 , pp. 3613-5, (1993) </li></ul></ul><ul><ul><ul><li>PVCR of 21 </li></ul></ul></ul><ul><ul><ul><li>Grown on a GaAs substrate </li></ul></ul></ul><ul><li>Target structure based on published III-V Device (GaAs/In 0.1 Ga 0.9 As) </li></ul>
  12. 12. Strained p-GaAs (C) Strained n-InGaAs (Si) QW, 10nm wide n-GaAs (Si) <ul><ul><li>TEM image confirms the excellent crystal quality and sharp interface. </li></ul></ul><ul><ul><li>SIMS profile of TD1 shows doping in mid-10 19 cm -3 . </li></ul></ul>TD1: TEM image & SIMS profile
  13. 13. <ul><li>Post growth anneal removes H 2 from epi growth; Richard et. al. </li></ul><ul><ul><li>Result: Large increase in PVCR </li></ul></ul><ul><li>Similar trend is observed here: </li></ul><ul><ul><li>No anneal : PVCR 2.4 - 7 </li></ul></ul><ul><ul><li>425 o C, 5 min, N 2 : PVCR 24 </li></ul></ul><ul><li>All devices reported use 425 o C, 5 min. N 2 anneal. </li></ul>Influence of Anneal on PVCR
  14. 14. <ul><li>Devices of ~ 3.5  m 2 show larger PVCR of 27 </li></ul><ul><li>Current density is low due to doping levels. </li></ul><ul><li>KEY POINT : </li></ul><ul><li>Exceeds GaAs world record PVCR (25) reported by Holonyak, et. al. </li></ul>TD1: I-V Characteristics
  15. 15. TD1: Temperature Response <ul><li>KEY POINTS : </li></ul><ul><li>Similar response as published GaAs Esaki diodes. </li></ul><ul><li>PVCR remains greater then or equal to the room temperature PVCR of Si/SiGe TDs. </li></ul>
  16. 16. <ul><li>Higher current density (as high as 1 kA/cm 2 ) </li></ul><ul><li>Higher PVCR: 43 </li></ul>TD2: 20% In 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.2 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm GaAs p-type (C) =5x10 19 cm -3 KEY POINT : Increasing In composition elevates current density and PVCR
  17. 17. <ul><li>World Record GaAs PVCR </li></ul><ul><li>Fourth Highest reported PVCR on any material system or Tunnel diode. </li></ul>TD3: All 10% InGaAs Esaki Diode 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm In 0.1 Ga 0.9 As p-type (C) =5x10 19 cm -3 KEY POINTS : 250 A/cm 2
  18. 18. <ul><li>Key points : </li></ul><ul><li>Lower PVCR than other structures </li></ul><ul><ul><li>Due to elimination of quantum well </li></ul></ul>TD4: Graded 10% InGaAs Esaki Diode 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm GaAs p-type (C) =5x10 19 cm -3 10 nm gradedGaAs to In 0.1 Ga 0.9 As n-type 65 A/cm 2
  19. 19. Comparison with Devices in Literature
  20. 20. Comparison with Devices in Literature
  21. 21. Conclusions <ul><ul><li>Enabling Technology : ART </li></ul></ul><ul><ul><ul><li>Developed by AmberWave </li></ul></ul></ul><ul><ul><li>World Record : GaAs-based Esaki diodes </li></ul></ul><ul><ul><ul><li>Fourth highest PVCR reported for any tunnel diode </li></ul></ul></ul><ul><ul><ul><li>Realized on a Si Substrate. </li></ul></ul></ul><ul><ul><ul><li>Structure are grown entirely by CVD. </li></ul></ul></ul><ul><ul><ul><li>Temperature response comparable to bulk GaAs Esaki Diodes </li></ul></ul></ul>
  22. 22. RIT: R. Rafaelle, S. Hubbard, S. Polly, C. Bailey, and SMFL Staff Amberwave: M. Curtin, C. Major and the other lab staff Micron Technology: D. MacMahon (TEM imaging) Silvaco Corporation: TCAD software donation Project supported by National Science Foundation grants ECCS-0725760 and ECCS-0832653 Acknowledgements

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