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World record GaAs Esaki reported on a Si substrate

World record GaAs Esaki reported on a Si substrate

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  • 1. Record PVCR GaAs-based Tunnel Diodes Fabricated on Si Substrates using Aspect Ratio Trapping S. L. Rommel 1 , D. Pawlik 1 , P. Thomas 1 , M. Barth 1 , K. Johnson 1 , S. Kurinec 1 , A. Seabaugh 2 , Z. Cheng 3 , J. Li 3 , J. Park 3 , J. Hydrick 3 , N. Bai 3 , M. Carroll 3 , J. G. Fiorenza 3 , and A. Lochtefeld 3 1 Department of Microelectronic Engineering, Rochester Institute of Technology, Rochester, NY 14623 USA 2 Department of Electrical Engineering, University of Notre Dame, South Bend, IN 46556 USA 3 Amberwave Systems Corporation, Salem, NH 03079-4235 USA
  • 2.
      • Motivation :
        • Why use tunnel diodes?
        • Why use III-V tunnel diodes?
      • Enabling Technology : “Aspect Ratio Trapping” (ART)
        • Developed by AmberWave
      • World Record GaAs-based Esaki diodes on a Si Substrate
        • Fourth highest PVCR ever reported
        • Structures are grown entirely by CVD.
    Outline
  • 3. Tunnel Diode Characteristics and Applications V I P I V V P V V
    • Goals:
    • Demonstrate GaAs tunnel junctions on Si to enable:
    • Tunnel SRAM
    • Low-subthreshold- swing III-V tunnel transistors
    n+ p+   PVCR > 10 desired!
    • Degenerate doping
    • Abrupt junction
  • 4.
    • III-V Tunnel Diodes have larger PVCR than Si
    • Extensive literature reports of III-V Esaki diodes
    • MOCVD has been demonstrated for III-Vs
    Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si
  • 5.
    • III-V Tunnel Diodes have larger PVCR than Si
    • Extensive literature reports of III-V Esaki diodes
    • MOCVD has been demonstrated for III-Vs
    Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si High Speed Logic Memory
  • 6.
    • III-V Tunnel Diodes have larger PVCR than Si
    • Extensive literature reports of III-V Esaki diodes
    • MOCVD has been demonstrated for III-Vs
    Si Vs. III-V Tunnel Diodes Approach in this study: Integrate a III-V Esaki Diode on Si Si Esaki Diodes III-V Esaki Diodes
  • 7. Silicon Ge SiO 2 500 nm J.S. Park et al., Appl. Phys. Lett 90 052113 (2007)
    • Aspect Ratio Trapping (ART)
      • Enables heterointegration of Ge and III-V on Si
      • Traps mismatch dislocations in high aspect ratio trenches
    • Advantages of ART
      • Works on variety of materials (Ge, GaAs, InP)
      • Thin buffer layer (100-400 nm) enables integration in CMOS
      • Accommodates high lattice mismatch (up to 8% demonstrated)
      • Enables selective integration of different materials
    Aspect Ratio Trapping (ART) Defect Trapping
  • 8. Aspect Ratio Trapping (ART) H W Ge Si
    • Important Points:
        • High trench aspect ratio is the key to trapping defects
        • ART reduces defects by 3 orders of magnitude
    Aspect Ratio = H/W
  • 9.
    • Approach used for this study:
      •  Integrate a III-V device atop a coalesced Ge substrate.
        • RP-CVD for Ge
        • MOCVD for III-V Growth
    Aspect Ratio Trapping (ART)
  • 10. Coalesced Ge InGaAs/GaAs TD Strained InGaAs/top contact (Some layers are all InGaAs) Gold Contact GaAs/Ge heterointerface TEM image of Fabricated Device illustrates strained InGaAs diode layer. GaAs/InGaAs Device Concept Si Substrate Ge filled SiO 2 trenches
  • 11. 50 nm GaAs n-type (Si) >1x10 19 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥1x10 19 cm -3 80 nm GaAs p-type (C) >1x10 20 cm -3 TD1: Baseline Structure
      • T.A. Richard et. al. Appl. Phys. Lett. 63 , pp. 3613-5, (1993)
        • PVCR of 21
        • Grown on a GaAs substrate
    • Target structure based on published III-V Device (GaAs/In 0.1 Ga 0.9 As)
  • 12. Strained p-GaAs (C) Strained n-InGaAs (Si) QW, 10nm wide n-GaAs (Si)
      • TEM image confirms the excellent crystal quality and sharp interface.
      • SIMS profile of TD1 shows doping in mid-10 19 cm -3 .
    TD1: TEM image & SIMS profile
  • 13.
    • Post growth anneal removes H 2 from epi growth; Richard et. al.
      • Result: Large increase in PVCR
    • Similar trend is observed here:
      • No anneal : PVCR 2.4 - 7
      • 425 o C, 5 min, N 2 : PVCR 24
    • All devices reported use 425 o C, 5 min. N 2 anneal.
    Influence of Anneal on PVCR
  • 14.
    • Devices of ~ 3.5  m 2 show larger PVCR of 27
    • Current density is low due to doping levels.
    • KEY POINT :
    • Exceeds GaAs world record PVCR (25) reported by Holonyak, et. al.
    TD1: I-V Characteristics
  • 15. TD1: Temperature Response
    • KEY POINTS :
    • Similar response as published GaAs Esaki diodes.
    • PVCR remains greater then or equal to the room temperature PVCR of Si/SiGe TDs.
  • 16.
    • Higher current density (as high as 1 kA/cm 2 )
    • Higher PVCR: 43
    TD2: 20% In 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.2 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm GaAs p-type (C) =5x10 19 cm -3 KEY POINT : Increasing In composition elevates current density and PVCR
  • 17.
    • World Record GaAs PVCR
    • Fourth Highest reported PVCR on any material system or Tunnel diode.
    TD3: All 10% InGaAs Esaki Diode 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm In 0.1 Ga 0.9 As p-type (C) =5x10 19 cm -3 KEY POINTS : 250 A/cm 2
  • 18.
    • Key points :
    • Lower PVCR than other structures
      • Due to elimination of quantum well
    TD4: Graded 10% InGaAs Esaki Diode 50 nm GaAs n-type (Si) >9x10 18 cm -3 10 nm In 0.1 Ga 0.9 As n-type (Si) ≥9x10 18 cm -3 80 nm GaAs p-type (C) =5x10 19 cm -3 10 nm gradedGaAs to In 0.1 Ga 0.9 As n-type 65 A/cm 2
  • 19. Comparison with Devices in Literature
  • 20. Comparison with Devices in Literature
  • 21. Conclusions
      • Enabling Technology : ART
        • Developed by AmberWave
      • World Record : GaAs-based Esaki diodes
        • Fourth highest PVCR reported for any tunnel diode
        • Realized on a Si Substrate.
        • Structure are grown entirely by CVD.
        • Temperature response comparable to bulk GaAs Esaki Diodes
  • 22. RIT: R. Rafaelle, S. Hubbard, S. Polly, C. Bailey, and SMFL Staff Amberwave: M. Curtin, C. Major and the other lab staff Micron Technology: D. MacMahon (TEM imaging) Silvaco Corporation: TCAD software donation Project supported by National Science Foundation grants ECCS-0725760 and ECCS-0832653 Acknowledgements