Stuart Riley

8 Followers

ASQ Certified Six-Sigma Green Belt Quality (Yield) Engineer and Software Product Manager with over 15 years experience in semiconductor and semiconductor-related companies. Technical & management skills include Six-Sigma lean, organizational improvement, team leadership, consulting, and project management. Over 10 years experience managing projects with various teams of engineers, technicians and software developers. Over 2 years experience in Yield Management (Quality) Consulting.

defect semiconductor die klarf wafer gnuplot map fail stuart l riley fault yield inspection bit-fail caa critical area analysis

Activity
About

Stuart Riley

Presentations

How To Translate Bit Fail Correlation Data To Die Kill Ratios May2009

Semiconductor Defect Management Separating The Vital Few From The Trivial Many

How To Estimate The Number Of Die Escapes Using In Line Defect Data

How To Set Kill Ratios For Defects

Control Charts For Semiconductor Defect Management

Documents

Klarf View Users Guide

Die View Users Guide