Assic 6th Lecture

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1
Verilog HDLVerilog HDL
ASIC DESIGN USING
FPGA
BEIT VII
KICSIT
Sep 6 2012 Lecture 6

2
Hierarchical Design
Sep 6 2012 Lecture 6

3
Structural Model (Gate Level)
Sep 6 2012
• Built-in gate primitives:
•and, nand, nor, or, xor, xnor,
buf, not
•bufif0, b...

4
Structural Model (Gate Level)
Sep 6 2012
and #2 u1(out, in1, in2, in3);
3-input AND with 2 t.u. delay
not #1 N1(out, in)...

5
Example: Half Adder
Sep 6 2012
•Assuming
•XOR: 2 t.u delay
• AND: 1 t.u delay
Lecture 6

6
Example: Half Adder
Sep 6 2012
module half_adder(S, C, A, B);
output S, C;
input A, B;
wire S, C;
xor #2 u1(S, A, B);
an...

7
Continuous Assignements (Data flow)
Sep 6 2012
• Syntax:
assign #del <id> = <expr>;
• Where to write them:
• inside a mo...

8
Example: Half Adder
Sep 6 2012 Lecture 6

9
Module Ports
Sep 6 2012
• Similar to pins on a chip
• Provide a way to communicate with outside
world.
• Ports can be in...

10
Port Assignments
Sep 6 2012 Lecture 6

11
Connecting Ports to External Signals
Sep 6 2012
There are two methods of making connections
b/w signals specified in th...

12
Connecting Ports to External Signals
Sep 6 2012
Example:
module Top;
fulladder fa_ordered(SUM, C_OUT,
A, B, C_IN);
endm...

13
Connecting Ports to External Signals
Sep 6 2012
Example:
module Top;
fulladder fa_byname(.c_out (C_OUT),
.sum (SUM),
.i...

14
Example: Full Adder
Sep 6 2012 Lecture 6

15Sep 6 2012 Lecture 6
Example: Full Adder

16Sep 6 2012
module full_adder(sum, cout, in1, in2,
cin);
output sum, cout;
input in1, in2, cin;
wire sum, cout, in1, in2,...

17Sep 6 2012
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;
wire sum, cout, in1, in2,...

18Sep 6 2012 Lecture 6
2-Bit Full Adder Schematic View

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