Sivakumar P R is the Founder and Chief Executive Officer of
Maven Silicon, responsible for the company’s vision, overall
strategy and technology.
Before starting MavenSilicon, he worked as Verification
Consultant in the leading EDA companies, Synopsys, Cadence
and Mentor Graphics over the past 10 years.
He worked very closely with various ASIC and FPGA design
houses and helped them to use the EDA solutions effectively, for
the successful tape-outs of multi million gate designs.
LinkedIn Profile : http://www.linkedin.com/in/sivapr
Amitra Sudan, Component Engineer at Intel says:
*System Verilog training at Maven Silicon gave me a great opportunity to
look into modern verification concepts using System Verilog.
*Through the course I could learn to develop a robust testbench which can
generate different testcase scenarios using the concepts of Object
*Learning Assertion Based Verification was also an added advantage
which is in high demand in todays Verification job market.
"I am sure this training will not only give openings to job seekers but also
help to create great interest in Verification IP development among
Adnan Khan, Verification Engineer at i-WORKZ says:
This is what I felt while undergoing the vlsi training.
The trainer, Sivakumar is excellent.I always wanted a trainer like him to
train me in something new.
His abundant knowledge about the subject and vast industry
experience is the right mix for somebody who is responsible to impart
"I found the whole experience at Maven Silicon a pleasant one.
Hence I have no reservations in recommending this course to any of my
friends or colleagues"
Shamanth, Verification Engineer at Kasura Technologies, says:
“The Verification course at Maven Silicon was exactly what I needed while
preparing for interviews for ASIC Verification positions.
The lectures and the course material helped me learn the concepts well, while the
challenging project work offered invaluable hands-on technical experience,
which eventually helped me find a job as a Verification Engineer in the industry.
I am really glad I found Maven Silicon and took up their Verification
Abha Katiyar, Verification Engineer at TCS Says:
Maven Silicon training was really helpful to me for getting the clear idea not only
about the SV testbench design but also why it is really important in today's
market where the TTM is very critical.
As a Verification Engineer, I have architected many testbenches using verilog.
During the course, I realized that how can I utilize my time for the verification
rather than writing testbench and testcases what we do in verilog.
Moreover, I understood VMM and Assertion Based Verification which are
again very useful for verifying complex chips.
"I appreciate the efforts made by the Maven Silicon's team to make this
SystemVerilog language learning easy for us and wish a great future for Maven
Vijay Meda, Sr.Verification Engineer at KPIT says:
I am happy to be a part of SystemVerilog-Verification Methodology course in
According to me the unique features are
*Excellent teaching professionals with vast industry experience
*Well designed course content to meet the real time industry needs
*More concentration on concepts and practical implementation
*Availability of industry standard tools and environment
*Not just the project assignment to implement the concepts learnt but also the
evaluation by the faculty
*Offline help of the faculty even after finishing the course
"I personally felt that this course will pave the way to great future“