メニーコアプロセッサにおけるコア間通信レイテンシ隠蔽手法の検討 @IPSJ72

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メニーコアプロセッサにおけるコア間通信レイテンシ隠蔽手法の検討 @IPSJ72

  1. 1. u  n  n  n  n u 
  2. 2. u u u u u 
  3. 3. u  n u  n  •  n  • 
  4. 4. u  n  –  »  –  » 
  5. 5. u u  n  •  n  • 
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  7. 7. u u  n u  n  n  •  • 
  8. 8. Off chip memory modulesu  n  n u  n u  n  n  Many-core processor chip
  9. 9. u  n u  n u  n  u  n 
  10. 10. u  Core stall store signal Violation Detector Head Address 0x1000 n  load load Tail Address 0x2000 DMA Req Yes n  store store DMA status read Node Memory INCC DMA Reg PUT to (3,2) write DMA Transfer Router On Chip Network : data : control
  11. 11. u u u u u u  n u 
  12. 12. u  n  n  n  16cores 0.8 64cores 0.6 Speedup [%] 0.4 0.2 0 cg ft is lu mg Benchmark
  13. 13. u  n  •  1 16cores 64cores 0.8 Stall Rate 0.6 0.4 0.2 0 cg ft is lu mg Benchmark
  14. 14. u  n  n  n  n  n  • 
  15. 15. u u 
  16. 16. u  5.5 16cores base 5 64cores base 4.5 16cores pre-write 64cores pre-write 4 DMA rate [%] 3.5 3 2.5 2 1.5 1 0.5 cg ft is lu mg Benchmark

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