VHDL 360©<br />by: Mohamed Samy<br />        Samer El-Saadany<br />
Copyrights<br />Copyright © 2010 to authors. All rights reserved<br />All content in this presentation, including charts, ...
Course Prerequisites<br />Digital/Logic design<br />System architecture<br />Computer architecture (is a plus)<br />Softwa...
Module 0<br />Introduction to VHDL<br />
Objective<br />Overview on VHDL<br />Skills gained:<br />VHDL History and usage<br />VHDL design flow<br />Understand conc...
6<br />VHDL Standard<br />Synthesizable VHDL<br />What is VHDL?<br />VHDL is<br />A High level modeling language<br />A mo...
VHDL history <br /><ul><li>Very high speed integrated circuit Hardware Description Language</li></ul>Early 1980s: Develope...
Uses of VHDL<br />Design representation<br />using different abstraction levels<br />Design documentation<br />Design simu...
Basic Design Flow<br />9<br />DesignEntry<br />Place and Route<br />VHDL 360 ©<br />Behavioral Simulation<br />failed<br /...
Let’s have a quick look at the following model & try to understand the main sections in the code<br />--<br />LIBRARYieee;...
A closer look at the code: “Entity”<br />--<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arit...
A closer look at the code:  “Architecture”<br />ARCHITECTURErtlOF model1 IS <br />-- This is a comment<br />SIGNAL x :std_...
Concurrency<br />BEGIN<br />	 x <= a AND b;<br />	 y <= c AND d;<br />	 e <= x OR y;<br />ENDrtl;<br />VHDL 360 ©<br />Thi...
Simple Exercise:<br />Deduce the logic of the below model<br />--<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />...
Simple Exercise:<br />Deduce the logic of the below model<br />--<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />...
Basic Concepts of Digital Design<br />Please revise the following:<br /><ul><li>Logic values
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Introduction to VHDL

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Overview on VHDL
Skills gained:
1- VHDL History and usage
2- VHDL design flow
3- Understand concurrency

This is part of VHDL 360 course

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Introduction to VHDL

  1. 1. VHDL 360©<br />by: Mohamed Samy<br /> Samer El-Saadany<br />
  2. 2. Copyrights<br />Copyright © 2010 to authors. All rights reserved<br />All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.<br />Authors are not personally liable for your using of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.<br />Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. <br />Product names and trademarks mentioned in this presentation belong to their respective owners.<br />VHDL 360 ©<br />2<br />
  3. 3. Course Prerequisites<br />Digital/Logic design<br />System architecture<br />Computer architecture (is a plus)<br />Software programming (is a plus)<br />3<br />VHDL 360 ©<br />
  4. 4. Module 0<br />Introduction to VHDL<br />
  5. 5. Objective<br />Overview on VHDL<br />Skills gained:<br />VHDL History and usage<br />VHDL design flow<br />Understand concurrency<br />VHDL 360 ©<br />5<br />
  6. 6. 6<br />VHDL Standard<br />Synthesizable VHDL<br />What is VHDL?<br />VHDL is<br />A High level modeling language<br />A model that will be either used to synthesize H/W or just used as a simulation model<br />Only a subset of the language can be used for synthesis<br />VHDL 360 ©<br />
  7. 7. VHDL history <br /><ul><li>Very high speed integrated circuit Hardware Description Language</li></ul>Early 1980s: Developed by U.S. Department of Defense<br />1987: IEEE Standard 1076 - 87 <br />1993: IEEE Standard 1076 – 93 (New features)<br />1999: Analog Mixed Signal extension (VHDL-AMS)<br />2008: IEEE Std 1076 – 2008 (New features)<br />7<br />VHDL 360 ©<br />
  8. 8. Uses of VHDL<br />Design representation<br />using different abstraction levels<br />Design documentation<br />Design simulation<br />Design synthesis<br />Design verification<br />8<br />VHDL 360 ©<br />
  9. 9. Basic Design Flow<br />9<br />DesignEntry<br />Place and Route<br />VHDL 360 ©<br />Behavioral Simulation<br />failed<br />Post Place & Route Simulation<br />failed<br />Succeeded<br />Synthesis<br />Succeeded<br />Start Production<br />Post Synthesis Simulation<br />failed<br />Succeeded<br />
  10. 10. Let’s have a quick look at the following model & try to understand the main sections in the code<br />--<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY model1 IS<br />PORT( a :INstd_logic;<br /> b :INstd_logic;<br /> c :INstd_logic;<br /> d :INstd_logic;<br /> e :OUTstd_logic);<br />END model1 ;<br />ARCHITECTURErtlOF model1 IS<br />-- This is a comment<br />SIGNAL x :std_logic;<br />SIGNAL y :std_logic;<br />BEGIN<br /> -- This is another comment<br /> x <= a AND b;<br /> y <= c AND d;<br /> e <= x OR y; -- end of line comment<br />ENDrtl;<br />VHDL 360 ©<br />Libraries & Packages headers<br />Interface definition<br />(input/output ports)<br />Functional/behavioral <br />Implementation<br />10<br />
  11. 11. A closer look at the code: “Entity”<br />--<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY model1 IS<br />PORT( a :INstd_logic;<br /> b :INstd_logic;<br /> c :INstd_logic;<br /> d :INstd_logic;<br /> e :OUTstd_logic);<br />END model1 ;<br />VHDL 360 ©<br />Reusing Library components<br />Packages defining data types<br />& Functions to be used in our code<br />Defining a model with name “model1”<br />Defining the interface ports,<br /> their types &<br /> their direction<br />model1<br />11<br />
  12. 12. A closer look at the code: “Architecture”<br />ARCHITECTURErtlOF model1 IS <br />-- This is a comment<br />SIGNAL x :std_logic;<br />SIGNAL y :std_logic;<br />BEGIN<br /> -- This is another comment<br /> x <= a AND b;<br /> y <= c AND d;<br /> e <= x OR y;-- end of line comment<br />ENDrtl;<br />VHDL 360 ©<br />Comments start with --<br /> Internal declarations, for example <br /> signals used for connections<br />Comments start with --<br />Assignments relating<br /> outputs to inputs<br />12<br />
  13. 13. Concurrency<br />BEGIN<br /> x <= a AND b;<br /> y <= c AND d;<br /> e <= x OR y;<br />ENDrtl;<br />VHDL 360 ©<br />Think Hardware:<br />In real life, the value @ x is always the result of a AND b, whenever a/b changes x will change accordingly<br />Similarly the value @ y will always change whenever c/d changes<br />It might happen that the value @ x changes at the same time the value @ y changes  Both changes happen concurrently<br /> These assignment statements are concurrent,<br /> they can be written in any order<br />VHDL is concurrent by nature<br />13<br />
  14. 14. Simple Exercise:<br />Deduce the logic of the below model<br />--<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY exercise1 IS<br />PORT( a :INstd_logic;<br /> b :INstd_logic;<br /> c :OUTstd_logic;<br /> s :OUTstd_logic);<br />END exercise1 ;<br />ARCHITECTUREbehavOF exercise1 IS<br />BEGIN<br /> c <= a AND b;<br /> s <= a XOR b;<br />ENDbehav;<br />VHDL 360 ©<br />14<br />
  15. 15. Simple Exercise:<br />Deduce the logic of the below model<br />--<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />USEieee.std_logic_arith.all;<br />ENTITY exercise1 IS<br />PORT( a :INstd_logic;<br /> b :INstd_logic;<br /> c :OUTstd_logic;<br /> s :OUTstd_logic);<br />END exercise1 ;<br />ARCHITECTUREbehavOF exercise1 IS<br />BEGIN<br /> c <= a AND b;<br /> s <= a XOR b;<br />ENDbehav;<br />VHDL 360 ©<br />I got it!!<br />This is a Half adder Model<br />15<br />
  16. 16. Basic Concepts of Digital Design<br />Please revise the following:<br /><ul><li>Logic values
  17. 17. Tristate buffer
  18. 18. Level vs. Edge triggered
  19. 19. Latches vs. Flip-Flops
  20. 20. Combinational vs. Sequential logic
  21. 21. Synchronous vs. Asynchronous
  22. 22. Please revise the following (Logic gates, multiplexers, decoders, counters, adders, multipliers, shift registers, all types of flip flops)</li></ul>16<br />VHDL 360 ©<br />
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