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Introduction to VHDL

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Overview on VHDL …

Overview on VHDL
Skills gained:
1- VHDL History and usage
2- VHDL design flow
3- Understand concurrency

This is part of VHDL 360 course

Published in: Education, Technology, Design
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  • 1. VHDL 360©
    by: Mohamed Samy
    Samer El-Saadany
  • 2. Copyrights
    Copyright © 2010 to authors. All rights reserved
    All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.
    Authors are not personally liable for your using of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.
    Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact.
    Product names and trademarks mentioned in this presentation belong to their respective owners.
    VHDL 360 ©
    2
  • 3. Course Prerequisites
    Digital/Logic design
    System architecture
    Computer architecture (is a plus)
    Software programming (is a plus)
    3
    VHDL 360 ©
  • 4. Module 0
    Introduction to VHDL
  • 5. Objective
    Overview on VHDL
    Skills gained:
    VHDL History and usage
    VHDL design flow
    Understand concurrency
    VHDL 360 ©
    5
  • 6. 6
    VHDL Standard
    Synthesizable VHDL
    What is VHDL?
    VHDL is
    A High level modeling language
    A model that will be either used to synthesize H/W or just used as a simulation model
    Only a subset of the language can be used for synthesis
    VHDL 360 ©
  • 7. VHDL history
    • Very high speed integrated circuit Hardware Description Language
    Early 1980s: Developed by U.S. Department of Defense
    1987: IEEE Standard 1076 - 87
    1993: IEEE Standard 1076 – 93 (New features)
    1999: Analog Mixed Signal extension (VHDL-AMS)
    2008: IEEE Std 1076 – 2008 (New features)
    7
    VHDL 360 ©
  • 8. Uses of VHDL
    Design representation
    using different abstraction levels
    Design documentation
    Design simulation
    Design synthesis
    Design verification
    8
    VHDL 360 ©
  • 9. Basic Design Flow
    9
    DesignEntry
    Place and Route
    VHDL 360 ©
    Behavioral Simulation
    failed
    Post Place & Route Simulation
    failed
    Succeeded
    Synthesis
    Succeeded
    Start Production
    Post Synthesis Simulation
    failed
    Succeeded
  • 10. Let’s have a quick look at the following model & try to understand the main sections in the code
    --
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    USEieee.std_logic_arith.all;
    ENTITY model1 IS
    PORT( a :INstd_logic;
    b :INstd_logic;
    c :INstd_logic;
    d :INstd_logic;
    e :OUTstd_logic);
    END model1 ;
    ARCHITECTURErtlOF model1 IS
    -- This is a comment
    SIGNAL x :std_logic;
    SIGNAL y :std_logic;
    BEGIN
    -- This is another comment
    x <= a AND b;
    y <= c AND d;
    e <= x OR y; -- end of line comment
    ENDrtl;
    VHDL 360 ©
    Libraries & Packages headers
    Interface definition
    (input/output ports)
    Functional/behavioral
    Implementation
    10
  • 11. A closer look at the code: “Entity”
    --
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    USEieee.std_logic_arith.all;
    ENTITY model1 IS
    PORT( a :INstd_logic;
    b :INstd_logic;
    c :INstd_logic;
    d :INstd_logic;
    e :OUTstd_logic);
    END model1 ;
    VHDL 360 ©
    Reusing Library components
    Packages defining data types
    & Functions to be used in our code
    Defining a model with name “model1”
    Defining the interface ports,
    their types &
    their direction
    model1
    11
  • 12. A closer look at the code: “Architecture”
    ARCHITECTURErtlOF model1 IS
    -- This is a comment
    SIGNAL x :std_logic;
    SIGNAL y :std_logic;
    BEGIN
    -- This is another comment
    x <= a AND b;
    y <= c AND d;
    e <= x OR y;-- end of line comment
    ENDrtl;
    VHDL 360 ©
    Comments start with --
    Internal declarations, for example
    signals used for connections
    Comments start with --
    Assignments relating
    outputs to inputs
    12
  • 13. Concurrency
    BEGIN
    x <= a AND b;
    y <= c AND d;
    e <= x OR y;
    ENDrtl;
    VHDL 360 ©
    Think Hardware:
    In real life, the value @ x is always the result of a AND b, whenever a/b changes x will change accordingly
    Similarly the value @ y will always change whenever c/d changes
    It might happen that the value @ x changes at the same time the value @ y changes  Both changes happen concurrently
    These assignment statements are concurrent,
    they can be written in any order
    VHDL is concurrent by nature
    13
  • 14. Simple Exercise:
    Deduce the logic of the below model
    --
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    USEieee.std_logic_arith.all;
    ENTITY exercise1 IS
    PORT( a :INstd_logic;
    b :INstd_logic;
    c :OUTstd_logic;
    s :OUTstd_logic);
    END exercise1 ;
    ARCHITECTUREbehavOF exercise1 IS
    BEGIN
    c <= a AND b;
    s <= a XOR b;
    ENDbehav;
    VHDL 360 ©
    14
  • 15. Simple Exercise:
    Deduce the logic of the below model
    --
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    USEieee.std_logic_arith.all;
    ENTITY exercise1 IS
    PORT( a :INstd_logic;
    b :INstd_logic;
    c :OUTstd_logic;
    s :OUTstd_logic);
    END exercise1 ;
    ARCHITECTUREbehavOF exercise1 IS
    BEGIN
    c <= a AND b;
    s <= a XOR b;
    ENDbehav;
    VHDL 360 ©
    I got it!!
    This is a Half adder Model
    15
  • 16. Basic Concepts of Digital Design
    Please revise the following:
    • Logic values
    • 17. Tristate buffer
    • 18. Level vs. Edge triggered
    • 19. Latches vs. Flip-Flops
    • 20. Combinational vs. Sequential logic
    • 21. Synchronous vs. Asynchronous
    • 22. Please revise the following (Logic gates, multiplexers, decoders, counters, adders, multipliers, shift registers, all types of flip flops)
    16
    VHDL 360 ©

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