Reference page<br />Component Instantiation<br />There are two ways to connect ports:<br />Positional<br />The first signal in the component instantiation corresponds to the first port in the component declaration, the second signal => second port (signal2), etc<br />Use “OPEN” keyword to leave port unconnected<br /><ul><li>Named
Explicitly specify port names and the connected signal
21<br />Testbench<br />Testbench<br />Stimulus<br />generators<br />& <br />Monitors<br />Tester<br />UUT<br />UUT<br />Testbench<br />Testbenches are used to test the design in a programmatic way<br />Testbenches can apply the same set of tests on different abstraction levels of the design<br />Is my design functioning correctly?<br /><ul><li>Testbench is used to:
Generate stimulus & apply it to the entity under test
Monitors<br />Syntax:<br />One way to monitor & report outputs is using assertions<br />24<br />assert<condition>report <message> <br /> severity <level>;<br /><ul><li>An assertion statement checks that a specified condition is true and reports a message if it is not.
When the specified condition is false, the ASSERT statement triggers and the report is issued in the simulation console
The alu_tester entity will have several architectures each one tests a specific aspect in the alu
The alu_tb instantiates the alu DUT & the alu_tester</li></ul>lgc_test<br />Entities & their <br />architectures<br />Tests using <br />Configurations<br /><ul><li>Several VHDL configurations are created, each represents a test and binds a specific architecture to the alu_tester entity</li></ul>alu<br />all_test<br />behav<br />crnr_cs_test<br />alu_tb<br />crnr_cases<br />arith_test<br />struct<br />bug_fixes_test<br />alu_tester<br />rltn_test<br />relational<br />arith<br />logical<br />