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Building Hierarchy

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1- Modeling Hierarchy …

1- Modeling Hierarchy
2- Creating Testbenches
Skills gained:
1- Reuse design units several times in a design hierarchy
2- Automate testing of design units

This is part of VHDL 360 course

Published in: Education, Technology, Business

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  • 1. VHDL 360©
    by: Mohamed Samy
    Samer El-Saadany
  • 2. Copyrights
    Copyright © 2010/2011 to authors. All rights reserved
    All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.
    Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.
    Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact.
    Product names and trademarks mentioned in this presentation belong to their respective owners.
    VHDL 360 ©
    2
  • 3. Module 6
    Structural Description
  • 4. Objective
    Modeling Hierarchy
    Creating Testbenches
    Skills gained:
    Reuse design units several times in a design hierarchy
    Automate testing of design units
    VHDL 360 ©
    4
  • 5. Outline
    Generics
    Structural Description
    Testbench
    Generate Statement
    Configuration Statement
    VHDL 360 ©
    5
  • 6. How to create a generic DU?
    VHDL provides an easy way to create generic design units that can be used several times with different properties in the design hierarchy
    4-bit counter
    N-bit counter
    8-bit counter
    6
    VHDL 360 ©
  • 7. Generic Clause
    7
    VHDL 360 ©
    Syntax:
    Declared inside the entity
    The default value can be overridden at component instantiation
    If the optional default_value is missing in generic clause declaration, it must be present when the component is instantiated
    generic(
    <identifier>:type [:= default_value];
    <identifier>:type [:=default_value])
    );
    Example 1:
    LIBRARYieee;
    USEieee.NUMERIC_STD.all;-- required to use "unsigned" type
    Entitygeneric_multiplieris
    generic(N :integer:=4);
    port(A, B:inunsigned(N-1downto0);
    Z :outunsigned(2*N-1downto0));
    Endentity;
    Architecture behave ofgeneric_multiplieris
    Begin
    Z <= A * B;
    Endarchitecture;
  • 8. Exercise 1
    • Construct an N-input OR gate by doing the following:
    • 9. Declare a generic value (N) with default value = 5
    • 10. Declare an input port (A) of size N
    • 11. Use the 'range attribute to loop on the input A bits
    A1
    A2
    Z
    .
    .
    libraryIEEE;
    useIEEE.std_logic_1164.all;
    Entityor_nis
    <Here>
    port(<Here>
    Z :outstd_logic);
    Endor_n;
    Architecture behave ofor_nis
    Begin
    process(A)
    variable temp :std_logic;
    begin
    temp := '0' ;
    foriin <Here> loop
    temp := temp or A(i);
    endloop;
    Z <= temp;
    endprocess;
    End behave;
    An
    8
    VHDL 360 ©
  • 12. Exercise 1 (Soln.)
    • An N-input OR gate
    libraryIEEE;
    useIEEE.std_logic_1164.all;
    Entityor_nis
    generic(N :integer:=5);
    port(A :instd_logic_vector(N-1downto0);
    Z :outstd_logic);
    Endor_n;
    Architecture behave ofor_nis
    Begin
    process(A)
    variable temp :std_logic;
    begin
    temp := '0' ;
    foriinA'rangeloop
    temp := temp or A(i);
    endloop;
    Z <= temp;
    endprocess;
    End behave;
    A1
    A2
    Z
    An
    9
    VHDL 360 ©
  • 13. Generic Clause
    Example 2: N-input AND gate
    libraryIEEE;
    useIEEE.std_logic_1164.all;
    Entityand_nis
    generic( N :integer:=4);
    port(A :instd_logic_vector(N-1downto0);
    Z :outstd_logic);
    Endentity;
    Architecture behave ofand_nis
    Begin
    process(A)
    variable temp :std_logic;
    begin
    temp := '1' ;
    foriinA'rangeloop
    temp := temp and A(i);
    endloop;
    Z <= temp ;
    endprocess;
    Endarchitecture;
    10
    VHDL 360 ©
    Reference page
    A1
    A2
    Z
    An
  • 14. Structural Description
    VHDL 360 ©
    11
    A
    E
    B
    C
    D
    Models complex digital system through a set of components (design units) and their interconnection in a hierarchicalfashion
    Hierarchical design approach is always preferred over flat design approach because it reduces the complexity
  • 15. Structural Description
    Structural modeling involves the following:
    Component declaration
    Declaring component names and ports; can be done in the architecture declaration area or in a package
    Component instantiation and Interconnections
    Creating instances of declared components
    Connecting instances' ports to appropriate signals
    Component declaration
    12
    Syntax:
    component <component_name>
    generic(
    <generic name>:type[:=default_value]);
    port (<port_names>: <mode> <type>;
    :
    );
    end component;
    Example 3:
    Architecture arch of Alu7 is
    -- component declaration
    Component ALU
    generic (width: integer := 3);
    port(A, B,Cin:inbit;
    Result:outbit_vector(8downto0));
    endcomponent;
    Begin
    VHDL 360 ©
  • 16. Structural Modeling
    Component instantiation and Interconnects
    The instance name is the name of this particular instance
    The component name is the name of the component declared earlier using the component declaration statement
    13
    VHDL 360 ©
    Syntax:
    <instance_name>: <component_name >
    generic map(
    <generic_name> => <value>,
    …);
    port map(
    <port_name> => <sig_name>,
    …);
    Example 4:
    f1:Alugeneric map(Width => 32);
    portmap (A => in1,
    B => in2,
    Cin=> cin,
    Result => out1);
  • 17. Reference page
    Component Instantiation
    There are two ways to connect ports:
    Positional
    The first signal in the component instantiation corresponds to the first port in the component declaration, the second signal => second port (signal2), etc
    Use “OPEN” keyword to leave port unconnected
    • Named
    • 18. Explicitly specify port names and the connected signal
    • 19. Preferred as it's more readable and avoids misconnection of ports
    Use “OPEN” keyword to leave port unconnected
    14
    VHDL 360 ©
    Syntax:
    instance_name: component_name
    port map (signal1,
    signal2,…);
    Syntax:
    instance_name: component_name
    port map (port2 => signal2,
    port1=> signal1,…);
  • 20. 15
    VHDL 360 ©
    Structural Modeling
    Example 5:
    libraryIEEE;
    useIEEE.std_logic_1164.all;
    Entity top is
    port(In1:instd_logic_vector(9downto0);
    In2:instd_logic_vector(31downto0);
    In3:instd_logic_vector(4downto0);
    out1, out2, out3 :outstd_logic);
    Endentity;
    ARCHITECTUREstructOF top is
    COMPONENTand_n
    GENERIC(N :integer:=4);
    PORT(A :INstd_logic_vector(N-1downto0);
    Z :OUTstd_logic);
    ENDCOMPONENT;
    COMPONENTor_n
    GENERIC(N :integer:=5);
    PORT(A :INstd_logic_vector(N-1downto0);
    Z :OUTstd_logic);
    ENDCOMPONENT;
    BEGIN
    OR5 :or_nPORTMAP(A => In3, Z => out3);-- use the default generic value
    OR32 :or_nGENERICMAP(N =>32)PORTMAP(A => In2, Z => out2);-- overrides default generic value
    AND10:and_nGENERICMAP(N =>10)PORTMAP(A => In1, Z => out1);
    ENDarchitecture;
  • 21. 16
    VHDL 360 ©
    fulladder
    Structural Modeling
    X
    S
    Y
    C
    Z
    Example 6: 1-bit Full-Adder
    ENTITYfullAdderIS
    PORT(X, Y, Z :INbit;
    S :OUTbit;
    C :OUT bit);
    ENDfullAdder;
    ARCHITECTUREexprOFfullAdderIS
    signal temp :bit;
    BEGIN
    temp <=X XOR Y;
    S <= temp XOR Z;
    C <= (X AND Y) OR (Z AND temp);
    ENDexpr;
  • 22. 17
    VHDL 360 ©
    Structural Modeling
    z
    f1
    fulladder
    cin
    f2
    fulladder
    t
    cout
    Example 7: 2-bit Full-Adder using the 1-bit Full-Adder of Example 6
    Entity my_adder2 is
    port(a, b:inbit_vector(1downto0);
    cin:inbit;
    cout:outbit;
    z :outbit_vector(1downto0));
    Endentity;
    Architecture arch of my_adder2 is
    -- component declaration
    Componentfulladder
    port(x ,y, z:inbit;
    c, s :outbit);
    endcomponent;
    signal t:bit;
    Begin
    -- component instantiation
    f1:fulladder portmap(x => a(0), y => b(0), z => cin, c => t, s => z(0));
    f2:fulladder
    portmap(x => a(1), z => t, c => cout, s => z(1), y => b(1));
    End arch;
    X
    S
    Y
    C
    Z
    X
    S
    Y
    C
    Z
  • 23. Structural Modeling
    Example 8:
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    ENTITY gent_exp2 IS
    port(A, B, C:instd_logic;
    G:outstd_logic);
    ENDENTITY;
    ARCHITECTURE behave OF gent_exp2 IS
    componentor_n
    generic(N :integer:=5);
    port(A :instd_logic_vector(N-1downto0);
    Z :outstd_logic);
    endcomponent;
    signal temp1:std_logic;
    BEGIN
    temp1 <= A and B;
    U:or_ngenericmap(N =>2)portmap(temp1 & C, G);
    ENDARCHITECTURE;
    Expression in port map; supported only in VHDL 2008
    18
    VHDL 360 ©
  • 24. Exercise 2
    VHDL 360 ©
    19
    • Use the T-FF code shown to create a 2-bit counter
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    entityt_ffis
    port(T,clk,rst:instd_logic;
    q:outstd_logic);
    endentity;
    architecture behave oft_ffis
    signal temp:std_logic;
    begin
    process(clk,rst)
    begin
    ifrst= '1' then
    temp <= '0';
    else
    ifrising_edge(clk)then
    if T = '1' then
    temp <=not temp;
    endif;
    endif;
    endif;
    endprocess;
    q <= temp;
    endarchitecture;
  • 25. TestBench
    VHDL 360 ©
    20
  • 26. 21
    Testbench
    Testbench
    Stimulus
    generators
    &
    Monitors
    Tester
    UUT
    UUT
    Testbench
    Testbenches are used to test the design in a programmatic way
    Testbenches can apply the same set of tests on different abstraction levels of the design
    Is my design functioning correctly?
    • Testbench is used to:
    • 27. Generate stimulus & apply it to the entity under test
    • 28. Compare output responses againstexpected values
    • 29. Stimulus generators & monitors can be encapsulated in a tester block
    VHDL 360 ©
  • 30. Stimulus Generation
    We have seen in “module 3”* how to use “wait” statements to generate waveforms & counter patterns
    One other way to generate a waveform is the “after” keyword
    22
    Example 9:
    a <= '1' ,
    '0' after10 ns,
    '1' after25 ns,
    '0' after30 ns;
    • The “after” keyword can also be used to model delays*
    Example 10:
    b <= a after15 ns;
    *Module 3: Write More Complex Models
    * Delays are not synthesizable
    VHDL 360 ©
  • 31. 23
    Testbench
    Stimulus
    generators
    AND
    Stimulus Generation
    Example 11: A Simple stimulus generation example for an “AND” gate testbench
    Entityand_tbis
    -- do we need ports here?
    Endentity;
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    architecture waveform ofand_tbis
    --component declaration of the DUT
    componentAND_gate
    port(a :instd_logic;
    b :instd_logic;
    c :outstd_logic);
    endcomponent;
    -- signal declaration
    signal x, y, z :std_logic;
    Begin
    x <= '0' ,
    '1' after40 ns;
    y <= '0' ,
    '1' after20 ns,
    '0' after40 ns,
    '1' after60 ns;
    uut:AND_gatePORTMAP( a => x, b => y, c => z );
    Endarchitecture;
    VHDL 360 ©
  • 32. Monitors
    Syntax:
    One way to monitor & report outputs is using assertions
    24
    assert<condition>report <message>
    severity <level>;
    • An assertion statement checks that a specified condition is true and reports a message if it is not.
    • 33. When the specified condition is false, the ASSERT statement triggers and the report is issued in the simulation console
    • 34. severity levels
    • 35. Note -- relays information about conditions to the user
    • 36. Warning -- alerts the user to conditions that are not expected, but not fatal
    • 37. Error -- relays conditions that will cause the model to work incorrectly
    • 38. Failure -- stops the simulation
    Example 12:
    assertnot((s='1')AND(r='1'))
    report"Set and Reset are both 1"
    severity ERROR;
    VHDL 360 ©
  • 39. Testbench
    25
    Example 13: A Simple testbench example for an “AND” gate testbench
    Entityand_tbis
    Endentity;
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    architecture waveform ofand_tbis
    componentAND_gate
    port(a :instd_logic;
    b :instd_logic;
    c :outstd_logic);
    endcomponent;
    signal x, y, z :std_logic;
    Begin
    x <= '0', '1' after40 ns;
    y <= '0', '1' after20 ns,
    '0' after40 ns,
    '1' after60 ns;
    uut:AND_gatePORTMAP( a => x, b => y, c => z );
    assertnot(z = '1')
    report"Now we have completed our testing"
    severity failure; -- Monitor the occurrence of a '1' and abort
    process
    begin-- Monitor the inputs outputs relation and abort in case of failure
    waiton x, y for1 ns;
    assert(z =(x and y))
    report"Error found, The output port Z is not the ANDing of inputs a and b“
    severity failure;
    endprocess;
    Endarchitecture;
    Testbench
    Stimulus
    generators
    Monitors
    AND
    VHDL 360 ©
  • 40. Testbench
    Let’s create a testbench for the shown ALU and test all operations with all operand values
    Example 14: ALU Design Unit
    26
    VHDL 360 ©
    when X"5"=>
    result <=not('1' & a);
    when X"6"=>
    result <=('1' & a)nand('1' & b);
    when X"7"=>
    result <=('1' & a)nor('1' & b);
    when X"8"=>
    result <=('1' & a)xnor('0' & b);
    when X"9"=>
    if(a > b)then
    result(8)<= '1';
    result(7downto0)<=(others=> 'Z');
    else
    result(8)<= '0';
    result(7downto0)<=(others=> 'Z');
    endif;
    when X"A"=>
    if(a < b)then
    result(8)<= '1';
    result(7downto0)<=(others=> 'Z');
    else
    result(8)<= '0';
    result (7downto0)<=(others=> 'Z');
    endif;
    when X"B"=>
    if(a >= b)then
    result(8)<= '1';
    result(7downto0)<=(others=> 'Z');
    else
    result(8)<= '0';
    result(7downto0)<=(others=> 'Z');
    endif;
    ...
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    USEieee.std_logic_unsigned.all;
    ENTITYaluIS
    port(cin:instd_logic;
    sel:instd_logic_vector(3downto0);
    a, b :instd_logic_vector(7downto0);
    cout:outstd_logic;
    y :outstd_logic_vector(7downto0));
    ENDENTITYalu;
    ARCHITECTUREbehavOFaluIS
    signal result :std_logic_vector(8downto0);
    BEGIN
    y <= result (7downto0);
    cout<= result (8);
    process(cin,sel, a, b)
    begin
    case(sel)is
    when X"0"=>
    result <=('0' & a)+('0' & b)+cin;
    when X"1"=>
    result <=('0' & a)-('0' & b)-cin;
    when X"2"=>
    result <=('0' & a)and('0' & b);
    when X"3"=>
    result <=('0' & a)or('0' & b);
    when X"4"=>
    result <=('0' & a)xor('0' & b);
  • 41. Testbench
    27
    VHDL 360 ©
    when X"C"=>
    if(a <= b)then
    result(8)<= '1';
    result(7downto0)<=(others=> 'Z');
    else
    result(8)<= '0';
    result(7downto0)<=(others=> 'Z');
    endif;
    when X"D"=>
    if(a = b)then
    result(8)<= '1';
    result(7downto0)<=(others=> 'Z');
    else
    result(8)<= '0';
    result(7downto0)<=(others=> 'Z');
    endif;
    --when X"E" =>--;
    --when X"F" =>--;
    whenothers=>
    result <=(others=> 'Z');
    endcase;
    endprocess;
    ENDARCHITECTUREbehav;
  • 42. Testbench
    Example 14: ALU Testbench
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    ENTITYalu_tbIS
    ENDalu_tb;
    ARCHITECTUREstructOFalu_tbIS
    SIGNALcin:std_logic;
    SIGNALsel:std_logic_vector(3downto0);
    SIGNAL a :std_logic_vector(7downto0);
    SIGNAL b :std_logic_vector(7downto0);
    SIGNALcout:std_logic;
    SIGNAL y :std_logic_vector(7downto0);
    COMPONENTalu
    PORT(cin:INstd_logic;
    sel:INstd_logic_vector(3downto0);
    a :INstd_logic_vector(7downto0);
    b :INstd_logic_vector(7downto0);
    cout:OUTstd_logic;
    y :OUTstd_logic_vector(7downto0));
    ENDCOMPONENT;
    COMPONENTalu_tester
    PORT(cin:OUTstd_logic;
    sel:OUTstd_logic_vector(3downto0);
    a :OUTstd_logic_vector(7downto0);
    b :OUTstd_logic_vector(7downto0);
    cout:INstd_logic;
    y :INstd_logic_vector(7downto0));
    ENDCOMPONENT;

    Testbench
    BEGIN
    UUT :alu
    PORTMAP(cin=>cin,
    sel=>sel,
    a => a,
    b => b,
    cout=>cout,
    y => y );
    Tester :alu_tester
    PORTMAP(cin=>cin,
    sel=>sel,
    a => a,
    b => b,
    cout=>cout,
    y => y );
    ENDstruct;
    28
    VHDL 360 ©
  • 43. Testbench
    Example 14: ALU Tester
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    USEieee.std_logic_arith.all;
    USEieee.std_logic_unsigned.all;
    ENTITYalu_testerIS
    PORT(cin:OUTstd_logic;
    sel:OUTstd_logic_vector(3downto0);
    a :OUTstd_logic_vector(7downto0);
    b :OUTstd_logic_vector(7downto0);
    cout:INstd_logic;
    y :INstd_logic_vector(7downto0));
    ENDalu_tester;
    ARCHITECTUREall_testerOFalu_testerIS
    signal temp :std_logic_vector(20downto0):=(others=> '0');
    BEGIN
    -- generate the stimulus
    temp <= temp +1after20 ns;
    -- drive the duti/p signals
    cin<= temp(0);
    b <= temp(8downto1);
    a <= temp(16downto9);
    sel<= temp(20downto17);
    -- now start monitoring whenever the stimulus changes
    process
    begin
    waitfor2 ns;
    case(temp(20downto17))is
    when X"0"=>
    assert((cout& y)=
    conv_std_logic_vector((conv_integer(temp(16downto9)) +
    conv_integer(temp(8downto1))+
    conv_integer(temp(0))),9))
    report"Addition failed!!"severity failure;
    when X"1"=>
    assert((cout& y)=
    conv_std_logic_vector((conv_integer(temp(16downto9)) -
    conv_integer(temp(8downto1)) -
    conv_integer(temp(0))),9))
    report"Subtraction failed!!"severity failure;

    when X"2"=>
    assert(cout= '0' and
    y =(temp(16downto9)and temp(8downto1)))
    report"AND operation failed!!"severity failure;
    when X"3"=>
    assert(cout= '0' and
    y =(temp(16downto9)or temp(8downto1)))
    report"OR operation failed!!"severity failure;
    when X"4"=>
    assert(cout= '0' and
    y =(temp(16downto9)xor temp(8downto1)))
    report"XOR operation failed!!"severity failure;
    when X"5"=>
    assert(cout= '0' and
    y =not(temp(16downto9)))
    report"NOT operation failed!!"severity failure;
    when X"6"=>
    assert(cout= '0' and
    y =(temp(16downto9)nand temp(8downto1)))
    report"NAND operation failed!!"severity failure;
    when X"7"=>
    assert(cout= '0' and
    y =(temp(16downto9)nor temp(8downto1)))
    report"NOR operation failed!!"severity failure;
    when X"8"=>
    assert(cout= '0' and
    y =(temp(16downto9)xnor temp(8downto1)))
    report"XNOR operation failed!!"severity failure;
    when X"9"=>
    assert(y ="ZZZZZZZZ")
    report"Output y should be equal to Z"
    severity failure;
    if(temp(16downto9)> temp(8downto1))then
    assert(cout= '1')
    report"Relational operation greater than failed!!"
    severity failure;

    29
    VHDL 360 ©
  • 44. Testbench
    else
    assert(cout= '0')
    report"Relational operation greater than failed"
    severity failure;
    endif;
    when X"A"=>
    assert(y ="ZZZZZZZZ")
    report"Output y should be equal to Z"
    severity failure;
    if(temp(16downto9)< temp(8downto1))then
    assert(cout= '1')
    report"Relational operation less than failed!!"
    severity failure;
    else
    assert(cout= '0')
    report"Relational operation less than failed"
    severity failure;
    endif;
    when X"B"=>
    assert(y ="ZZZZZZZZ")
    report"Output y should be equal to Z"
    severity failure;
    if(temp(16downto9)>= temp(8downto1))then
    assert(cout= '1')
    report"Relational operation greater than or equal
    failed!!"
    severity failure;
    else
    assert(cout= '0')
    report"Relational operation greater than or equal
    failed"
    severity failure;
    endif;

    when X"C"=>
    assert(y ="ZZZZZZZZ")
    report"Output y should be equal to Z"
    severity failure;
    if(temp(16downto9)<= temp(8downto1))then
    assert(cout= '1')
    report"Relational operation less than or equal
    failed!!"
    severity failure;
    else
    assert(cout= '0')
    report"Relational operation less than or equal
    failed"
    severity failure;
    endif;
    when X"D"=>
    assert(y ="ZZZZZZZZ")
    report"Output y should be equal to Z"
    severity failure;
    if(temp(16downto9)= temp(8downto1))then
    assert(cout= '1')
    report"Relational operation equal failed!!"
    severity failure;
    else
    assert(cout= '0')
    report"Relational operation equal failed"
    severity failure;
    endif;
    --when X"E" =>-- when X"F" =>
    whenothers=>
    assert((cout& y)="ZZZZZZZZZ");
    endcase;
    waiton temp;
    endprocess;
    -- Stop the simulation when temp is all 1s
    assert(temp /=('1' & X"FFFFF"))
    report"Simulation ended!!"severity failure;
    ENDARCHITECTUREall_tester;
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    VHDL 360 ©
  • 45. Generate statement
    VHDL 360 ©
    31
  • 46. Generate Statement
    • A concurrent statement used for iterative or conditional logic inference
    For-generate (Iterative mode)
    <Label> mandatory to identify the generate statement
    <Range> loop range
    If-generate (Conditional mode)
    <Label> mandatory to identify the generate statement
    <condition> Boolean expression that evaluates to either TRUE or FALSE
    "elsif" and "else" branches were added in VHDL 2008*
    Case-generate* (Conditional mode)
    <Label> mandatory to identify the generate statement
    <choice> constants representing one of possible <expression> values
    Syntax:
    <Label>: for n in<range> generate
    -- list of concurrent statements
    end generate<Label>;
    Syntax:
    <Label>: if <condition> generate
    -- list of concurrent statements
    elsif<condition> generate
    -- list of concurrent statements
    else generate
    -- list of concurrent statements
    end generate<Label>;
    Syntax:
    <Label>: case <expression> generate
    when choice => concurrent statements
    when choice => concurrent statements
    end generate<Label>;
    *VHDL 2008 is not yet supported by all tools in the market
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    VHDL 360 ©
  • 47. Generate Statement
    Example 15: for-generate
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    ENTITY gent_exp1 IS
    port(A, B, C:instd_logic_vector(3downto0);
    G:outstd_logic_vector(3downto0));
    ENDENTITY;
    ARCHITECTURE behave OF gent_exp1 IS
    componentor_n
    generic(N :integer:=5);
    port(A :instd_logic_vector(N-1downto0);
    Z :outstd_logic);
    endcomponent;
    signal temp1:std_logic_vector(3downto0);
    typemyTypeisarray(3downto0)ofstd_logic_vector(1downto0);
    signal temp2:myType;
    BEGIN
    ex1:for j in0to3generate
    temp1(j)<= A(j)and B(j);
    temp2(j)<= temp1(j)& C(j);
    U:or_ngenericmap(N =>2)portmap(temp2(j), G(j));
    endgenerate ex1;
    ENDARCHITECTURE;
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    VHDL 360 ©
  • 48. Generate Statement
    Example 16:
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    ENTITY gent_exp3 IS
    port(A, B:instd_logic_vector(3downto0);
    G:outstd_logic_vector(3downto0));
    ENDENTITY;
    ARCHITECTURE behave OF gent_exp3 IS
    BEGIN
    L1:for j in0to3generate
    L2:if j =2generate
    G(j)<= A(j)xor B(j);
    endgenerate L2;
    L3:if j /=2generate
    G(j)<= A(j)nor B(j);
    endgenerate L3;
    endgenerate L1;
    ENDARCHITECTURE;
    34
    VHDL 360 ©
  • 49. Generate Statement
    Example 17:
    LIBRARYieee;
    USEieee.std_logic_1164.all;
    ENTITY gent_exp4 IS
    port(A, B:instd_logic_vector(3downto0);
    G:outstd_logic_vector(3downto0));
    ENDENTITY;
    ARCHITECTURE behave OF gent_exp4 IS
    BEGIN
    ex1:for j in0to3generate
    L1:case j generate
    when0|2=>-- if j = 0 or j = 2
    G(j)<= A(j)and B(j);
    whenothers=>
    G(j)<= A(j)nand B(j);
    endgenerate L1;
    endgenerate ex1;
    ENDARCHITECTURE;
    VHDL 2008 is not yet supported by all tools in the market
    35
    VHDL 360 ©
  • 50. Exercise 3
    Create the n-bit shift register shown below

  • 51. VHDL Configurations
    VHDL 360 ©
    37
  • 52. Configurations
    Why do we need Configurations?
    VHDL design units are organized in libraries. Units in different libraries can have the same name but with different implementation. Designers can specify which one is needed via configurations
    VHDL allows designers to have the component name to be different than the entity name. Designers need a configuration to specify the bindings
    38
    Lib1
    Lib2
    Lib3
    Which ALU should I use?
    How to bind it in my design?
    ALU
    CPU
    ALU
    arch
    struct
    sim
    syn
    arch
    cntrlr
    cache
    Mem
    fsm
    model
    behave
    du12
    ALU
    cntrlr
    behav
    rtl
    sim
    gte
    fastsim
    rtl
    sim
    synth
    VHDL 360 ©
  • 53. Configurations
    VHDL offers different ways to specify bindings
    39
    • Configuration Specification Statement
    • 54. Defined in the declarative region of the block in which the component instance is created
    • 55. <lib> library name where the entity resides
    • 56. <ent> entity name to be used
    • 57. <arch> architecture to be used for <ent>
    • 58. <config> configuration design unit
    Syntax:
    for <inst_name | all | others> :<comp_name>
    use entity <lib>.<ent> (<arch>)
    [generic_map_aspect]
    [port_map_aspect] ;
    end for;
    for <inst_name | all | others> :<comp_name>
    use configuration <lib>.<config>;
    end for;
    • Configuration Design Unit
    • 59. Useful when the binding of component instances needs to be deferred to later time
    Syntax:
    configuration <config_name> of <entity_name> is
    for <arch_name>
    [configuration_spec_statement] ;

    end for;
    end configuration;
    VHDL 360 ©
  • 60. 40
    VHDL 360 ©
    Configurations
    Example 18: Using Configuration Specification statement
    ENTITYfullAdderIS
    PORT(X,Y,Z:INbit;
    S:OUTbit;
    C:OUTbit);
    ENDfullAdder;
    ARCHITECTUREexprOFfullAdderIS
    signal temp :bit;
    BEGIN
    temp <= X XOR Y;
    S <= temp XOR Z;
    C <=(X AND Y)OR(Z AND temp);
    ENDexpr;
    Entity adder2 is
    port(a,b:inbit_vector(1downto0);
    cin:inbit;
    cout:outbit;
    z:outbit_vector(1downto0));
    Endentity;
    Architecture arch of adder2 is
    signalt:bit;
    Componentfa
    port(a,b,c:inbit;
    d,e:outbit);
    endcomponent;
    forall:fauseentitywork.fulladder(expr)
    portmap(X=>a,Y=>b,Z=>c,S=>d,C=>e);
    Begin
    f1:faportmap(a => a(0), b => b(0), c => cin, d => t, e => z(0));
    f2:faportmap(a(1), b(1), t, z(1), cout);
    End arch;
    library* name where the design unit resides
    *more on libraries in the next modules
  • 61. configurationadder_configof my_add3 is
    for arch
    -- Binding f1 to entity fulladder
    for f1 :fa
    useentitywork.fulladder(expr);
    endfor;
    -- Binding f2 to another entity cla_fad
    forf2:fa
    useentitywork.cla_fadd(behave);
    endfor;
    -- for other instances of fa use another architecture of fulladder
    forothers:fa
    useentitywork.fulladder(expr2);
    endfor;
    endfor;
    endconfiguration;
    41
    VHDL 360 ©
    Configurations
    Example 19: Using Configuration Design Unit
  • 62. 42
    VHDL 360 ©
    Configurations
    • Example 20: In a design house, they need to create a test suite for the ALU; the purpose was to reduce the run time & to test specific aspects in the ALU rather than the whole operation. To make it generic & minimize the coding they use configurations to bind different architectures to the same tester unit as shown below
    • 63. The alu_tester entity will have several architectures each one tests a specific aspect in the alu
    • 64. The alu_tb instantiates the alu DUT & the alu_tester
    lgc_test
    Entities & their
    architectures
    Tests using
    Configurations
    • Several VHDL configurations are created, each represents a test and binds a specific architecture to the alu_tester entity
    alu
    all_test
    behav
    crnr_cs_test
    alu_tb
    crnr_cases
    arith_test
    struct
    bug_fixes_test
    alu_tester
    rltn_test
    relational
    arith
    logical
  • 65. 43
    VHDL 360 ©
    Configurations
    Example 20 (cont.):
    Test1 : Testing arithmetic Operations
    configurationarith_testofalu_tbis
    forstruct
    forall:alu
    useentitywork.alu(behav);
    endfor;
    forall:alu_tester
    useentitywork.alu_tester(arith);
    endfor;end
    for;
    endconfigurationarith_test;
    Test 3 : Testing Relational Operations
    Test 2 : Testing Logical Operations
    configurationrltn_testofalu_tbis
    forstruct
    forall:alu
    useentitywork.alu(behav);
    endfor;
    forall:alu_tester
    useentitywork.alu_tester(relational);
    endfor;end
    for;
    endconfigurationrltn_test;
    configurationlgc_testofalu_tbis
    forstruct
    forall:alu
    useentitywork.alu(behav);
    endfor;
    forall:alu_tester
    useentitywork.alu_tester(logical);
    endfor;end
    for;
    endconfigurationlgc_test;
  • 66. Contacts
    You can contact us at:
    http://www.embedded-tips.blogspot.com/
    VHDL 360 ©
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