Keynote Speech - Low Power Seminar, Jain College, October 5th 2012
LOW POWER – YESTERDAY, TODAYAND TOMORROW“Learn from yesterday, live for today, hope for tomorrow” -Albert Einstein Shivoo Koteshwar - firstname.lastname@example.org
Motivation for Low Power Portability: Battery life, Increased functionality and Heat generation Huge server farms Environmental awareness Our world is mobile and connected!
What do we need? Energy efficient infrastructure To deliver more functionality in the same footprint Gains from process migration diminishing, what can be done as the demand for performance continues to increase?
YESTERDAY TECHNIQUES CHALLENGESArchitectural exploration - system Power estimation tools are not accuratepartitioning, pipelining, redundancy andperformance-critical blocksMultiple power domains Verification Issue – Asynchronous interfacesFrequency and voltage scaling Electrical issuesClock gating Equivalence checkingPower gating State retention and recovery plus electrical issues plus extra mode of operation in simulation & Non-determinism to model power-on state increases coverage space
YESTERDAY1996 Clock Gating (Macro Level)1997 Low-Power Libraries1999 Frequency Scaling1999 Clock Gating (Micro Level)2004 Body Biasing2006 Power Islands2007 Voltage Scaling
TODAY Power must be considered at every step – From applications to Transistors , every element is critical Process technology, library and physical IP selection Power efficient RTL IP SOC architecture and designed balanced for power and performance Best in class hardware system components (Memory, PMIC, Display) OS power management strategies Power optimized software applications Designers and tools encounter almost 20 clock domains and 10 voltage domains! Architectural and implementation techniques yield biggest gains (Almost 67%)
TODAY Apart from traditional approach we employ newer methods: DVFS, Lower VDD, MTCMOS, Architecture for Low Power, Hardware Accelerators and RTL Power Optimization A standard language for describing power design: power domains, power modes, power lines / switches / fences / retention registers, voltages … CPF – Common Power Format Developed as a standard by the Si2 organization Donated by Cadence UPF – Unified Power Format Approved as a standard by Accellera, now IEEE 1801 Based on donations by Synopsys & Mentor Graphics
TODAY – Mobile Challenge Media hub for all content Contextually aware Laptop performance for any screen Seamless LTE (4G) connection to cloud apps and content Wireless connect to any screen Continuously connected updating your digital life Augmented reality Mobile security for payments and digital identity
TODAY – Mobile Workload 90min voice calling 60min email 30min reading web 30min watching HW-accelerated video 50min angry birds or other games 90min jogging while listening to music and logging GPS coordinates 10min video recording 7hrs sleep with music alarm clock with 3 snooze atleast OS typically executing ~28 active processes Apps synchronizing in backgroundSource: ARM
TODAY – Mobile Use Analysis ARM’s big-LITTLE approach where Cortex A7 isSource: ARM focusing on energy efficiency and Cortex A15 is focusing on performance
TOMORROW: Emerging Technologies,A Prediction 2018 – 2019: Self-driving cars let human drivers relax behind the wheel 2019 – 2020: 5G connectivity becomes the norm, replacing 4G; traveling into space becomes a leisure activity; eyewear comes equipped with tiny displays that project into the wearers retina 2026: Humans hand off household chores to domestic robots 2030: Displays can be embedded into human skin and powered by the blood 2034: Manned missions to Mars begin 2036 - 2037: Materials are transported from the surface of the earth into space using an elevator-like structure 2037 - 2038: Anti-aging drugs make us all look young and lovely forever Source: http://www.huffingtonpost.com/2012/07/31/envisioning- emerging-technology-for-2012-and-beyond_n_1723096.html
TOMORROW Improvements in SoC power consumption – PredictionsSource: Cadence 360http://eda360insider.wordpress.com/2012/04/11/want-to-see-the-future-of-low-power-soc-design-have-a-look-into-gary-smiths-crystal-ball/
TOMORROW 3D transistor technology: FinFETs or Tri-Gate Transistors According to Intel, 22nm Tri-Gate transistors provide a 37% performance increase at low voltage compared to 32nm planar transistors, and use 50% less power at the same performance as 32nm planar transistors. Added wafer cost is only 2-3%. Challenge: Manufacturing is not expected to be a big hurdle, and digital designers will see relatively little change. On the custom/ analog side, however, transistor-level extraction must comprehend the 3D structures, SPICE models will have added parameters, and a new layout methodology will be needed to improve designer productivity FinFETs will require an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes.
Koomey’s Law Moore’s Law: The density of components in each chip had doubled two years or Personal- computer performance doubles every 18 months Jonathan Koomey of Stanford University found that the electrical efficiency of computing has doubled every 1.6 years since the mid-1940s “That means that for a fixed amount of computational power, the need for battery capacity will fall by half every 1.6 years,” This trend, he says, “bodes well for the continued explosive growth in mobile computing, sensors and controls.” Some researchers are already building devices that run on “ambient” energy harvested from light, heat, vibration or TV transmitters