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4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
4Sem-HDL Programming Notes-Unit8-Synthesis
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4Sem-HDL Programming Notes-Unit8-Synthesis

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4Sem-HDL Programming Notes-Unit8-Synthesis

4Sem-HDL Programming Notes-Unit8-Synthesis

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  • 1.                                                                      P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )  Shivoo  Koteshwar  Professor,  E&C  Department,  PESIT  SC      Synthesis  Basics  • Synthesis  Basics:  Highlights  of  Synthesis  • Synthesis  information  from  Entity  and  Module  • Mapping  Process  and  Always  in  the  Hardware  Domain.    Reference  Books:  • HDL  Programming  (VHDL  and  Verilog)-­‐  Nazeih  M.Botros-­‐  John  Weily  India  Pvt.  Ltd.  2008.    UNIT  8:    Synthesis  Basics:  Synthesis  Basics:  Highlights  of  Synthesis,  Synthesis  information  from  Entity  and  Module,  Mapping  Process  and  Always  in  the  Hardware  Domain                                                            6  Hours      EVEN  SEMESTER   13  HDL  DESIGN-­‐4-­‐CLASS  NOTES  –  UNIT8  
  • 2. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  2  Synthesis:  Synthesis is a process of converting HDL written in RTL format usingeither Verilog or VHDL to optimized mapped gate level netlist.• The RTL is optimized based on the constraints given – Timing, Area,Power etc• The netlist is mapped to the target library specified by userSynthesis is a 3-step process: Translation, Optimization and MappingTranslation: Conversion of RTL to Generic Boolean (GTECH equation).• Here while translating, it also does HDL Syntax/Rule checkingMapping: Mapping the netlist to target technology/library/standard cells.Here the tool maps Boolean functions to technology specific primitivefunctions. The mapping is done at 3 levels1. Arithmetic function mapping2. Sequential function mapping3. Combinational function mappingOptimization: Boolean optimization is done based on the constraintsspecified (Area, Power, Timing etc). Some examples1. Tree delay Minimization (Timing focused): Tree Height Minimizationis an algorithm that is used during Timing Based high-leveloptimization. It restructures resources based on the timingconstraints. In the example below, tool would choose theimplementation on the right if D were the late arriving signal. If all 4inputs had the same arrival time, DC would choose theimplementation on the left.
  • 3. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  3  2. Resource Sharing (Area focused)3. Optimization to replace set of components by a complex gateNOTE:• Ultimate goal for HDL is to synthesize the system onto an electronicchip• Before synthesis, we need to simulate and test it. For testing, after wehave written the logical code (RTL for the design), we need to write atestbench to give inputs and trigger the block so that we can monitorthe output either in text format or in a waveform format
  • 4. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  4  Synthesis Information from Entity and ModuleFrom entity/module, tool extracts four unique properties:1. Name of the block (Functional unit)2. The port list and whether they are input, output or inout3. The bit size of the each of the pins4. Possible values each of these pins can takeExample:
  • 5. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  5  Example2:
  • 6. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  6  Mapping the signal assignment statement (y=x)
  • 7. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  7  Mapping the signal assignment statement (y=2x+3)
  • 8. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  8  
  • 9. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  9  Mapping the variable assignment statement• Verilog/VHDL does not distinguish between signal and variableassignment statements• Example:• The hardware domain is not capable of mapping the variabledeclaration and cannot distinguish between signal and variable• We notice that signal C takes the value of variable c1, so in hardwaredomain, c1 and C are one signal
  • 10. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  10  Mapping the “if” statement (example1)Mapping the “if” statement (example2)
  • 11. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  11  Mapping the “if” statement (example3)
  • 12. HDL  Design  (4th  Semester)                                                                                                                            UNIT  8  Notes  v1.0      Shivoo  Koteshwar’s  Notes                                                                                                                                        shivoo@pes.edu  12  Mapping the “if” statement (example4 –incomplete “if”)

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