3Sem-Logic Design Notes-Unit8-Sequential Design

2,202 views

Published on

VTU 3rd Semester E&C Department, Logic Design Unit 8 Detailed Notes

Published in: Education
2 Comments
3 Likes
Statistics
Notes
No Downloads
Views
Total views
2,202
On SlideShare
0
From Embeds
0
Number of Embeds
8
Actions
Shares
0
Downloads
0
Comments
2
Likes
3
Embeds 0
No embeds

No notes for slide

3Sem-Logic Design Notes-Unit8-Sequential Design

  1. 1. 12       ODD     SEMESTER                                  LOGIC  DESIGN-­‐3-­‐CLASS  NOTES  –  UNIT8            Shivoo  Koteshwar  Professor,  E&C  Department,  PESIT  SC      Sequential  Design  2   • Construction  of  State  Diagrams  -­‐  Up-­‐Down  Decade  Counter,  Sequence  Detectors,   Serial  EX-­‐3  to  BCD  Code  Converter   • Counter  Design  -­‐  Modulo  8  Synchronous  Counter,  Up  Down  Decade  Counter      Reference  Books:   • Digital  Logic  Applications  and  Design”,  John  M  Yarbrough,  Thomson  Learning,  2001   • “Logic  and  computer  design  Fundamentals”,  Mono  and  Kim,  Pearson,  Second   edition,  2001    Unit  8:    Sequential  Design  -­‐  II:    Construction  of  state  Diagrams,  Counter  Design  [(Text  book  1)  6.4,  6.5]                                                                                                                                                                                                                                                                                                                                                                                                                      6  Hours          P e o p l e s   E d u c a t i o n   S o c i e t y   S o u t h   C a m p u s   ( w w w . p e s . e d u )  
  2. 2. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0    Sequence Detector:When we design sequence detectors, the most important design aspect iswhether the detector is overlapping or non-overlapping. By default wealways assume it’s overlapping.In the overlapping sequence detector, previous bits of already detectedsequence can be a part of the new sequence.TIP:When you are checking where the arc should go while drawing the statediagrams, follow these 5 rules: 1. Look at the previous bit and present bit only 2. See if this combination of 2 bits is a part of the sequence (First 2 bits of the sequence from left). If yes, terminate the arc at this third bubble 3. If the combination of 2 bits is not a part of the sequence, check for the present bit and see if it’s a part of the sequence (First bit of the sequence from left). If yes, terminate the arc at the second bubble 4. If its not meeting these two conditions, then the arc will terminate at the first bubble 5. Usually any arc from any bubble will go to either the first bubble, second or third unless we have a sequence of 1s or 0s to be detected   Shivoo  Koteshwar’s  Notes                                          2                                                                                          shivoo@pes.edu        
  3. 3. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     Sequence Detector Design 1Question: Design a circuit that detects a sequence of three or moreconsecutive 1s in a string of bits coming through an input line using aMoore and Mealy modelSolution: Reading the requirement, we can rewrite the specification in asimpler way as below: • Sequence: 111 • Overlapping (By default always assume its overlapping) • Moore and Mealy • Assumption: Input data sequence is coming from the left MEALYSTEP1:For a Mealy circuit, if the sequence length is “n”, write “n” bubbles (states).Here the sequence is 111 so the sequence length is 3 so write 3 bubblesSTEP2:Fill the sequence-detected stateSTEP3:Fill the remaining input combinations • At A, when you get a 0, 0 is not a part of the sequence so it stays at A • At B, when you get a 0, 10 is not a part of the sequence and 0 is also not a part of a sequence so it goes back to A • At C, when you get a 0, 10 is not a part of the sequence and 0 is also not a part of a sequence so it goes back to A • At C, when you get a 1, output is 1 as it has detected the sequence 111. It stays at C as the previous state and present state is 11 which is a part of the next sequence   Shivoo  Koteshwar’s  Notes                                          3                                                                                          shivoo@pes.edu        
  4. 4. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0    Write the State Table:Lets implement with D-Flip-Flop. Encode the states and re-write the StateTable. DaDb will be same as NS in D Flip-Flop implementation   Shivoo  Koteshwar’s  Notes                                          4                                                                                          shivoo@pes.edu        
  5. 5. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     MOORESTEP1:For a Moore circuit, if the sequence length is “n”, write “n+1” bubbles(states). Here the sequence is 111 so the sequence length is 3 so write 4bubblesSTEP2:Fill the sequence-detected stateSTEP3:Fill the remaining input combinations   Shivoo  Koteshwar’s  Notes                                          5                                                                                          shivoo@pes.edu        
  6. 6. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     • At A, when you get a 0, 0 is not a part of the sequence so it stays at A • At B, when you get a 0, 10 is not a part of the sequence and 0 is also not a part of a sequence so it goes back to A • At C, when you get a 0, 10 is not a part of the sequence and 0 is also not a part of a sequence so it goes back to A • At D, when you get a 0, 10 is not a part of the sequence and 0 is also not a part of a sequence so it goes back to A • At D, when you get a 1, the next sequence is already detected as previously it had 11 so the output should be 1 which means it should stay at D (Where the output is always 1)Write the State Table:Lets implement with D-Flip-Flop. Encode the states and re-write the StateTable. DaDb will be same as NS in D Flip-Flop implementation   Shivoo  Koteshwar’s  Notes                                          6                                                                                          shivoo@pes.edu        
  7. 7. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0       Shivoo  Koteshwar’s  Notes                                          7                                                                                          shivoo@pes.edu        
  8. 8. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     Sequence Detector Design 2Question:  The network will examine a string of 0’s and 1’s applied to the Xinput and generate an output Z=1 only when a prescribed input sequenceoccurs. It will be assumed that the input X can only change between clockpulses. Design a network so that any input sequence ending with 101 willproduce an output Z=1Solution: Reading the requirement, we can rewrite the specification in asimpler way as below: • Sequence is 101 • Sequential Design • Overlapping • Mealy and Moore • Assumption: Input data sequence is coming from the left MEALYSTEP1:For a Mealy circuit, if the sequence length is “n”, write “n” bubbles (states).Here the sequence is 101 so the sequence length is 3 so write 3 bubblesSTEP2:Fill the sequence-detected stateSTEP3:Fill the remaining input combinations 1. At A, when you get a 0, 0 is not a part of the sequence so it stays at A 2. At B, when you get a 1, 11 is not a part of the sequence but 1 is a part of the sequence and it’s the first bit of the sequence, so it will stay at B 3. At C, when you get a 1, the sequence is detected so the output goes to 1. 01 is not a part of the sequence but 1 is a part of the sequence and it’s the first bit of the sequence, so it will go at B   Shivoo  Koteshwar’s  Notes                                          8                                                                                          shivoo@pes.edu        
  9. 9. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     4. At C, when you get a 0, 00 is not a part of the sequence and 0 is also not a part of the sequence so it goes to A   Shivoo  Koteshwar’s  Notes                                          9                                                                                          shivoo@pes.edu        
  10. 10. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     MOORESTEP1:For a Moore circuit, if the sequence length is “n”, write “n+1” bubbles(states). Here the sequence is 101 so the sequence length is 3 so write 4bubblesSTEP2:Fill the sequence-detected stateSTEP3:Fill the remaining input combinations 1. At A, when you get a 0, 0 is not a part of the sequence so it stays at A 2. At B, when you get a 1, 11 is not a part of the sequence but 1 is a part of the sequence and it’s the first bit of the sequence, so it will stay at B 3. At C, when you get a 0, 00 is not a part of the sequence and 0 is also not a part of the sequence so it goes to A 4. At D, when you get a 0, 10 is a part of the sequence and it is 2 bits of the sequence so it goes to C 5. At D, when you get a 1, 11 is not a part of the sequence but 1 is a part of the sequence and it’s the first bit of the sequence, so it will go to B   Shivoo  Koteshwar’s  Notes                                          10                                                                                    shivoo@pes.edu              
  11. 11. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     Sequence Detector Design 3Question: Construct a Mealy state diagram that will detect input sequenceof 10110. The detection of the required bit pattern can occur in a longerdata string and the correct pattern can overlap with another pattern. Whenthe input patterns has been detected, cause an output z to be asserted highSolution: Reading the requirement, we can rewrite the specification in asimpler way as below: • Mealy state diagram • Sequence: 10110 • Overlapping • Output z when sequence is detected • Assumption: Input data sequence is coming from the left MEALYSTEP1:For a Mealy circuit, if the sequence length is “n”, write “n” bubbles (states).Here the sequence is 10110 so the sequence length is 5 so write 5 bubblesSTEP2:Fill the sequence-detected stateSTEP3:Fill the remaining input combinations 1. At A, when you get a 0, 0 is not a part of the sequence so it stays at A 2. At B, when you get a 1, 11 is not a part of the sequence but 1 is a part of the sequence and it’s the first bit of the sequence, so it will stay at B 3. At C, when you get a 0, 00 is not a part of the sequence so it goes back to A 4. At D, when you get a 0, 10 is a part of the sequence and it is 2 bits of the sequence so it goes to C 5. At E, when you get a 0, the sequence is detected and the output is 1. 10 is a part of the sequence and it is 2 bits of the sequence so it goes to C   Shivoo  Koteshwar’s  Notes                                          11                                                                                    shivoo@pes.edu              
  12. 12. Logic  Design  (3rd  Semester)                                                                                                                            UNIT  8  Notes  v1.0     6. At E, when you get a 1, 11 is not a part of the sequence but 1 is a part of the sequence and it’s the first bit of the sequence, so it will go to B   Shivoo  Koteshwar’s  Notes                                          12                                                                                    shivoo@pes.edu              

×