AN-835                                                                                                                    ...
AN-835TABLE OF CONTENTSScope ................................................................................................
AN-835BACKGROUND                                                                                                          ...
AN-835ANALOG SIGNAL SOURCE                                                              frequency of the guaranteed stop-b...
AN-835cascaded rejection should be about 140 dB. Although this is                           It is very important that an a...
AN-835The additive jitter of the AD9510 is about 0.22 ps, and the                                          DATA ACQUISITIO...
AN-835AC TEST DEFINITIONSAC or dynamic tests are typically made with the analog signal at               Signal-to-Noise Ra...
AN-835This is an indication of the average noise in each FFT bin. If the                         Most ADCs have specificat...
AN-835TWO-TONE FFT                                                                          2F1 ± F2 and 2F2 ± F1 (dBc)Whe...
AN-835NOISE POWER RATIO (NPR, dB)The noise power ratio (NPR) is a dynamic test that is used to assess                     ...
AN-835FULL POWER BANDWIDTH (MHz)Analog input bandwidth is the analog input frequency at whichthe spectral power of the fun...
AN-835DITHER TESTING                                                                     is often used in high performance...
AN-835ANALOG INPUT                                                                      The amount of power reflected back...
AN-835ANALOG INPUT FULL-SCALE RANGE (V p-p)Analog input full-scale range is the range of peak-to-peakvoltage (either singl...
AN-835COMMON-MODE INPUT RANGE (V)                                                         COMMON-MODE REJECTION RATIO (CMR...
AN-835APERTURE DELAY (ps)                                                             5.      Remove the shorting bar from...
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An 835 0
An 835 0
An 835 0
An 835 0
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An 835 0

  1. 1. AN-835 APPLICATION NOTEOne Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Understanding High Speed ADC Testing and Evaluation by Brad Brannon and Rob ReederSCOPE The FIFO board can be connected to a PC through a standardThis document describes both the characterization and USB cable and used with the ADC Analyzer software to quicklyproduction test methods used by Analog Devices’ High Speed evaluate the performance of high speed ADCs. Users can viewConverter Group to evaluate high speed ADCs. While this an FFT for a specific analog input and clock rate and analyzeapplication note should be considered a reference, it is not a SNR, SINAD, SFDR, and harmonic information. There aresubstitute for a product data sheet. single-channel and dual-channel versions of the FIFO board available. The FIFO data sheet should be consulted to determineDYNAMIC TEST HARDWARE SETUP which version is required for a specific ADC. LVDS and serialSNR, SINAD, worst spur, and IMD are tested using a hardware output devices may need an additional adapter board calledsetup similar to that shown in Figure 1. In production tests, the HSC-ADC-FPGA. This will be specified in the product datatest hardware is highly integrated, but the hardware principles sheet. For more detailed information on HSC-ADC-FPGA serialare the same. The basic setup for dynamic testing includes a LVDS adapter board, FIFO, and how the ADC Analyzer softwaresignal generator, band-pass filter, test fixture, low noise power works see the Analog Devices website www.analog.com/FIFO.supply, encode source (often integrated on the evaluationboard), data acquisition module, and data analysis software.Analog Devices provides application hardware and software toaid in bench evaluation. See the ADC FIFO Kit section. STANDARD WALL OUTLET USB 2.0 100V TO 240V AC 47Hz TO 63Hz 3.3V – + 6V DC SWITCHING 2A MAX POWER GND VCC SUPPLY CHB PARALLEL CMOS OUTPUTS PC HSC-ADC-EVALB-DC EVALUATION FIFO DATA RUNNING SINGLE OR DUAL HSC-ADC-EVALB-SC CAPTURE ADC ROHDE & SCHWARZ, BOARD BOARD ANALYZER HIGH-SPEED ADC OR SMHU, 2V p-p SIGNAL BAND-PASS XFMR EVALUATION BOARD HSC-ADC-EVALB-DC FILTER INPUT CHA SYNTHESIZER PARALLEL USB CMOS CONNECTION CHB FIFO, ROHDE & SCHWARZ, OUTPUTS PS REG n PS SMHU, CLK 32K, 05941-001 2V p-p SIGNAL SPI SPI SPI 133MHz SYNTHESIZER FILTERED +3.0V ANALOG REG Figure 1. Typical Characterization Test Setup LOGIC INPUT ADC TIMING CIRCUITADC FIFO KIT USB CTLR CHA FIFO,The high speed ADC FIFO evaluation kit (HSC-ADC-EVALA- n 32k, CLOCK 133MHzSC/HSC-ADC-EVALA-DC and HSC-ADC-EVALB-SC/HSC- CIRCUIT SPI SPIADC-EVALB-DC includes a memory board to capture blocksof digital data from Analog Devices’ high speed analog-to-digital CLOCK INPUT 05941-002converter (ADC) evaluation boards and ADC Analyzer™ software. 120-PIN CONNECTORFor more information on the ADC FIFO evaluation kit, visit Figure 2. Typical ADI ADC FIFO Kit Setupwww.analog.com/FIFO. Rev. 0 | Page 1 of 24
  2. 2. AN-835TABLE OF CONTENTSScope .................................................................................................. 1 Common-Mode Input Range (V) ............................................ 15Dynamic Test Hardware Setup ....................................................... 1 Common-Mode Rejection Ratio (CMRR, dB) ...................... 15ADC FIFO Kit................................................................................... 1 Aperture Delay (ps).................................................................... 16Revision History ............................................................................... 2 Aperture Jitter or Aperture Uncertainty (ps RMS) .................... 17Background ....................................................................................... 3 Crosstalk (dB) ............................................................................. 17 ADIsimADC ................................................................................. 3 Input-Referred Noise (LSB RMS) ............................................ 17 Analog Signal Source ................................................................... 4 Out-of-Range Recovery Time (CLK Cycles) ............................. 17 Analog Signal Filter...................................................................... 4 Digital Time Domain................................................................. 17 Encode signal sources .................................................................. 5 Conversion Error Rate (CER)................................................... 19 Power Supplies .............................................................................. 6 DC Test Definitions ....................................................................... 20 Data Acquisition........................................................................... 6 Gain Error (%FS)........................................................................ 20AC Test Definitions .......................................................................... 7 Gain Matching (%FS) ................................................................ 20 FFT Testing.................................................................................... 7 Offset Error (%FS) ..................................................................... 20 Single-Tone FFT ........................................................................... 7 Offset Matching (mV) ............................................................... 20 Two-Tone FFT .............................................................................. 9 Temperature Drift (ppm) .......................................................... 20 Noise Power Ratio (NPR, dB)................................................... 10 Voltage Output High/Voltage Output Low (VOH/VOL, V) ......20 Full Power Bandwidth (MHz) .................................................. 11 Linearity....................................................................................... 20 Dither Testing ............................................................................. 12 Power Supply Rejection Ratio (PSRR, dB) ............................. 22 Analog Input ............................................................................... 13 References........................................................................................ 23 Analog Input Full-Scale Range (V p-p)................................... 14REVISION HISTORY4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24
  3. 3. AN-835BACKGROUND 6V SWITCHING IDT72V283 32k × POWER SUPPLY 16-BIT 133MHz FIFO CONNECTION TIMING ADJUSTMENT JUMPERS ON BOARD +3.3V REGULATOR 120-PIN CONNECTOR (PARALLEL CMOS INPUTS) OPTIONAL POWER CONNECTION IDT72V283 32k × 16-BIT 133MHz FIFO USB CONNECTION TO COMPUTER OPEN SOLDER MASK ON ALL DATA AND CLOCK LINES FOR EASY PROBING OPTIONAL SERIAL RESET SWITCH µCONTROLLER CRYSTAL PORT INTERFACE WHEN ENCODE RATE CLOCK = 24MHz, 05941-003 CONNECTOR IS INTERRUPTED OFF DURING DATA CAPTURE Figure 3. Dual-Channel ADC FIFO BoardADIsimADC (no hardware required). Information about ADIsimADC can be found at www.analog.com/ADIsimADC. For more detailedADIsimADC™ is Analog Devices ADC behavioral modeling tool. information on ADIsimADC, see the AN-737 Application Note.ADIsimADC accurately models many of the time and frequencydomain errors common to ADCs. This tool can be invaluable interms of both simple converter selection and complete systemsimulation. The tool is fully integrated into the ADC Analyzersoftware to aid in simple converter selection; it is also supportedby several third-party CAD vendors. Currently, ADIsimADC issupported by MATLAB®, C++, National Instruments’ LabVIEW™and Signal Express, Agilent’s ADS, and Applied Wave Research’sVisual System Stimulatior™. Others will be available in the future.The tool can be downloaded from the website along with acomplete collection of current models. Links are providedto third-party tools that support ADIsimADC. (For moreinformation on ADIsimADC behavioral modeling, visitwww.analog.com/ADIsimADC.) 05941-004As mentioned, the tool is provided with ADC Analyzer software,which provides direct access to ADIsimADC, allowing users to Figure 4. ADC Analyzersimulate a given ADC based on a behavioral model of the ADC Rev. 0 | Page 3 of 24
  4. 4. AN-835ANALOG SIGNAL SOURCE frequency of the guaranteed stop-band performance. In the case of TTE’s Q56, the stop-band rejection is 60 dB.Usually, dynamic testing employs a Rohde & Schwarz 0dBc(www.rohde-schwarz.com) SMA/SMHU/SMG/SMGU, an J97Agilent (www.agilent.com) 8644 signal generator, or a Wenzel RELATIVE ATTENUATION (–10dB/DIV)(www.wenzel.com) crystal oscillator. These sources haveproven to provide exceptional performance (low phase noise,flat frequency response, and reasonable harmonic performance)for frequencies of a few kilohertz to those of a few gigahertz.Harmonic performance of these generators is typically not asgood as the intrinsic linearity of a given ADC, mandating theneed for additional filtering between the signal generator andthe analog input to the ADC.ANALOG SIGNAL FILTER 05941-005 F/Fo RATIOBoth fixed frequency and tunable frequency band-pass filters 0.1 1.0 1.6are utilized for device testing. The fixed frequency filters are NOTEtypically smaller than tunable filters and often provide slightly 1. REPRINTED WITH PERMISSION FROM TTE.better performance. Tunable filters allow testing across a wide Figure 5. Typical Performance of TTE’s J97range of frequencies using one filter. Several filter manufacturers, 0dBcincluding K&L Microwave (www.klmicrowave.com), TTE(www.tte.com), and Allen Avionics, Inc., (www.allenavionics.com), RELATIVE ATTENUATION (–10dB/DIV)provide excellent filters for ADC testing. Q34There are two types of filters that are often used for ADCtesting: low-pass filters and band-pass filters. These can be used Q56individually or combined to yield the level of performancerequired for an application.Low-pass filters are a good choice when a wide range of analogfrequencies must be applied to the ADC. However, they allownoise to pass from the signal generator to the ADC. This noise 05941-006may reduce the level of performance measured for the ADC. A F/Fo RATIOtypical low-pass filter is the J97 available from TTE. Usually, 0.6 1.0 1.4low-pass filters have a transition band that defines where the NOTE 1. REPRINTED WITH PERMISSION FROM TTE.pass band ends and the stop band begins. Along with this Figure 6. Typical Band-Pass Performance of TTE’s Q34 and Q56specification, a guaranteed stop-band rejection is specified. Inthe case of the J97, the transition band is defined to be between As noted previously, band-pass filters may only have a stop-1.0 and 1.2 times the 3 dB frequency, and the guaranteed stop- band rejection of 60 dB, meaning that signals that fall into theband rejection is 80 dB. Energy beyond 1.2 times the 3 dB stop band will be rejected by 60 dB. If, for example, a signalfrequency is reduced by a minimum of 80 dB. source has a harmonic that is 25 dB below the fundamental, theBand-pass filters are used when analog frequencies are fixed effective level of the harmonic is −85 dBc after a Q56 filter. Forand will not be changed. Band-pass filters also eliminate much many high performance ADCs, this is not sufficient. Whenof the wideband noise generated by signal sources and typically performance of −100 dBc or better is required, it is common toprovide the best performance for ADC testing. Filters such as cascade a band-pass filter with a low-pass filter. When selectingTTE’s Q56 series have a bandwidth defined as a percentage of a low-pass filter to follow a band-pass filter, the low-pass frequencythe center frequency. The more narrow the bandwidth, the less should be selected such that stop-band performance of the low-noise that passes through the filter; however, the analog frequency pass filter optimally filters any harmonics that pass through theis more restricted, and there is a greater insertion loss. Once a band-pass filter. With a J97 low-pass filter, stop-band rejectioncenter frequency is chosen, the bandwidth can be determined. is reached at 1.2 times the 3 dB frequency. If the second harmonicIdeally, a bandwidth of 5% to 6% should be selected, keeping in of the band-pass filter is set equal to 1.4 times the low-pass 3 dBmind that good noise performance is being traded for analog frequency, it ensures that all harmonics passing through the band-frequency flexibility. As with low-pass filters, the band-pass filter pass filter are filtered and that the additional insertion loss ofhas a transition band that defines the shape between the 3 dB the low-pass filter does not significantly reduce the level of thefrequency (above and below the center frequency) and the desired pass band. In this case, the low-pass frequency should equal 1.4 times the band-pass frequency and theoretically the Rev. 0 | Page 4 of 24
  5. 5. AN-835cascaded rejection should be about 140 dB. Although this is It is very important that an appropriate clock oscillator be used indifficult to achieve in practice due to coupling and radiation each ADC design. Selection of the proper clock is aided by Analogeffects, this technique is a useful one and can achieve well beyond Devices AN-501 Application Note and AN-756 Application Note.−100 dBc harmonic rejection. It is also worth noting that a 0.5 dB These application notes explain how to measure aperture jitterto 3 dB pad can be placed between the band-pass and low-pass and how to specify a clock that meets the required phase noise orseries combination. This helps to provide a better match between jitter specification. Failure to properly specify a clock source willthe two filters, which are nominally specified at 50 Ω. degrade SNR performance, as shown in Figure 8 and Figure 9.When specifying filters, request those made with large cores to As a reference, a typical Wenzel clock oscillator has about 0.07 psprevent saturation. Filters are typically designed for an input power of aperture jitter, whereas the CMOS clock oscillators have aboutof about 5 dBm. In many cases, however, ADC drive requirements 0.3 ps or more of aperture jitter.are much larger than this, causing core saturation and distortion.Specifying larger cores reduces the spurious distortion causedby core saturation. Finally, it is worth mentioning that filterconnectors can also be specified. Although adapters are easilyfound to convert between connector types, using them introducesmismatches that can subtly affect converter performance. Whilethis might not be a problem with 8-bit and 10-bit converters, itis quite noticeable with 12-, 14-, and 16-bit converters.ENCODE SIGNAL SOURCESFor high performance converters, stock signal generators usually 05941-008are insufficient as encode sources because of both close-in andwideband phase noise. Fixed-frequency oscillators are typicallyused for encode sources. High performance crystal oscillators Figure 8. AD9445 with Analog IF of 130 MHz @ −1.0 dBFS using a Wenzel Clock, SNR = 75.2 dBFSmanufactured by Wenzel (www.wenzel.com) and TechtrolCyclonetics, Inc., (TCI) (www.tci-ant.com) can be used. Wenzel’sSprinter and Ultra Low Noise series can offer optimum phasenoise performance. Another source of high quality encodesources is Valpey Fisher (www.valpeyfisher.com), which offersseveral options, including differential PECLs and VCXOs. Forless demanding applications, standard CMOS clock modulescan be used and are available from various manufacturers. Forend applications that require the clock to be synchronized withan external reference, a voltage-controlled crystal oscillator(VCXO) in a PLL loop can be employed. 05941-009 Figure 9. AD9445 with Analog IF of 130 MHz @ −1.0 dBFS using a CMOS Clock, SNR = 71.2 dBFS When clock sources are not available with the desired jitter performance, it is possible to divide a higher frequency clock into lower rates. This has the effect of reducing the jitter at the rate of 10 log(x), where x is the division ratio. The limitation of this, however, is the jitter of the gates themselves. The AN-501 Application Note provides an indication of the clock jitter associated with various logic families. When custom clocking is desired, a PLL is often required. A 05941-007 PLL allows the ADC to be synchronized to an external clock reference using a VCO or VCXO. However, it is difficult to Figure 7. Typical Low Cost CMOS Clock Oscillator clock more than one device using a simple PLL, but adding delays between the devices can facilitate such clocking. Devices such as the AD9510 are ideal for clock cleanup and distribution. Rev. 0 | Page 5 of 24
  6. 6. AN-835The additive jitter of the AD9510 is about 0.22 ps, and the DATA ACQUISITIONdevice is optimized for driving ADCs, DACs, and various logic Data acquisition and processing is accomplished with highdevices. speed caching memory. Data is collected at full ADC speed orPOWER SUPPLIES can be decimated depending on the testing method used. Bench testing uses the ADI FIFO kit data capture board (no decimationPower supplies for ADCs are very important. Therefore, it is required) in conjunction with the ADC Analyzer software (Seeimportant to provide clean, quiet power supplies because most the ADC FIFO Kit section for more details). Typically 16k, 32k,ADCs have poor power supply rejection ratios. While switching and 64k FFTs are performed, but bench FFTs can be as large asregulators are fine for many applications, linear regulators often 4M samples. When the analog input source is not synchronizedprovide a quieter, higher performance solution. Devices such as with the clock (noncoherent sampling), a Hanning or Blackman-the ADP3338 and ADP3339 provide very low noise and well- Harris windowing function is typically used. (For more infor-regulated sources, and they are very suitable for most ADC mation, see “On the Use of Windows for Harmonic Analysisapplications. Additionally, they are available in a variety of with the Discrete Fourier Transform,” Fredric J. Harris,voltages and can source up to 1 A to 1.5 A, respectively. Proceedings on the IEEE. Vol. 66, No. 1, January 1978.) OUT ADP3338/ 10µH VIN IN ADP3339 OUT VOUT 1µF 1µF GND 05941-011 Figure 10. ADP3338/ADP3339 Typical Application VS GND RSET CPRSET VCP DISTRIBUTION PLL REF AD9510 REF REFIN R DIVIDER PHASE REFINB FREQUENCY CHARGE PUMP CP N DIVIDER DETECTOR SYNCB, FUNCTION RESETB PDB PLL STATUS SETTINGS CLK1 CLK2 CLK1B CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 OUT1B LVPECL OUT2 /1, /2, /3... /31, /32 OUT2B SCLK LVPECL SDIO SERIAL OUT3 CONTROL /1, /2, /3... /31, /32 SDO PORT OUT3B CSB LVDS/CMOS OUT4 /1, /2, /3... /31, /32 OUT4B LVDS/CMOS OUT5 /1, /2, /3... /31, /32 ΔT OUT5B LVDS/CMOS OUT6 /1, /2, /3... /31, /32 ΔT OUT6B LVDS/CMOS OUT7 /1, /2, /3... /31, /32 05941-010 OUT7B Figure 11. AD9510 Low Jitter Clock Source Rev. 0 | Page 6 of 24
  7. 7. AN-835AC TEST DEFINITIONSAC or dynamic tests are typically made with the analog signal at Signal-to-Noise Ratio Referenced to Full Scalethe rated frequency with a signal power of 0.1 dB, 0.5 dB, or (SNRFS, dBFS)1 dB below full scale (dBFS). If different amplitudes are used, The signal-to-noise ratio referenced to full scale (SNRFS) is thethey will be defined in the data sheet test conditions. For these ratio of the rms full scale to the rms value of the sum of alltests, the encode rate is usually set at or near the maximum spectral components except the first six harmonics and dc.rated value. The data sheet should be consulted to determine SNRFS is expressed in decibels referenced to full scale (dBFS).the remainder of the test conditions, including power supply The difference between SNR and SNRFS is the differenceand temperature conditions. between the fundamental amplitude and full scale.FFT TESTING Signal-to-Noise-and-Distortion (SINAD, dB)Both coherent and noncoherent FFT testing can be used, The signal-to-noise and distortion (SINAD) is the ratio of thedepending on the actual test conditions. When coherent testing rms signal amplitude to the rms value of the sum of all spectralis used, the analog frequency is chosen such that the captured components, including harmonics but excluding dc. Thedata samples exercise as many converter codes as possible in the difference between SNR and SINAD is the energy contained inrecord length. This is accomplished by using a prime the first six harmonics.relationship between the analog frequency and the encode rate. User-Defined Signal-to-Noise Ratio (UDSNR, dB)For example, if coherent sampling is used and a 10 MHz User-defined signal-to-noise ratio (UDSNR) is a term used inanalog input is desired with a specified sample rate of ADC Analyzer software (see the ADC Analyzer User Manual).65 MSPS, the calculated coherent analog input frequency It is the ratio of the rms signal amplitude to the rms sum ofis 10.0015258789063 MHz, or exactly 2521 cycles. This can be all spectral components except the first six harmonics and dccalculated using the following equation: within the specified band set by the user. The ADC Analyzer f DESIRED _ FREQUENCY software allows the noise bandwidth to the left and right of the Cycles = desired signal to be set independently. UDSNR is reported in Sample _ Rate FFT _ Samples decibels. Noise Figure (NF, dB)The number of cycles should be rounded to the nearest integer.When possible, the nearest prime number should be selected to The noise figure (NF) is the ratio of the noise power at theensure that the maximum number of quantization levels of the output of a device to the noise power at the input to the device,converter are exercised. Once the number of cycles has been where the input noise temperature is equal to the referenceselected, the previous equation can be solved using the desired temperature (298 K). The noise figure is expressed in decibels.analog input frequency. The noise figure of an ADC can be computed for a singleFFT testing typically results in measurements expressed in configuration. Assuming that the input range, termination, anddecibels. Units can be expressed in dBc, which is the desired sample rate are fixed, the NF for an ADC can be calculatedsignal referenced to the carrier, or in dBFS, which is the desired using the following equation:signal referenced to the full scale of the converter. Either unit ⎛ V 2 rms /Z IN ⎞ ⎟ − SNRFS − 10 × log ⎛ Encode Frequency ⎞ ⎛ k ×T × B ⎞can be converted to the other by adding or subtracting the level Noise Figure = 10 × log ⎜ ⎜ ⎜ ⎟ ⎟ − 10 × log ⎜ 0.001 ⎟ ⎜ 0.001 ⎟ ⎝ 2 ⎠ ⎝ ⎠ ⎝ ⎠of the carrier from full scale. (For more information about FFTtesting, see “The FFT: Fundamentals and Concepts,” Tektronix, where:Inc., 070-1754-00, Production Group 45, first printing K = Boltzman’s constant = 1.38 × 10−23December 1975.) T = temperature in Kelvin = 273 K B = bandwidth = 1 HzSINGLE-TONE FFT Encode Frequency = ADC clock rateSignal-to-Noise Ratio (SNR, dB) V rms = rms full-scale input voltageThe signal-to-noise ratio (SNR) is the ratio of the rms signal ZIN = input impedanceamplitude to the rms value of the sum of all spectral SNRFS = full-scale ADC SNRcomponents except the first six harmonics and dc. As the input Noise Floor (dBFS)level is decreased, SNR typically decreases decibel-for-decibel ina linear fashion. Noise floor is a term used in ADC Analyzer software (see the ADC Analyzer User Manual). Noise floor is equivalent to ⎛ FFT Bins ⎞ Noise Floor = SNRFS − 10 log ⎜ ⎟ ⎝ 2 ⎠ Rev. 0 | Page 7 of 24
  8. 8. AN-835This is an indication of the average noise in each FFT bin. If the Most ADCs have specifications for one or more harmonics.size of the FFT is doubled, this number decreases by 3 dB. Noise Typically, the second and third harmonics are singled outfloor does not provide an absolute measurement, but instead because they have the worst performance of all the harmonics.gives a relative indication of where the noise is for a given setup. Harmonic distortion, no matter the order, is the ratio of the rmsEffective Number of Bits (ENOB, Bits) signal amplitude to the rms value of the specified harmonicThe effective number of bits (ENOB) provide a measure of an component, reported in dBc or dBFS.ADC’s performance that is expressed in bits. ENOB is most Because ADCs are nonlinear devices, the output is rich inaccurately measured using a sine wave, curve-fit method (see spectral components. The worst spurious energy may not beCalculate an ADCs Effective Bits). The most common method directly related to the first two harmonics (2HD and 3HD) andfor computing ENOB is to use the following equation based on is measured by the worst other spurious (WoSpur). WoSpur isthe SINAD at the full scale of the converter: the ratio of the rms signal amplitude to the rms value of the SINAD − 1.76 worst spurious component excluding the first six harmonically ENOB = 6.02 related components; it is reported in dBc.Spurious-Free Dynamic Range (SFDR, dBc) Total Harmonic Distortion (THD, dBc)The spurious-free dynamic range (SFDR) is the ratio of the rms Total harmonic distortion (THD) is the ratio of the rms signalvalue of the signal to the rms value of the peak spurious spectral energy to the rms value of the sum of the first six harmonics.component for the analog input that produces the worst result.In most cases, SFDR is a harmonic of the input signal applied to Harmonic Image (dBc)the ADC. The harmonic image measurement result is valid only when analyzing interleaved ADCs. This specification does not applyHarmonic Distortion (dBc or dBFS) to most ADCs. Harmonic image is the ratio of the rms signalA harmonic is a spectral component that is an integer multiple amplitude to the rms value of the nonharmonic componentof the driven analog input frequency. For example, the generated from the clocking phase difference of two ADCs,frequency of the second harmonic is twice the analog input. reported in dBc. WENZEL XTAL 1dB PAD1 1dB PAD1 ROHDE & SCHWARZ TTE OR K&L TTE OR K&L ANALOG MICROWAVE MICROWAVE AGILENT OUTPUT BPF LPF1 WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC ADC-FIFO DUT BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC USB 1 OPTIONAL TO IMPROVE PERFORMANCE. NOTES 1. AIN LEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 05941-012 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. Figure 12. Single-Tone Test Setup Rev. 0 | Page 8 of 24
  9. 9. AN-835TWO-TONE FFT 2F1 ± F2 and 2F2 ± F1 (dBc)When multiple tones are passed through a converter with These terms represent the third-order distortion products of thenonlinearities, intermodulation distortion products (IMD) converter. The measure of each term is the ratio of its rms valueresult. Two-tone testing in an ADC is a means of specifying to the rms value of one of the two input tones expressed in dBc.these nonlinearities. Because many of the distortion products The peak spurious component is considered an IMD product.may be relatively high in the analog spectrum, it is possible that Third-Order Input Intercept Point (IIP3, dBm)the frequencies have aliased. This should be kept in mind when The third-order input intercept point (IIP3) is the measure ofidentifying distortion products. the full-scale input signal power of the converter minus half theF1 + F2 (dBc) IMD third-order products. It is reported in dBm.This term represents the second-order distortion product that Worst Other Spur (WoSpur, dBc)appears at the frequency and is the sum of the two input fre- The worst other spur (WoSpur) is the worst resulting spuriousquencies. The measure of this term is the ratio of its rms value not related to the second- or third-order distortion productsto the rms value of one of the two input tones expressed in dBc. resulting from mixing two analog input signals. The measure ofF2 − F1 (dBc) this term is the ratio of its rms value to the rms value of one ofThis term represents the second-order distortion product that the two input tones expressed in dBc.appears at the frequency and is the difference of the two input Two-Tone SFDR (dBc)frequencies. The measure of this term is the ratio of its rms value The spurious-free dynamic range (SFDR) is the ratio of the rmsto the rms value of one of the two input tones expressed in dBc. value of the signal to the rms value of the peak spurious spectralSecond-Order Input Intercept Point (IIP2, dBm) component for the analog input that produces the worst result.The second-order input intercept point (IIP2) is the measure of In most cases, SFDR is a harmonic of the input signal applied tothe full-scale input signal power of the converter minus the the ADC.IMD second-order products. It is reported in dBm. 1dB TO WENZEL XTAL 10dB PAD1 ROHDE & SCHWARZ TTE OR K&L ANALOG MICROWAVE AGILENT OUTPUT BPF MINI-CIRCUITS COMBINER 1dB TO ZFSC-2-1 WENZEL XTAL 10dB PAD1 ROHDE & SCHWARZ TTE OR K&L ANALOG MICROWAVE AGILENT OUTPUT BPF WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC ADC-FIFO DUT BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC USB 1 OPTIONAL TO IMPROVE PERFORMANCE. NOTES 1. AIN LEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 05941-013 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. Figure 13. Two-Tone Test Setup Rev. 0 | Page 9 of 24
  10. 10. AN-835NOISE POWER RATIO (NPR, dB)The noise power ratio (NPR) is a dynamic test that is used to assess to determine the ratio of noise density in the notch to the noisethe converters performance with a fully loaded Gaussian noise density without the notch. The results are expressed in decibels.source. The noise level is adjusted such that the converter is loaded NPR is optimized just prior to clipping, as shown in Figure 14.just below the point of clipping with a Nyquist-limited noise source. Once clipping begins, NPR falls off rapidly as the input signal isThen a narrow band of noise is removed with a deep notch filter. increased. If the input signal is reduced, NPR falls off approx-The noise within the notch is measured using FFT techniques imately 1 dB for each decibel reduction in noise power. 86 0 16-BIT NPR = 60.83dB 81 NOTCH = 18.0MHz –20 NOTCH WIDTH = 3.0MHz 76 71 14-BIT AMPLITUDE (dBFS) –40 66 NPR (dB) 61 –60 12-BIT 56 –80 51 46 10-BIT –100 05941-014 05941-015 41 36 –120 –30 –25 –20 –15 –10 0 0 5 10 15 20 25 30 20 log (VO/N rms) (dBFS) FREQUENCY (MHz) Figure 14. Typical NPR Curves Figure 15. Typical NPR Response for a 12-Bit Converter 1dB NOISE/COM PAD NC7108 ANALOG 18MHz TTE OR NOISE GENERATOR OUTPUT NOISE/COM K&L MICROWAVE NOTCH FILTER ANTI-ALIAS FILTER WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC ADC-FIFO DUT BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC USB NOTES 1. SET NOISE/COM TO ~5dBm OR DECREMENT/INCREMENT FOR APPROPRIATE NOISE INPUT LEVEL. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 05941-016 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. 6. USE AN ADC-FIFO BOARD WITH AT LEAST 64k. Figure 16. NPR Test Setup Rev. 0 | Page 10 of 24
  11. 11. AN-835FULL POWER BANDWIDTH (MHz)Analog input bandwidth is the analog input frequency at whichthe spectral power of the fundamental frequency (as determinedby the FFT analysis) is reduced by 3 dB. A particular value ofSFDR or SNR performance is not implied by this test. 0 –1 –2 FUNDAMENTAL LEVEL (dB) –3 –3dB CUTOFF = 315MHz –4 –5 –6 –7 –8 05941-017 –9 –10 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 17. Typical Full Power Bandwidth Response TEE ROHDE & SCHWARZ ADAPTER AGILENT ANALOG ANALOG BOONTON OUTPUT INPUT 9200B RF VOLTMETER GPIB WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC ADC-FIFO DUT BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC GPIB USB NOTES 1. AIN LEVELS SHOULD BE ADJUSTED FOR –1dB AT A 10MHz REFERENCE FREQUENCY. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 05941-018 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. 6. BOONTON PROBES SHOULD USE UNTERMINATED ADAPTERS. Figure 18. Full Power Bandwidth Test Setup Rev. 0 | Page 11 of 24
  12. 12. AN-835DITHER TESTING is often used in high performance test equipment. In this configuration, wideband analog noise is added to the input andApplying extra noise to an ADC’s analog input causes dithering the digital equivalent is subtracted from the output. The netof the transfer function, reducing the spurious caused by static effect of either technique is that spurious performance of thenonlinearities. While dither does little to reduce distortion converter is greatly enhanced. For more details, see the AN-410caused by slew rate limitations, it is very efficient at reducing Application Note.localized errors that hinder ADC performance. It is common for spurious performance to improve by 15 dB orThere are two types of dither: out-of-band and wideband. As more when dither is used, depending on the application. Manyshown in the setup in Figure 19, out-of-band dither is band- data sheets include dithered performance plots for comparison.limited noise placed out of band, where it will not spectrally In addition, using the ADC Analyzer software with ADIsimADCdisrupt converter performance. This technique is commonly allows dither to be added to the simulation, further demonstratingused in communication systems, where digital filters are used to how dither will improve performance.select desired signals and filter out all others. Wideband dither 1dB NOISE/COM PAD DNG7500 TTE OR K&L ANALOG NOISE GENERATOR MICROWAVE OUTPUT 1.5MHz MINI-CIRCUITS COMBINER 1dB ZFSC-2-1 WENZEL XTAL PAD ROHDE & SCHWARZ TTE OR K&L ANALOG MICROWAVE AGILENT OUTPUT BPF WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC ADC-FIFO DUT BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC USB NOTES 1. AIN LEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 05941-019 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. ADJUST DC BINS TO EXCLUDE DITHER. 6. USE AN ADC-FIFO BOARD WITH AT LEAST 64k. 7. ADJUST NOISE/COM DITHER LEVEL FOR MAXIMUM SFDR PERFORMANCE. Figure 19. Dither Test Setup Rev. 0 | Page 12 of 24
  13. 13. AN-835ANALOG INPUT The amount of power reflected back from the device can beAnalog Input Impedance computed from the input impedance based on the followingAnalog input impedance is the ratio of the complex input equation:voltage divided by the complex input current for the analog Z IN − Z 0input. Analog input impedance is typically measured with a ρ= Z IN + Z 0network analyzer and displayed on a Smith chart. where:In some instances, the complex input can be broken down into ρ is the amount of power reflected back from the device.resistive, capacitive, or inductive terms and reported as such. ZIN is the complex input impedance of the ADC.Voltage Standing Wave Ratio (VSWR) Z0 is the desired impedance of the network.VSWR is a measure of the amount of power that is reflected From the reflection coefficient, the VSWR can be calculated byback from the input of the ADC. This is a measure of the using the following equation:efficiency of the transfer of energy to the input port of the ADC. 1+ ρ VSWR = 1− ρ ENA5071B NETWORK ANALYZER WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC DUT STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx EVALUATION BOARD NOTES 1. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 2. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 3. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 05941-020 4. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. 5. CALIBRATE NETWORK ANALYZER (3.5mm CALIBRATION KIT, PART NO. 85033C OR EQUIVALENT. Figure 20. Analog Input Impedance and VSWR Test Setup Rev. 0 | Page 13 of 24
  14. 14. AN-835ANALOG INPUT FULL-SCALE RANGE (V p-p)Analog input full-scale range is the range of peak-to-peakvoltage (either single-ended or differential) that can be appliedto the analog input(s) of the converter to generate a valid full-scale response. ROHDE & SCHWARZ AGILENT ANALOG ANALOG BOONTON OUTPUT INPUT 9200B RF VOLTMETER GPIB WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC ADC-FIFO DUT BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC GPIB USB NOTES 1. AIN LEVELS SHOULD BE ADJUSTED FOR –1dB AT 10MHz. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 05941-021 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. 6. BOONTON PROBES SHOULD USE UNTERMINATED ADAPTERS. Figure 21. Analog Input Full-Scale Range Test Setup Rev. 0 | Page 14 of 24
  15. 15. AN-835COMMON-MODE INPUT RANGE (V) COMMON-MODE REJECTION RATIO (CMRR, dB)Common-mode input range is the range of dc offsets applied to The common-mode rejection ratio (CMRR) is defined as theboth inputs of a differential input ADC for which the converter amount of rejection on the differential analog inputs when awill operate normally. For many converters, the range is very common signal is applied. Typically, CMRR is expressed inlimited, but some operate over a wide common-mode range. decibels and can be calculated as shown in the followingThe converter’s data sheet should be consulted to determine the equation:specific common-mode range. ⎛ A ⎞ CMRR = 20 log ⎜ DIFFERENTIAL ⎟ ⎜ ACOMMON MODE ⎟ ⎝ ⎠ WENZEL XTAL 1dB PAD1 1dB PAD1 ROHDE & SCHWARZ TTE OR K&L TTE OR K&L ANALOG MICROWAVE MICROWAVE AGILENT OUTPUT BPF LPF1 WENZEL XTAL ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR VCC ANALOG AGILENT INPUT INPUT SINGLE-ENDED ADC-FIFO ADC BOARD DUT STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC USB 1 OPTIONAL TO IMPROVE PERFORMANCE. NOTES 1. AIN LEVELS SHOULD BE ADJUSTED FOR THE FREQUENCY AND LEVEL SPECIFIED. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 05941-022 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. 6. RESISTIVE DIVIDER MAY NOT BE NECESSARY FOR SOME ADCs. Figure 22. CMRR Test Setup Rev. 0 | Page 15 of 24
  16. 16. AN-835APERTURE DELAY (ps) 5. Remove the shorting bar from the analog input and reconnect the analog input as shown in Figure 23.Aperture delay (AD) is a measure of the difference in the delaybetween the analog path and the encode path. It is measured by 6. Record the new offset value and use it to solve theobserving the time from the 50% point of the rising edge of the following equation: ⎛ (Code AVERAGE − Offset )/(2 N / 2) ⎞sample clock to the time at which the input signal is actuallysampled. t AD = sin −1 ⎜ ⎟ ⎜ 2π × Frequency ⎟ ⎝ ⎠AD can be measured by using the following test configuration: where:1. Connect the analog input to an analog filtered source. 2N/2 is the midscale of a 16-bit ADC.2. Using a program like ADC Analyzer, adjust the input until Offset is the offset of the part measured using a continuous the single-tone FFT results in a full-scale signal (0 dBFS). average time domain plot (see Step 4). CodeAVERAGE is the new offset value obtained after removing3. Disconnect the analog input, and use a shorting bar to the shorting bar from the analog input and reconnecting short the analog input to ground. the analog input (see Step 5).4. Use a continuous average time domain plot to measure the offset of the part. WENZEL XTAL ROHDE & SCHWARZ ANALOG AGILENT OUTPUT TEE SHORTING ADAPTER BAR WENZEL XTAL ANALOG ROHDE & SCHWARZ DIFFERENTIAL ENCODE OR INPUT AGILENT INPUT SINGLE-ENDED ADC ADC-FIFO DUT BOARD STANDARDIZED 6V TO 9V SUPPLY OR LAB SUPPLIES INPUT AD92xx, AD94xx, OR AD66xx SUPPLY EVALUATION BOARD INPUT STANDARDIZED 6V TO 9V OR LAB SUPPLIES MONITOR PC USB NOTES 1. AIN LEVELS SHOULD BE ADJUSTED FOR 0dBFS OUTPUT FOR THE INPUT FREQUENCY OF MIDBAND. 2. ENCODE SETTING SHOULD BE ADJUSTED TO THE SPECIFIED RATE. 3. UNLESS ONBOARD REGULATORS ARE USED, SUPPLIES SHOULD BE AT NOMINAL. 05941-023 4. TEMPERATURE SHOULD BE AT AMBIENT, UNLESS OTHERWISE NOTED. 5. USE THE APPROPRIATE CONFIGURATION FILE FOR ADC ANALYZER. Figure 23. Aperture Delay Test Setup Rev. 0 | Page 16 of 24

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