Unit – 2

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I/O Memory Interface

Programmable, Interrupt initiated, DMA, Serial and Parallel Interfaces for data transfer
Detailed study of 8251 USART chip

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Unit – 2

  1. 1. Unit – 2 I/O Memory Interface <ul><li>Topics: </li></ul><ul><li>Programmable, Interrupt initiated, DMA, Serial and Parallel Interfaces for data transfer </li></ul><ul><li>Detailed study of 8251 USART chip </li></ul>
  2. 2. Content <ul><li>Introduction to data transfer techniques </li></ul><ul><li>Programmed Data Transfer </li></ul><ul><li>DMA Controlled Data Transfer </li></ul><ul><li>8251 USART – A Serial I/O Processor </li></ul>
  3. 3. 1. Introduction to Data Transfer Techniques <ul><li>Data transfer may take place between two devices. For e.g. </li></ul><ul><ul><li>Microprocessor and memory </li></ul></ul><ul><ul><li>Microprocessor and I/O device </li></ul></ul><ul><ul><li>Memory and I/O device </li></ul></ul><ul><li>Classification of data transfer techniques </li></ul><ul><ul><li>Programmed data transfer </li></ul></ul><ul><ul><li>Direct Memory Access (DMA) </li></ul></ul>
  4. 4. 2. Programmed Data Transfer <ul><li>Data is transferred from the I/O device to the microprocessor or memory </li></ul><ul><li>Data is transferred under the control of the program stored in the program memory of the microprocessor based system </li></ul><ul><li>This technique of data transfer is normally used if the size of data to be transferred is small </li></ul>
  5. 5. Programmed data transfer techniques <ul><li>Classified as </li></ul><ul><ul><li>Parallel data transfer </li></ul></ul><ul><ul><li>Serial data transfer </li></ul></ul><ul><ul><li>Synchronous data transfer </li></ul></ul><ul><ul><li>Asynchronous data transfer </li></ul></ul><ul><ul><li>Interrupt Initiated data transfer </li></ul></ul>
  6. 6. Parallel Data Transfer <ul><li>All the bits are transferred at the same time </li></ul><ul><li>Used for data transfer between nearby devices </li></ul><ul><ul><li>E.g microprocessor and program memory </li></ul></ul><ul><li>Advantage </li></ul><ul><ul><li>Data transfer is very fast </li></ul></ul>
  7. 7. Serial data transfer <ul><li>Data is transferred one bit at a time </li></ul><ul><li>Suitable for data transfer over long distances </li></ul><ul><ul><li>E.g. dial-up internet connections using modems </li></ul></ul><ul><li>Data transfer is slow as compared to parallel data transfer technique </li></ul>
  8. 8. Comparison of Parallel/ Serial <ul><li>Parallel </li></ul><ul><li>8 bits of data tranferred at a time </li></ul><ul><li>9 lines required to connect two devices </li></ul><ul><li>Advantageous over small distances </li></ul><ul><li>Serial </li></ul><ul><li>Only 1 bit of data is transferred at a time </li></ul><ul><li>2 lines required to connect two devices </li></ul><ul><li>Advantageous over long distances </li></ul>
  9. 9. Synchronous data transfer <ul><li>Used when the I/O device is always in the ready state for data transfer </li></ul><ul><li>Microprocessor reads / writes to the I/O device without checking if it is in a ready state </li></ul><ul><li>For e.g. data transfer from 8085 microprocessor to a 7-segment display </li></ul>
  10. 10. Asynchronous Data Transfer <ul><li>Microprocessor reads the status of a device to check if it is ready for data transfer </li></ul><ul><li>This method is also known as polling method of handling I/O devices </li></ul><ul><li>Handshake signals are used for communication between microprocessor and I/O devices </li></ul><ul><li>Used to connect slower peripherals with microprocessor </li></ul>
  11. 11. Comparison of Asynchronous/ Synchronous Data Transfer techniques <ul><li>Asynchronous </li></ul><ul><li>Used to transfer one character at a time </li></ul><ul><li>Start and stop bits are used with each character </li></ul><ul><li>Speed is less </li></ul><ul><li>Transmitter and receiver can use two separate clock inputs </li></ul><ul><li>Synchronous </li></ul><ul><li>Used to transfer a block of characters at a time </li></ul><ul><li>No start/ stop bits are used </li></ul><ul><li>Speed is high </li></ul><ul><li>Transmitter and receiver share a common clock </li></ul>
  12. 12. Interrupt Initiated Data Transfer <ul><li>Microprocessor initiates the interrupt mechanism and starts executing the main program </li></ul><ul><li>I/O device informs the microprocessor that it is ready by generating an interrupt signal </li></ul><ul><li>Microprocessor services the interrupt by completing the data transfer </li></ul>
  13. 13. 3. DMA Controlled Data Transfer <ul><li>DMA stands for Direct Memory Access </li></ul><ul><li>used when large amount of data is to be transferred </li></ul><ul><li>Microprocessor does not participate in this type of data transfer </li></ul><ul><li>Data is transferred directly between an I/O device and memory or vice-versa </li></ul><ul><li>Data transfer is controlled by an I/O device or a DMA controller </li></ul><ul><li>DMA data transfer is fast as compared to programmed data transfer </li></ul>
  14. 14. Microprocessor Memory DMA Controller I/OPort I/OPort I/OPort External device External device External device
  15. 15. 8085 signals used for DMA <ul><li>DMA controlled data transfer uses two pins HOLD (pin 39) and HLDA (pin 38) of 8085 </li></ul><ul><li>HOLD – </li></ul><ul><ul><li>An input signal to 8085 from a DMA controller </li></ul></ul><ul><ul><li>It is a request to 8085 to hand over the control of data and address bus to a DMA controller </li></ul></ul><ul><li>8085 responds to HOLD request by </li></ul><ul><ul><li>Freeing up the buses for use by a DMA device </li></ul></ul><ul><ul><li>Sending out Hold acknowledge signal HLDA on pin 38 </li></ul></ul>
  16. 16. DMA Modes of Operation <ul><li>DMA operates in these two modes </li></ul><ul><ul><li>Slave Mode </li></ul></ul><ul><ul><li>Master Mode </li></ul></ul><ul><li>Slave Mode </li></ul><ul><ul><li>DMA behaves as a I/O peripheral requesting the microprocessor for the control of the buses </li></ul></ul><ul><li>Master Mode </li></ul><ul><ul><li>DMA plays the role of a data transfer processor to peripherals such as floppy disks </li></ul></ul>
  17. 17. DMA Data Transfer Techniques <ul><li>These are </li></ul><ul><ul><li>Burst or Block transfer DMA </li></ul></ul><ul><ul><li>Cycle Steal or Single Byte transfer DMA </li></ul></ul><ul><ul><li>Transparent or Hidden DMA </li></ul></ul>
  18. 18. Burst or Block Transfer <ul><li>It is the fastest DMA mode </li></ul><ul><li>Two or more data bytes are transferred continuously </li></ul><ul><li>N number of DMA cycles are added into the machine cycles of the microprocessor </li></ul><ul><li>DMA controller sends HOLD signal to 8085 and waits for HLDA </li></ul><ul><li>After receiving HLDA signal, DMA controller gains control of buses and executes DMA cycle to transfer 1 byte </li></ul><ul><li>Then it increments the memory address, decrements the COUNT and transfers the next byte </li></ul>
  19. 19. Cycle Steal/ Single Byte Transfer DMA <ul><li>Only 1 byte is transferred at a time </li></ul><ul><li>Slower than the burst DMA </li></ul><ul><li>Only 1 DMA cycle is added between 2 machine cycles of the microprocessor </li></ul><ul><li>DMA controller sends HOLD signal to 8085 and waits for HLDA </li></ul><ul><li>After receiving HLDA signal, DMA controller gains control of buses and executes DMA cycle to transfer 1 byte </li></ul><ul><li>After single byte transfer, it disables the HOLD signal and goes into SLAVE mode again </li></ul>
  20. 20. Transparent or Hidden DMA <ul><li>Microprocessor executes some states during which it floats the address and data buses </li></ul><ul><li>During these states the microprocessor is isolated from the system bus </li></ul><ul><li>Transparent or Hidden DMA uses these states to transfer data between memory and I/O devices </li></ul><ul><li>This type of DMA transfer does not reduce the speed of the microprocessor </li></ul><ul><li>This is the slowest type of DMA transfer </li></ul>
  21. 22. 4. 8251 USART – A Serial I/O Processor <ul><li>8251 is a programmable USART chip designed for Synchronous and Asynchronous serial communication </li></ul><ul><li>USART stands for Universal Synchronous/ Asynchronous Receiver and Transmitter </li></ul><ul><li>It is used to implement hardware-controlled serial I/O in a microprocessor based system </li></ul>
  22. 23. How 8085 uses 8251 for serial communication? <ul><li>8085 initializes 8251 chip by sending some command words to it </li></ul><ul><li>8085 sends a 8-bit data value to 8251 for serial data transfer </li></ul><ul><li>8251 converts this parallel data into serial stream and transmits on serial output line </li></ul><ul><li>Similarly, 8251 can receive data on serial input line, converts it to parallel form and then transfers it to 8085 microprocessor </li></ul>
  23. 24. Block Diagram of 8251
  24. 25. Features of 8251 <ul><li>Supports both synchronous and asynchronous modes of operation </li></ul><ul><li>Synchronous baud rate – 0 to 64 K baud </li></ul><ul><li>Asynchronous baud rate – 0 to 19.2 K baud </li></ul><ul><li>Contains full duplex double buffered system </li></ul><ul><li>Provides error detection to detect parity and framing errors </li></ul><ul><li>Compatible with INTEL microprocessors </li></ul><ul><li>28-pin DIP package, TTL compatible </li></ul><ul><li>Single +5V supply </li></ul>
  25. 26. References <ul><li>Chapter – 15,16 of “Microprocessor Architecture, Programming, and Applications with the 8085” by Ramesh Gaonkar </li></ul><ul><li>Chapter – 10 of “Microprocessor and Assembly Language Programming” by U.S. Shah </li></ul><ul><li>http://www.electronics.dit.ie/staff/tscarff/8251usart/8251.htm </li></ul><ul><li>Resources on Chalkpad </li></ul>

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