Chapter 3 cmos(class2)

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Chapter 3 cmos(class2)

  1. 1. 1 CMOS Digital Integrated Circuits Analysis and Design Chapter 3 MOS Transistor
  2. 2. 2 The Metal Oxide Semiconductor (MOS) structure • The structure consists of three layer – The metal gate electrode – The insulating oxide (SiO2) layer – The p-type bulk semiconductor • The basic properties of the semiconductor Ap A i n A i Np, N n econcptronandholibriumelecthen equil n Nncentratiodoping cosubstrateAssume the npnction law:The mass a ≅≅ =⋅ 0 2 0 2 n=mobile carrier concentration of electron P=mobile carrier concentration of hole
  3. 3. 3 Energy band diagram of a p-type silicon substrate
  4. 4. 4 qx. bygivenisandlevelvacuumtheandLevel bandconductionebetween thDifference potentialtheissiliconofaffinityElectron int ln ln )-E(Eqχqφ k functioned the worce is callo free spalFermi leve heove from tctron to mfor an elerequiredThe energy n N q kT ductor, φpe semiconFor a n-ty N n q kT ductor, φpe semiconFor a p-ty q -EE φpotentialThe Fermi Fcs i D Fn A i Fp iF F += = = =
  5. 5. 5
  6. 6. 6 Energy diagram of the combined MOS system • The equilibrium Fermi levels of the semiconductor (Si) substrate and the metal gate are at the same potential • The bulk Fermi level is not significantly affected by the bending • The surface Fermi level moves closer to the intrinsic Fermi level
  7. 7. 7 Example 1
  8. 8. 8 The MOS System under External Bias - accumulation • A negative voltage VG is applied to the gate electrode. – The holes in the p-type substrate are attracted to the semiconductor- oxide surface – The majority carrier concentration > the equilibrium hole concentration • The electron concentration (minority carrier) decreases as the negatively charged electron are pushed deeper into the substrate – The oxide electric field is directed towards the gate electrode – Causing the energy bands bend up-ward near the surface
  9. 9. 9 The MOS System under External Bias – depletion • A small positive gate bias VG is applied to the gate electrode – The oxide electric field will be directed towards the substrate – Causing the energy bands to bend downward near the surface – The majority carrier (hole) will be repelled back into the substrate • Leaving negatively charged fixed acceptor ions behind (depletion region)
  10. 10. 10 FsSiAdA A FsSi d Si dA Fs x Si A s Si A Si s A NqxNqQ Nq x xNq dx xNq d dx xNqdQ xd dxNqdQ s F d φφε φφε ε φφ ε φ εε φ φ φ −⋅⋅⋅−=⋅⋅−= ⋅ −⋅ = ⋅⋅ =− ⋅⋅ = ⋅⋅ =⋅−= ⋅⋅−= ∫ ∫ 2 2 2 2 0 Assume that the mobile hole charge in a thin horizontal layer parallel to the surface is The change in surface potential Required to displace this charge sheet dQ by a distance xd away from the surface can be found by using Poisson equation Integrating along the vertical dimension gives Thus, the depth of the depletion region is And the depletion region charge density is given by
  11. 11. 11 The MOS System under External Bias – inversion • A further increase in the positive gate bias – Increasing surface potential the downward bending of the energy bands will increase – The mid-gap energy level Ei becomes smaller than the Fermi level EFp on the surface • The substrate semiconductor in this region become n-type • The electron density is larger than the majority hole density • Inversion layer, surface inversion • Can be utilized for conducting current between two terminal of the MOS transistor – The surface is said to be inverted • The density of mobile electrons on the surface becomes equal to the density of holes in the bulk substrate • Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi potential φF • Further increase gate voltage  electron concentration↑  but not to an increase of the depletion depth A FSi dm Nq x ⋅ ⋅⋅ = φε 22
  12. 12. 12 The physical structure of a n-channel enhancement-type MOSFET • MOS structure – polysilicon gate, thin oxide layer, semiconductor • Source, drain n+ -region – The current conducting terminals of the device • Conducting channel, channel length L, channel width W – The device structure is completely symmetrical with respect to the drain and source • The simple operation of this device – Controlling the current conduction between the source and the drain, using the electric field generated by the gate voltage as a control variable
  13. 13. 13 Circuit symbols for enhancement-type MOSFET • Enhancement-mode MOSFET – No conducting region at zero gate bias • Depletion-mode MOSFET – A conducting channel already exists at zero gate bias • The abbreviations used for device terminals are – G for the gate, D for the drain, S for the source, and B for the substrate • The small arrow always marks the source terminal
  14. 14. 14 Formation of a depletion region • For small gate voltage level – The majority carriers (holes) are repelled back into the substrate – The surface of the p-type substrate is depleted – Current conduction between S and D is not possible
  15. 15. 15 Formation of an inversion layer • As the gate-to-source voltage is further increased – The surface potential reaches -φFp  surface inversion will be established  conducting channel between S and D – Allowing current flow, as log as there is a potential difference between S and D – VGS<VT0 (threshold voltage) • Not sufficient to establish an inversion layer • No current between S and D – VGS>VT0 (threshold voltage) • Electrons are attracted to the surface – Contributing to channel current conduction – Further increase gate voltage • Not affect the surface potential and the depletion region depth
  16. 16. 16 The threshold voltage • Four physical components of VT0 – The work function difference between gate and the channel ∀ φGC= φF(substrate)- φM for metal gate ∀ φGC= φF(substrate)- φF(gate) for polysilicon gate – The gate voltage component to change the surface potential(to achieve surface inversion) .To change the surface potential by -2φF – The gate voltage component to offset the depletion region charge • -QB/Cox • – The voltage component to offset the fixed charge in the gate oxide and in the silicon-oxide interface(due to impurities and/or lattice imperfections at the interface) ox ox ox SBFSiAB t C VNqQ ε φε = +−⋅⋅⋅−= 22The depletion region charge Density is given as
  17. 17. 17 ( ) tcoefficieneffectbodybiassubstrate C Nq VVV C Q C Q V ox SiA FSBFTT ox ox ox B FGCT )( 2 ewher effect)body(with22 effect)body(no2 0 0 0 −−= ⋅⋅ = −+−⋅+= −−−Φ= γ ε γ φφγ φ
  18. 18. • Compared with the p-MOSFET – The substrate Fermi potential φF is negative in NMOS, positive in pMOS – The depletion region charge densities QB0 and QB are negative in nMOS, positive in pMOS – The substrate bias coefficient γ is positive in nMOS, negative in pMOS – The substrate bias voltage VSB is positive in nMOS, negative in pMOS • Threshold voltage adjustment • For n-channel MOS – Implanting p-type impurity  VT increased – Implanting n-type impurity  VT decreased – The amount of change in the threshold voltage as a result of extra implant • qNI/Cox where Ni is the density of implanted impurities 18
  19. 19. 19 Example 2
  20. 20. 20
  21. 21. 21 Circuit symbols for n-channel depletion-type MOSFETs • Using selective ion implantation into the channel – The threshold voltage for nMOSFET can be made negative – Having a conducting channel at VGS=0
  22. 22. 22
  23. 23. 23 Example 3
  24. 24. 24 MOSFET operation: linear region • The MOSFET consists – A MOS capacitor, two pn junction adjacent to the channel – The channel is controlled to the MOS gate • The carrier (electron in nMOSFET) – Entering through source, controlling by gate, leaving through drain • To ensure that both p-n junctions are reverse-biased initially – The substrate potential is kept lower than the other three terminal potentials • When 0<VGS<VT0 – G-S region depleted, G-D region depleted – No current flow • When VGS>VT0 – Conduction channel formed – Capable of carrying the drain current – As VDS=0 • ID=0 – As VDS>0 and small • ID proportional to VDS • Flowing from S to D through the conducting channel • The channel act as a voltage controlled resistor • The electron velocity much lower than the drift velocity limit • As VDS↑the inversion layer charge and the channel depth at the drain end start to decrease
  25. 25. 25 MOSFET operation: saturation region • For VDS=VDSAT – The inversion charge at the drain is reduced to zero – Pinch off point • For VDS>VDSAT – A depleted surface region forms adjacent to the drain – As further increases VDS  this depletion region grows toward the source – The channel-end voltage remains essentially constant and equal to VDSAT – The pinch-off (depleted) section • Absorbs most of the excess voltage drop, VDS-VDSAT • A high-field region forms between the channel-end and the drain boundary – Accelerating electrons, usually reaching the drift velocity limit
  26. 26. 26 MOSFET current-voltage characteristics-gradual channel approximation (GCA)(1) • Considering linear mode operation – VS=VB=0, the VGS and VDS are the external parameters controlling the drain current ID – VGS > VT0 (assume constant through the channel) to create a conducting inversion layer – Defining • X-direction: perpendicular to the surface, pointing down into the substrate • Y-direction: parallel to the surface – The y=0 is at the source end of the channel – Channel voltage with respect to the source, Vc(y) – Assume the electric field Ey is dominant compared with Ex • This assumption reduced the current flow in the channel to the y-direction only – Let QI(y) be the total mobile electron charge in the surface inversion layer • QI(y)=-Cox[VGS-Vc(y)-VT0]
  27. 27. 27
  28. 28. 28 MOSFET current-voltage characteristics-gradual channel approximation (GCA)(2) ( ) ( )[ ] ( )[ ] ( )[ ] L W kwhere kVVVV k I Cμwhere kVVVV L Wk I VVVV L WC I dVVVVCWLI dVyQWdyI dy (y)QμW I -dRIdV yisdropalongdThevoltage μ Q (y)QμW dy dR cesislincrementa Theμ ' DSDSTGSD oxn ' DSDSTGSD DSDSTGS oxn D V CTCGSoxnD V CI L D In D DC n I In n DS DS ⋅=−−⋅⋅= =−−⋅⋅⋅= −−⋅⋅⋅ ⋅ = ⋅−−⋅⋅=⋅ ⋅⋅−=⋅ ⋅ ⋅⋅ =⋅= ⋅⋅ −= ∫ ∫∫ 2 0 2 0 ' 2 0 0 0 0 n 0 2 2 2 2 2 2 )( mobilityelectronbulktheofthatofhalf-oneabouttypicallyismagnitudeitsand region,channeltheofionconcentratdopingon thedependentsmobilitysurfaceelectronThe )chargelayerinversiontheofpolaritynegativethetodueissign(mimus tanRe mobilitysurfaceconstantahaslayerinversionin theelectronsmobileallthatAssumeing µ µ µ
  29. 29. 29 Example 4
  30. 30. 30 MOSFET current-voltage characteristics-gradual channel approximation (GCA)-saturation region • For VDS≥VDSAT=VGS-VT0 – – The drain current becomes a function only of VGS, beyond the saturation boundary ( ) ( ) ( )[ ] ( )2 0 2 000)( 2 2 2 TGS oxn TGSTGSTGS oxn satD VV L WC VVVVVV L WC I −⋅⋅ ⋅ = −−−⋅−⋅⋅⋅ ⋅ = µ µ
  31. 31. 31 Channel length modulation ( ) ( ) ( ) ( ) ( ) ( )DSTGS oxn D(sat) DS DS DSATDS TGS oxn D(sat) TGS' oxn D(sat) I ' I TGSDSATDS DSTGSoxI TGSoxI λVVV L WCμ I λλ , λVλ L ΔL VVΔL VV L WCμ L ΔL I VV L WCμ I QΔ L-ΔL L)(yQ -VVV, V V-VV-CL)(yQ -VV-C)(yQ +⋅−⋅⋅ ⋅ = << ⋅−≈− −∝ −⋅⋅             − = −⋅⋅= = = ≈= == −⋅== ⋅== 1 2 1thatAssuming tcoefficienmodulationlengthchannel11useWe 21 1 2 0thsegment wichanneltheoflengththeisLwhere L lengthchanneleffectiveThe 0 smallverybecomeenddrainat thechargelayerinversionThe saturationofedgeat thethatNote ischanneltheofenddrainat thechargelayerinversiontheand 0 ischanneltheofendsourceat thechargelayerinversionThe 2 0 2 0 2 0 0 0 0
  32. 32. 32 Substrate bias effect • The discussion in the previous has been done under the assumption – The substrate potential is equal to the source potential, i.e. VSB=0 • On the other hand – the source potential of an nMOS transistor can be larger than the substrate potential, i.e. VSB>0 – ( ) ( )[ ] ( ) ( )DSSBTGS oxn satD DSDSSBTGS oxn linD FSBFTSBT VVVV L WC I VVVVV L WC I VVVV ⋅+⋅−⋅⋅ ⋅ = −−⋅⋅⋅ ⋅ = −+⋅+= λ µ µ φφγ 1)( 2 )(2 2 22)( 2 )( 2 )( 0
  33. 33. 33 Current-voltage equation of n-, p-channel MOSFET ( )[ ] ( ) ( ) ( )[ ] ( ) ( ) TGSDS TGSDSTGS oxp satD TGSDS TGSDSDSTGS oxp linD TGSD TGSDS TGSDSTGS oxn satD TGSDS TGSDSDSTGS oxn linD TGSD -VVV VVVVV L WC I -VVV VVVVVV L WC I VVI -VVV VVVVV L WC I -VVV VVVVVV L WC I VVI ≤ ≤⋅+⋅−⋅⋅ ⋅ = > ≤−−⋅⋅⋅ ⋅ = >= ≥ ≥⋅+⋅−⋅⋅ ⋅ = < ≥−−⋅⋅⋅ ⋅ = <= and for1 2 and for2 2 for,0 MOSFETchannel-pFor and for1 2 and for2 2 for,0 MOSFETchannel-nFor 2 )( 2 )( 2 )( 2 )( λ µ µ λ µ µ
  34. 34. 34 Measurement of parameters- kn, VT0, and γ • The VSB is set at a constant value – The drain current is measured for different values of VGS – VDG=0 • VDS>VGS-VT is always satisfied  saturation mode • Neglecting the channel length modulation effect – – Obtaining the parameters kn, VT0, and γ – ( ) ( )0 2 0)( 2 , 2 TGS n DTGS n satD VV k IVV k I −⋅=−⋅= FSBF TSBT V VVV φφ γ 22 )( 0 −+ − =
  35. 35. 35
  36. 36. 36 Measurement of parameters- λ • The voltage VGS is set to VT0+1 • The voltage VDS is chosen sufficiently large (VDS>VGS-VT0) that the transistor operates in the saturation mode, VDS1, VDS2 – ID(sat)=(kn/2)(VGS-VT0)2 (1+λVDS) • Since VGS=VT0+1  ID2/ID1=(1+λVDS2)/ (1+λVDS1) • Which can be used to calculate the channel length modulation coefficient λ • This is in fact equivalent to calculating the slope of the drain current versus drain voltage curve in the saturation region – The slope is λkn/2
  37. 37. 37
  38. 38. 38 Example 5
  39. 39. 39 MOSFET scaling and small-geometry effects • High density chip – The sizes of the transistors are as small as possible – The operational characteristics of MOS transistor will change with the reduction of its dimensions • There are two basic types of size-reduction strategies – Full scaling (constant-field scaling) – Constant-voltage scaling • A new generation of manufacturing technology replaces the previous one about – every two or three years – The down-scaling factor S about 1.2 to1.5 • The scaling of all dimensions by a factor of S>1 leads to the reduction of the area occupied by the transistor by a factor of S2
  40. 40. 40 Full scaling (constant-field scaling) ( )[ ] ( )[ ] ( ) ( ) sresistanceabdescapacitancparasiticvariousofreductionA improveddown time-chargeandup,-chargetheoffactorabydownscaledis unchangedvirtuallyremainingareaunitperThe scalingfulloffeaturesattractivemosttheofoneisndissipatiopowertheofreductiontsignificanThe 1 ndissipatiopowerThe 1 22 currentdrainmodesaturationThe 2 1 2 2 2 currentdrainmodelinearThe offactorabyscaledalsowilltheunchangedratioaspectThe C areaunitperecapacitancoxidegateThe densitydopingscaledby theaffectedtlysignificannotismobilitysurfacetheAssuming factorscalingsameby theally,proportiondownscaledbemustpotentialsallgoal,thisachieveTo 22 2 2 2 2 2 2 ' ' ox ⇒ =⋅⋅=⋅= =−⋅⋅ ⋅ =−⋅= =−⋅−⋅⋅⋅ ⋅ = −⋅−⋅⋅= ⇒ ⋅=⋅== SC itypower dens S P VI S VIP S I VV S kS VV k (sat)I S I VVVV S kS VVVV k (lin)I SkW/L CS t S t μ g DSD ' DS ' D ' D(sat) TGS n' T ' GS ' n' D D(lin) DSDSTGS n ' DS ' DS ' T ' GS ' n' D n ox ox ox ox ox n εε
  41. 41. 41
  42. 42. 42
  43. 43. 43 Constant-voltage scaling ( )[ ] ( )[ ] ( ) ( ) stress-overelectricalandbreakdown,oxiden,degradatiocarrierhotration,electromig densitypowerdensity,currentincreasingDisadv. s.constraintlevel-voltageexternaltheofbecause casespracticalmamyinscalingfulloverpreferredbemayscalingvoltage-constant,summarizedTo offactorabyincresaeddensitypowerThe ndissipatiopowerThe offactorabyincreaseddensitycurrentdrainThe 22 currentdrainmodesaturationThe 2 2 2 2 currentdrainmodelinearThe byincreasedalsoisparameteructancetranscondThe offactorabyincreasedisareaunitperecapacitancoxidegateThe relationsfield-chargethepreserveorder toinoffactorabyincreasedbemustdensitiesdopingThe unchanged.remainedvoltagesterminaltheandtagesupply volpowerThe .offactorabyreducedMOSFETaretheofdimensionsAll 3 3 22 2 2 2 ⇒ ⇒ ⋅=⋅⋅=⋅= ⋅=−⋅ ⋅ =−= ⋅=−⋅−⋅⋅ ⋅ = −⋅−⋅⋅= ⇒ S PSV)I(SVIP S (sat)ISVV kS VV k (sat)I (lin)ISVVVV kS VVVV k (lin)I S SC S S DSD ' DS ' D ' DTGS n' T ' GS ' n' D DDSDSTGS n ' DS ' DS ' T ' GS ' n' D ox
  44. 44. 44
  45. 45. 45 Short-channel effects • A MOS transistor is called a short-channel device – If its channel length is on the same order of magnitude as the depletion region thickness of the S and D junction – The effective channel length Leff ≈ S, D junction depth xj – Two physical phenomena arise from short-channel effects • The limitations imposed on electron drift characteristics in the channel – The lateral electric field Ey increased, vd reached saturation velocity – » No longer a quadratic function of VGS, virtually independent of the channel length DSAToxsatd L IsatdsatdsatD VCvWQvWdxxnqvWI eff ⋅⋅⋅=⋅⋅=⋅⋅⋅⋅= ∫ )( 0 )()()( )(
  46. 46. 46 ( ) ( )TGS no cGS Siox ox nono n VVyVV t Ex eff −⋅+ = −⋅ Θ + = ⋅Θ+ = η µ ε ε µµ µ 1)(11 )( The carrier velocity in the channel is also a function of Ex Influence the scattering of carriers in the surface The modification of the threshold voltage due to the shortening channel length
  47. 47. 47 Short-channel effects-modification of VT • The n+ drain and source diffusion regions in p-type substrate induce a significant amount of depletion charge – The long channel VT, overetimates the depletion charge support by the gate voltage – The bulk depletion region  asymmetric trapezoidal shape • A significant portion of the total depletion region charge is due the S and D junction depletion ( ) ( ) ( ) ( )                 −++         −+⋅⋅⋅⋅⋅⋅⋅=         −+⋅≅         −+⋅≅+−−+−= =⋅⋅−−+⋅⋅+ ++=+       ⋅ ⋅=+⋅ ⋅ ⋅ =⋅ ⋅ ⋅ = ⋅⋅⋅⋅⋅      + −−= = 1 2 11 2 1 2 22 1 1 2 1 1 2 12 022 ln 22 22 2 1 ΔV-V 0 222 222 222 2000 0 T0T00 j dS j dDj FASi ox T j dS jS j dD jdDjdDdmjjD dDjdDdmDjD DjdmdDj i AD DS A Si dD A Si dS FASi DS B T x x x x L x φNεq C ΔV x x xΔL x x xxxxxxxΔL xxxxΔLxΔL ΔLxxxx n NN q kT , φVφ Nq ε , xφ Nq ε x φNεq L ΔLΔL Q nnel)(short chaV
  48. 48. 48
  49. 49. 49
  50. 50. 50 ( ) ( ) ( ) ( )                 −++         −+⋅⋅⋅⋅⋅⋅⋅=         −+⋅≅         −+⋅≅+−−+−= =⋅⋅−−+⋅⋅+ ++=+       ⋅ ⋅=+⋅ ⋅ ⋅ =⋅ ⋅ ⋅ = ⋅⋅⋅⋅⋅      + −−= = 1 2 11 2 1 2 22 1 1 2 1 1 2 12 ,022 ln 22 Re,22 2 1 )(arg,ΔV-V 0 222 222 222 2000 0 T0T00 j dS j dDj FASi ox T j dS jS j dD jdDjdDdmjjD DdDjdDdmDjD DjdmdDj i AD DS A Si dD A Si dS FASi DS B T x x x x L x φNεq C ΔV x x xΔL x x xxxxxxxΔL ΔLSolvingForxxxxΔLxΔL ΔLxxxx n NN q kT , φVφ Nq ε , xφ Nq ε x gionDepthpletionjunctionDeφNεq L ΔLΔL Q lregiontrapizoidaeegionchDepletionrnnel)(short chaV
  51. 51. 51 Example 6 (1)
  52. 52. 52 Example 6 (2)
  53. 53. 53 Example 6 (3)
  54. 54. 54 Narrow-channel effect • Channel width W on the same order of magnitude as the maximum depletion region thickness xdm • The actual threshold voltage of such device is larger than that predicted by the conventional threshold voltage • Fringe depletion region under field oxide – arcscircular-quarterbymodeledregiondepletionfor 2 22 1 V VVchannel)narrow( T0 T0T00 π κ κ φε = ⋅ ⋅⋅=∆ ∆+= W x Nq C V dm FASi ox T
  55. 55. 55 Other limitations imposed by small-device geometries • The current flow in the channel are controlled by two dimensional electric field vector • Subthreshold conduction – Drain-induced barrier lowering (DIBL) – A nonzero drain current ID for VGS<VT0 – • Punch-through – The gate voltage loses its control upon the drain current, and the current rises sharply • Gate oxide thickness tox scaled to tox/S, is restricted by processing difficulties – Pinholes, oxide breakdown • Hot-carrier effect ( )DSGS r VBVA kT q kT q B cn D ee L nWxqD ldsubthreshoI ⋅+⋅ ⋅⋅≅ φ 0 )(
  56. 56. 56 MOSFET capacitances • L=LM-2LD – L: the actual channel length – LM: the mask length of the gate – LD: the gate-drain, the gate- source overlap • On the order of 0.1µm
  57. 57. 57 Oxide related capacitance(1) • The gate electrode overlap capacitance – CGD(overlap)=CoxWLD – CGS(overlap)=CoxWLD • With Cox=εox/tox – Both capacitance do not depend on the bias condition, they are voltage-independent • The capacitances result from the interaction between the gate voltage and the channel charge – Cut-off mode • Cgs=Cgd=0 • Cgb=CoxWL – Linear mode • Cgb=0 • Cgs≅Cgd ≅(1/2) CoxWL – Saturation mode • Cgb= Cgd =0 • Cgs≅(2/3) CoxWL
  58. 58. 58 Oxide related capacitance(2) • The sum of all three voltage-dependent (distributed) gate oxide capacitances (Cgb+Cgs+Cgd) – A minimum value of 0.66CoxWL, in saturation mode – A maximum value of CoxWL, in cut off and linear modes – For simple hand calculation • The three capacitances can be considered to be in parallel • A constant worst-case value of CoxW(L+2LD) can be used for the sum of MOSFET gate oxide capacitances
  59. 59. 59 Junction capacitance(1) ( ) ( ) ( ) ( ) ( ) ( )1020 12 0 0 0 1 0 2 2 00 1 0 1 1 0 2 2 00 1212 12 0 0 0 0 0 0 20 0 2 11 2 junctions-pnabruptofcasespecialFor the 11 1 1 asdefinedbecanecapacitancsignal-largeequivalentThe 1 2 areaunitperecapacitancjunctionbiaszeroThe tcoefficiengradingismparameterthe, 1 1 2 ecapacitancjunctionThe 2chargeregiondepletionThe lnpotentialin-builtThe 2 cknessregion thidepletionThe 2 1 VV VV K KCAC VV VV φCA C VV mVV CA (V)dVC VVVV )(VQ)(VQ ΔV ΔQ C φNN NNqε C φ V AC (V)C VφNN NNqε A dV dQ C Vφ NN NN qεAx NN NN qAQ n NN q kT φ Vφ NN NN q ε x eq eqjeq j eq mm j V V j jj eq DA DASi j m j j DA DASij j DA DA Sid DA DA j i DA DA DASi d −−−⋅ − −= ⋅⋅=       −−−⋅ − ⋅⋅⋅ −=               −−      −⋅ −⋅− ⋅⋅ −= − = − − == ⋅      + ⋅ ⋅ ⋅ =       − = − ⋅      + ⋅ ⋅ ⋅ ⋅== − + ⋅ ⋅⋅⋅=⋅      + ⋅ ⋅⋅=       ⋅ ⋅= − ⋅ + ⋅ ⋅ = −− ∫ φφ φ φφ φφ φ
  60. 60. 60
  61. 61. 61 ( ) ( ) ( ) ( ) ( ) ( )1020 12 0 0 0 1 0 2 2 00 1 0 1 1 0 2 2 00 1212 12 0 0 0 0 0 0 20 0 2 11 2 junctions-pnabruptofcasespecialFor the 11 1 1 asdefinedbecanecapacitancsignal-largeequivalentThe 1 2 areaunitperecapacitancjunctionbiaszeroThe tcoefficiengradingismparameterthe, 1 1 2 ecapacitancjunctionThe 2chargeregiondepletionThe lnpotentialin-builtThe 2 cknessregion thidepletionThe 2 1 VV VV K KCAC VV VV φCA C VV mVV CA (V)dVC VVVV )(VQ)(VQ ΔV ΔQ C φNN NNqε C φ V AC (V)C VφNN NNqε A dV dQ C Vφ NN NN qεAx NN NN qAQ n NN q kT φ Vφ NN NN q ε x eq eqjeq j eq mm j V V j jj eq DA DASi j m j j DA DASij j DA DA Sid DA DA j i DA DA DASi d −−−⋅ − −= ⋅⋅=         −−−⋅ − ⋅⋅⋅ −=               −−      −⋅ −⋅− ⋅⋅ −= − = − − == ⋅      + ⋅ ⋅ ⋅ =       − = − ⋅      + ⋅ ⋅ ⋅ ⋅== − + ⋅ ⋅⋅⋅=⋅      + ⋅ ⋅⋅=       ⋅ ⋅= − ⋅ + ⋅ ⋅ = −− ∫ φφ φ φφ φφ φ
  62. 62. 62 ( ) ( ) 0 0 0 0 0 0 20 0 1 2 areaunitperecapacitancjunctionbiaszeroThe tcoefficiengradingismparameterthe, 1 1 2 ecapacitancjunctionThe 2chargeregiondepletionThe lnpotentialin-builtThe 2 cknessregion thidepletionThe φNN NNqε C φ V AC (V)C VφNN NNqε A dV dQ C Vφ NN NN qεAx NN NN qAQ n NN q kT φ Vφ NN NN q ε x DA DASi j m j j DA DASij j DA DA Sid DA DA j i DA DA DASi d ⋅      + ⋅ ⋅ ⋅ =       − = − ⋅      + ⋅ ⋅ ⋅ ⋅== − + ⋅ ⋅⋅⋅=⋅      + ⋅ ⋅⋅=       ⋅ ⋅= − ⋅ + ⋅ ⋅ =
  63. 63. 63 ( ) ( ) ( ) ( )1020 12 0 0 0 1 0 2 2 00 1 0 1 1 0 2 2 00 1212 12 2 11 2 junctions-pnabruptofcasespecialFor the 11 1 1 asdefinedbecanecapacitancsignal-largeequivalentThe 2 1 VV VV K KCAC VV VV φCA C VV mVV CA (V)dVC VVVV )(VQ)(VQ ΔV ΔQ C eq eqjeq j eq mm j V V j jj eq −−−⋅ − −= ⋅⋅=         −−−⋅ − ⋅⋅⋅ −=               −−      −⋅ −⋅− ⋅⋅ −= − = − − == −− ∫ φφ φ φφ φφ φ
  64. 64. 64 Example 7
  65. 65. 65 Junction capacitance(2) ( ) eq(sw)jsweq(sw) eq(sw) swsw sw sweq jswjjsw swDA(sw) DA(sw)Si swj A(sw) A KCPC P C VV VV K xCC φNN NNqε C N N p ⋅⋅= −−−⋅ − −= ⋅= ⋅         + ⋅ ⋅ ⋅ = + becan)(perimeterlengthofsidewalla forecapacitancjunctionsignal-largeequivalentThe 2 factoreequivalencvoltagesidewallThe 1 2 asfoundbecanareaunitperecapacitancbias-zerothe ,bygivenisdensitydopingsidewalltheAssume densitydopingsubstratethan the densitydopinghigherawithimplant,stop-channelabysurroundedare regiondiffusiondrainorsourceMOSFETtypicalaofsidewallsThe 1020 12 0 )( 0 0 0 φφ φ
  66. 66. 66 Example 8 (1)
  67. 67. 67 Example 8 (2)

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