2. • A sequential circuit is consists of combinational logic,
feedback path and employs some memory elements
Feedback path
Sequential circuit= Combinational logic + Memory
Elements
Present state
Next state
3. • The memory element is a device which can
remember value indefinitely, or change value on
command from its inputs.
• The memory element also has a clock input which
provides timing for changing states.
• The feedback path is required for the circuit to
have memory.
4. • State changes are controlled by clocks.
A “clock” is a special circuit that sends electrical
pulses through a circuit.
• Clocks produce electrical waveforms in generally
some form of square wave
• Circuits can change state on the rising edge, falling
edge, or when the clock pulse reaches its highest
voltage.
5.
6. • are storage elements that operate with
signal levels (rather than signal transitions)
• useful for storing binary information and for
the design of asynchronous sequential
circuits
• are the building blocks of flip-flops
7. •The SR latch is a circuit with two
cross-coupled NOR gates or two
cross-coupled NAND gates,
•The two inputs are labeled S for set
and R for reset.
8.
9. • when Q = 1 and Q’ = 0, the latch is said to
be in the set state
• S=HIGH (and R=LOW)
R
S
Q’
Q
S R Q Q'
1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 invalid!
0
1
1
0
10. • The inputs must go back to their normal conditions
(S=0, R=0) before any changes occur
0
0
1
0
R
S
Q
Q'
S R Q Q'
1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 invalid!
11. 1
0
• When Q = 0 and Q’ = 1, it is in the
0
1
R
S
Q
Q'
S R Q Q'
1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 invalid!
reset state
• S=LOW (and R=HIGH)
12. • The inputs must go back to their normal conditions
(S=0, R=0) before any changes occur
R
S
Q
Q'
S R Q Q'
1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 invalid!
0
0
0
1
13. If both inputs HIGH a Q and Q' both
R
S
Q
Q'
S R Q Q'
1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 invalid!
1
1
0
0
LOW (invalid)!
14.
15. • when Q = 0 and Q’ = 1, the latch is said to
be in the set state
• R=LOW (and S=HIGH)
S
R
Q
Q'
S R Q Q'
1 0 0 1 initial
1 1 0 1 (afer S=1, R=0)
0 1 1 0
1 1 1 0 (after S=0, R=1)
0 0 1 1 invalid!
1
0
0
1
16. • The inputs must go back to their normal conditions
(S=1, R=1)before any changes occur
S
R
Q
Q'
S R Q Q'
1 0 0 1 initial
1 1 0 1 (afer S=1, R=0)
0 1 1 0
1 1 1 0 (after S=0, R=1)
0 0 1 1 invalid!
1
0
1
1
17. • When Q = 0 and Q’ = 1, it is in the
S
R
Q
Q'
S R Q Q'
1 0 0 1 initial
1 1 0 1 (afer S=1, R=0)
0 1 1 0
1 1 1 0 (after S=0, R=1)
0 0 1 1 invalid!
0
1
1
0
reset state
• R=LOW (and S=HIGH)
18. • The inputs must go back to their normal conditions
(S=1, R=1)before any changes occur
S
R
Q
Q'
S R Q Q'
1 0 0 1 initial
1 1 0 1 (afer S=1, R=0)
0 1 1 0
1 1 1 0 (after S=0, R=1)
0 0 1 1 invalid!
1
1
1
0
19. If both inputs LOW a Q and Q' both
S
R
Q
Q'
S R Q Q'
1 0 0 1 initial
1 1 0 1 (afer S=1, R=0)
0 1 1 0
1 1 1 0 (after S=0, R=1)
0 0 1 1 invalid!
0
1
0
1
LOW (invalid)!
20.
21.
22. • Ensure that inputs S and R are never equal to 1 at the
same time.
• has only two inputs: D (data) and En (enable)
23. When EN is HIGH,
D=HIGH latch is SET
D=LOW latch is RESET
Hence when EN is HIGH, Q ‘follows’ the D
(data) input.
Characteristic table:
EN D Q
1 0 0 Reset
1 1 1 Set
0 X Q No change
Editor's Notes
The figure shows a theoretical view of how sequential circuits are made up from combinational logic and some storage elements
Observations about sequential circuits from the diagram:
The "state" of the sequential circuit is stored in the memory elements. There are a finite number of states the circuit can be in.
The next state of the memory elements is a function of the current state and current inputs.
Output of the circuit is a function of the current state and current inputs.
A sequential logic circuit typically has some kind of memory element to hold the state of the circuit.
The memory element is a device which can remember value indefinitely, or change value on command from its inputs.
the whole idea is that in the memory, you’re going to be retaining certain states,
The memory element also has a clock input which provides timing for changing states.
To retain their state values, sequential circuits rely on feedback.
Feedback in digital circuits occurs when an output is looped back to the input.
A clock is an important part of a sequential circuit. It controls the timing of changes in a sequential circuit.
State changes occur in sequential circuits only when the clock ticks.
Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage.
Circuits that change state on the rising edge, or falling edge of the clock pulse are called edge-triggered.
Level-triggered circuits change state when the clock voltage reaches its highest or lowest level
Latches are very similar to flip-flops, but are not synchronous devices, and do not operate on clock edges as flip-flops do.
Also known as active-HIGH input SR Latch
The latch has two states
When output Q = 1 and Q’ = 0, the latch is said to be in the set state . When Q = 0 and Q’ = 1, it is in the reset state .
However,
when both inputs are equal to 1 at the same time, a condition in which both outputs are
equal to 0 (rather than be mutually complementary) occurs. If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or undefined state or a metastable state. Consequently, in practical applications, setting both inputs to 1 is forbidden.
The operation of the basic SR latch can be modified by providing an additional input signal that determines (controls) when the state of the latch can be changed by determining whether S and R (or S and R ) can affect the circuit.
In the figure . It consists of the basic SR latch and two additional NAND gates. The control input En acts as an enable signal for the other two inputs.
