Library Characterization Flow


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Provides an primitive overview for various aspects of Library characterization

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Library Characterization Flow

  1. 1. Library Characterization <br />Its Impact on Semiconductor Industry & the flow<br />Satish Kumar Grandhi<br />(<br />
  2. 2. Let’s start off on a Funny Note<br />Why Choose Library Characterization as a career ??<br />Very little manual effort, need only little extra intelligence<br />Effort – 30% , Enjoyment – 70% ; No need to work over weekends <br />Only one issue : Convergence (Kills u big time)<br />Double Edged Sword; Little Chance of firing . But, Very few players in this business, no great chances of jumping around .<br />Most Important ; It keeps your options wide open<br />Physical Design, STA<br />EDA Tool Development<br />Circuit Design<br />
  3. 3. Acknowledgements<br />Heart Felt Thanks to <br />Masamb Electronics, Anupam Kumar Sinha in specific<br />Naveen Kumar Kotha (LSI Bangalore), Rachit I. Kushalappa (TI, Bangalore) & Naresh ANNE (AMD USA)<br />Wiki, EDABoard & LTSPICE yahoo group<br />NANGATE for providing open source 45nm STD cell library package<br />All prof’s with US universities (You guys don’t hide your work in the internal repositories, hats off to you)<br />Collegues @ NXP, Cypress & ST MicroElectronics<br />Check out my weblink on Library Characterization for latest updated version of these slides & for more info<br />Speaker guarantees no originality in this work ; It is a mix of material accumulated from various sources<br />We are as dwarfs sitting on the shoulders of giants -- Sir Issac Newton<br />
  4. 4. Contents<br />Necessity & the Impact<br />Fundamental Terminology<br />Glancing Through .LIB <br />Characterization Methodology <br />Case Studies : Inverter & D-Flop<br />Advanced Topics<br />References<br />
  5. 5. Two Great Laws<br />Moore’s LawOn April 19, 1965 Moore predicted the most important law ever proposed in Semiconductors. <br />Amdahl's law states that the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used<br />Missing 3rd law, the NLDM law <br />How are these related ??<br />
  6. 6. How to Implement them ? <br />
  7. 7. Two Generic Flows<br />Reference : Allen Holberg, Gatech and Laker, Upenn Class Room Lectures<br />
  8. 8. INTEL Processor’s Growth<br />* All the predictions are based on wiki…could be approximate<br />
  9. 9. Characterization Terminology<br />
  10. 10. Input Slew & Output Load<br />Slew rate : Represents the maximum rate of change of signal<br />Output Load : Total amount of capacitance at the output node<br />
  11. 11. Timing - Combinational<br />Transition Delay Time a system needs to switch between two different stable states, when responding to a stable input signal<br />Propagation Delays Time it takes for the output signal to switch after the input signal has been applied.<br />
  12. 12. Timing – Sequential 1<br />Setup & Hold Minimum time the data signal has to be present at the input pin of a memory cell before/after the write signal arrives.<br />General Methodology employed : Binary Chop<br />
  13. 13. Timing - Sequential 2<br />Recovery / Removal Minimum time delay that has to maintained between an asynchronous clear/set signal and before/after the clock of the cell is triggered.<br />Method Used : Binary Chop<br />
  14. 14. Timing – Sequential 3<br />Minimum Pulse WidthMinimum width of control signal in order for the cell to detect it.<br />If the clock signal active period is smaller than this minimum time, you cannot be sure that the cell will have stored the input’s value properly.<br />
  15. 15. Timing Unateness<br />Positive Unate<br />Negative Unate<br />Non Unate<br />
  16. 16. Power – Short circuit<br />If a path exists from power supply to ground, it results in continuous flow of current and results in static power dissipation<br />CMOS Technology has neglible static power consumption (biggest advantage and reason as to why CMOS is so very popular).<br />
  17. 17. Power - Dynamic<br />Power dissipated during the charging and discharging of the output Load capacitance.<br />Pdyn =  CL * Vdd2 * f<br />
  18. 18. Power - Leakage<br />The power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor<br />Major Sources :<br />Sub threshold condition<br />Gate Leakage current<br />* Check out Reference6<br />
  19. 19. Wire Load Models<br />/* Wire load table */<br />  wire_load("ABC") {<br />    capacitance : 1.774000e-04;<br />    resistance : 3.571429e-03;<br />    area  : 7.559700e-02;<br />    slope : 5.000000;<br />    fanout_length( 1, 1.3207 );<br />    fanout_length( 2, 2.9813 );<br />    fanout_length( 3, 5.1135 );<br />    fanout_length( 4, 7.6639 );<br />    fanout_length( 5, 10.0334 );<br />    fanout_length( 6, 12.2296 );<br />    fanout_length( 8, 19.3185 );<br />  }  <br />No info on interconnect parasitic before Physical Design<br />Attempts to predict the capacitance and resistance of nets in the absence of placement and routing information<br />Excellent Paper : Steve Golson, "Resistance is Futile! Building Better Wireload Models"  (Link)<br />
  20. 20. Library Characterization Flow<br />
  21. 21. Methodology<br />* Prototype Copied from Liberty NCX manual<br />
  22. 22. Sensitization<br />Set of logic conditions leading to transition; This logic condition setup process is called sensitization.<br />In other words, it generates the stimulus at the cell input pins necessary to produce a simulation measurement of the desired characteristic, such as delay or slew.<br />No simulations performed, analytically derives the functionality of the cell from Boolean expressions, truth tables, state tables, and flip-flop latch groups defined in the input library or template files. <br />
  23. 23. Load Sharing Facility (LSF)<br />Goal : Give many users processes "fair share" of resources (CPU, memory , ….)<br />Commands : bjobs, bqueues, bhist, bkill, bswitch, bpause, bresume<br />
  24. 24. How Simulator Works ??<br />Input Setup Sanity Check<br />Generate .LIB (final masala)<br />Arc List for each Cell<br />Fetch the Results<br />Develop Sensitization Vector’s<br />Launch Them on LSF<br />Create Spice Deck for each case<br />
  25. 25. Capacitance Characterization<br />Buffer comparison methodcalculates by comparing the output slope of three identical reference buffers.<br />Charge calculation method monitors the total current (charge) flowing through each input pin and integrates it over a period of time<br />
  26. 26. Power Characterization<br />Calculates the current consumed and convert into power<br />Find paths from input pins to outputs, look for every valid pin combination of the cell and simulate it. <br />Plus, some input combinations don't change any output. But, results in power consumption<br />For example:<br />Clocks, sets, resets etc. that do not change the output because it already had the proper state<br />Input changes without a clock change<br />Also, Leakage power<br />
  27. 27. Case Study: Inverter & D-Flop <br />
  28. 28. .Measure (Spice Command)<br />Prints the results of specific user defined analyses<br />With this command you can measure rise and fall times, length of a pulse, delays, voltages, etc.<br />ELDO - .extract<br />Spectre – {export}???<br />
  29. 29. CS 1 : Inverter<br />ARCS : <br />IN  OUT<br />Measurements :<br />Rise, Fall<br />Sensitization Vectors<br />IN : 01, 10<br />OUT : 10, 01<br />
  30. 30. Cap Measurements<br />Power Measurements<br />
  31. 31. Timing Calculations<br />
  32. 32. Technology Impact<br />Simulated a 3 Input NAND gate (all inputs set to '1') using cadence GPDK180 & NANGATE's 45nm models<br />With shrinking gate length, the leakage current increases<br />Ref : ITRS Roadmap 2005<br />
  33. 33. CS 2 : D Flip Flop<br />Consider a Asynchronous flop with set & Reset pins.<br />Possible arcs to be characterized :<br />Clk -> Q (delay)<br />D -> Clk (setup & Hold)<br />Set/ Reset -> Clk (Recovery & Removal)<br />Power & cap characterization<br />(Each instance is a 3 input nand gate)<br />
  34. 34. Various Arcs in Scan Flop<br />( Snapshot from Reference 3 )<br />
  35. 35. Setup Analysis<br />** For Setup Time Analysis<br />VIN2 D 0 pwl 0 0 4.99995n 0 5.99995n 1.8 11n 1.8 12n 0 24n 0 24.9995n 0 25.9995n 1.8<br />.MEASURE TRAN setup_time<br />**** Constrained pin is falling<br />+ trig V(D) val = 0.9 rise= 1<br />**** Related pin is rising<br />+ targ V(CLK) val = 0.9 rise = 2<br />Setup time=1.955e-008 FROM 5.49995e-009 TO 2.505e-008<br />
  36. 36. From STA Point of View<br />--Very primitive, will improve in the days to come<br />
  37. 37. CAP on a net<br />Total o/p node cap = Sum of { all input caps of driven cells + wire Capacitance + O/p Node Capacitance }<br />
  38. 38. Delay Calculation<br />UINV0 (NET0, I2)<br />UAND1 (O1, I1, NET0)<br />UNOR2(O2, O1, NET0)<br />
  39. 39. Advanced Topics<br />
  40. 40. State Dependent Delays<br />Timing arcs depend on the state of pins other than Input & Output<br />Multiple timing models are used to describe ‘a’ arc<br />Consider a 2 I/P XOR Gate<br />timing () { <br />related_pin : "A"; <br />when : "B"; <br />sdf_cond : "(B == 1'b1)";<br />timing_sense : negative_unate;<br />cell_fall(Timing_data_X1) {<br />values ("0.012959,0.015005,……..<br />……………………………………………<br />timing () { <br />related_pin : "A"; <br />when : "!B"; <br />sdf_cond : "(B == 1'b0)";<br />timing_sense : positive_unate;<br />cell_fall(Timing_data_X1) { <br />values ("0.036818,0.038956, ……..<br />……………………………………………<br />
  41. 41. Negative Delays<br />A large input slope and a cell that reacts either very quickly <br />
  42. 42. Load Cap Characterization<br />When output slew transition = Max_Slew(max_tout), the output loading = Max_load<br />
  43. 43. Tri State Delay Measurement<br />Cannot be measured using conventional voltage levels<br />Measured by looking at the current through the output pin.<br />Test Equipment consists of <br />Current detector on the output of the tristate cell <br />Pull-up and pull-down resistors that can be switched on/off independently<br />
  44. 44. Measuring Normal-tri state delays<br />Switch on both pull-up and pull-down resistors; produce a short current flows at the output pin. <br />When the cell enters tristate mode the output pin will be isolated from the rest of the cell, the path from supply to output cut, and current through the output pin will stop.<br />Current monitoring device detects when the value goes below a certain threshold (pre-defined) which is the required delay.<br />
  45. 45. Tri State to High state delays<br />Activate only the pull-down resistor<br />Switch off the pull-down resistor <br />Push the Circuit into Tri State Mode<br />Enable the cell so that output rise ‘s<br />
  46. 46. References<br />Sung Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits-Analysis and Design", Tata McGraw Hill, Third Edition, New Delhi, 2003<br />J. Bhasker & RakeshChadha, “Static Timing Analysis for Nanometer Designs: A Practical Approach”<br />Jan M. Rabaey, AnanthaChandrakasan, and BorivojeNikolic, “Digital Integrated Circuits: A Design Perspective”<br />RACHITH I. KUSHALAPPA, "AutoLibGen : An open source tool for automation of Standard Cell Library characterization for VDSM designs", M.E Thesis, NITK Surathkal, 2008<br />NARESH ANNE, "Design and Characterization of a standard cell library for the freePDK 45 process ", M.S Thesis, Oklahoma State University, 2010 (link)<br />
  47. 47. References….<br />HSpice Simulation and Analysis Users Guide, Version Y-2006.09, Sep 2006<br />Synopsys NCX User guide, Version B-2008.12, December 2008<br />An Excellent Lecture on Leakage power & possible reduction Techniques by R. Saleh, Uni of British Columbia (Link)<br />Nangate 45nm Open Cell Library (link)<br />Excellent Tutorial on HSPICE (Link)<br />LTSPICE Yahoo Group (Link)<br />Last, but not the least, extensive knowledge I gained by interacting with Library char teams @ NXP, Cypress & ST microelectronics which can’t be put in words<br />