directCell - Cell/B.E. tightly coupled via PCI Express


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directCell - Cell/B.E. tightly coupled via PCI Express

  1. 1. Heiko J Schick – IBM Deutschland R&D GmbH<br />November 2010<br />directCellCell/B.E. tightly coupled via PCI Express<br />
  2. 2. Agenda<br />Section 1: directCell<br />Section 2: Building Blocks<br />Section 3: Summary<br />Section 4: PCI Express Gen 3<br />2<br />
  3. 3. Terminology<br />An inline accelerator  is an accelerator that runs sequentially with the main compute engine.<br />A core accelerator  is a mechanism that accelerates the performance of a single core. A core may run multiple hardware threads as in an SMT implementation.<br />A chip accelerator  is an off-chip mechanism that boosts the performance of the primary compute chip. Graphics accelerators are typically of this type.<br />A system accelerator  is a network-attached appliance that boosts the performance of a primary multinode system. Azul is an example of a system accelerator<br />3<br />Section 1: directCell<br />
  4. 4. 4<br />Remote Control<br />Section 1: directCell<br />Our goal is to remotely control a chip accelerator via a device driver based on the primary compute chip. The chip accelerator does not run an operating system, but merely a firmware-based bare metal support library to facilitate the host based device driver.<br />Requirements<br />Operation (e.g. start and stop acceleration)<br />Memory Mapped I/O (e.g. Cell Broadband Architecture)<br />Special Instruction<br />Interrupts<br />Memory<br />Compatibility<br />Bus / Interconnect (e.g. PCI Express, PCI Express Endpoint)<br />
  5. 5. What is tightly coupled?<br />Distributed systems are state of the art<br />Tightly Coupled: Usage as a device rather than a system<br />Completely integrated into the host&apos;s global address space<br />I/O attached<br />Commonly referred to as a “hybrid”<br />OS-less, Controlled by host<br />Driven by interactive workloads<br />Example: A button is pressed, etc<br />Pluggable into existing form factors<br />5<br />Section 1: directCell<br />
  6. 6. Why tightly coupled?<br />Customers want to purchase applied acceleration<br />Classic appliance box will be deprecated by modular and hybrid approaches<br />Deployment and serviceability<br />A system needs to be installed and administered<br />Nobody is happy with accelerators that has to be program<br />Ship working appliance kernels<br />Software involvement and required<br />6<br />Section 1: directCell<br />
  7. 7. PCI Express Features<br />Computer expansion card interface format<br />Replacement for PCI, PCI-X and AGP as industry standard for PCs (Workstation and Server).<br />Serial Interconnect<br />Based on differential signals with 4 wires per lane<br />Each lane transmits 250 MB/s per direction <br />Up to 32 lane per link provides 4 GB/s per direction<br />Low Latency<br />Memory-mapped IO (MMIO) and direct memory access (DMA) are key concepts<br />7<br />Section 1: directCell<br />
  8. 8. Cell/B.E. Accelerator via PCI Express<br />Connect Cell/B.E. System as PCI Express device to a host system<br />Operating Systems runs only on host system (e.g. Linux, Windows)<br />Main application runs on host system<br />Compute intensive tasks will run as threads on SPEs<br />Using the same Cell/B.E. programming models as for non-hybrid systems.<br />Three level memory hierarchy instead of two level.<br />Cell/B.E. processor does not run any operation systems<br />MMIO and DMA used as access methods in both directions <br />8<br />Section 1: directCell<br />
  9. 9. PCI Express Cabling Products<br />9<br />Section 1: directCell<br />
  10. 10. Cell/B.E. Accelerator System<br />10<br />Section 1: directCell<br />Application<br />Main Thread<br />SPU Threads<br />SPU Tasks<br />Operating system<br />SPE<br />PPE<br />SPE<br />SPU<br />Core<br />SPU<br />Local Store<br />LS<br />Execution<br />Units<br />Local Store<br />LS<br />Execution<br />Units<br />MFC<br />MFC<br />L2<br />DMA <br />MMIO<br />Registers<br />DMA <br />MMIO<br />Registers<br />EIB<br />CELL/B.E.<br />Memory<br />Southbridge<br />DMAEngine<br />
  11. 11. Cell/B.E. Accelerator System<br />11<br />Section 1: directCell<br />Application<br />Main Thread<br />SPU Threads<br />Application<br />Main Thread<br />SPU Tasks<br />Operating system<br />Operating System<br />SPE<br />PPE<br />SPE<br />Host Processor<br />Host<br />Memory<br />SPU<br />Core<br />SPU<br />Core<br />Local Store<br />LS<br />Execution<br />Units<br />Local Store<br />LS<br />Execution<br />Units<br />MFC<br />MFC<br />L2<br />L2<br />DMA <br />MMIO<br />Registers<br />DMA <br />MMIO<br />Registers<br />EIB<br />CELL/B.E.<br />Memory<br />Southbridge<br />Southbridge<br />PCI Express Link<br />DMAEngine<br />
  12. 12. Building Block #1: Interconnect<br />Currently PCI Express support is included in many front office systems, hence most accelerator innovation will take place via PCI Express.<br />Intel&apos;s QPI & PCI Express convergence (core i5/i7) drives a strong movement to make I/O a native subset of the front-side bus.<br />PCI Express EP support for modern processors is the only real option for tightly coupled interconnects.<br />PCI Express has bifurcation support and hot plug support.<br />Current ECNs (ATS, TLP Hints, Atomic Ops) must be included in those designs!<br />12<br />Section 2: Building Blocks<br />
  13. 13. Building Block #2: Addressing (1)<br />Section 2: Building Blocks<br />Integration on the Bus Level<br />Host BIOS or firmware maps accelerators via PCI Express BARs:<br />Increase BAR size in EP designs<br />Resizable BAR ECN<br />Bus level integration scales well:<br />264 = 16 Exabyte = 16 K Petabyte<br />Entire SOCs clusters can be mapped into host<br />13<br />
  14. 14. Building Block #2: Addressing (2)<br />Section 2: Building Blocks<br />Inbound Address Translation<br />PIM / POM, IOMMUs, etc.<br />Switch-based<br />PCIe ATS Specification<br />PCIe Address Translation Services<br />Allow EP virtual to real address translation for DMA:<br />Application provides VA pointer to EP. <br />Host uses EP VA pointer to program it.<br />Userspace DMA Problem<br />Buffers on accelerator and host need to be pinned for async DMA transfers.<br />Kernel involvement should be minimal.<br />Linux UIO framework<br />HugeTLBfs is needed.<br />Windows UMDF<br />Large Pages is needed.<br />14<br />
  15. 15. Building Block #3: Run-time Control<br />Minimal software on accelerator<br />Device driver is running on host system<br />Include DMA engine(s) on accelerator<br />Control Mechanisms<br />MMIO<br />Can easily be mapped as VFS -&gt; UIO.<br />PCIe core of acc should be able to map entire MMIO range.<br />Special instructions<br />Clumsy to map as virtual file system.<br />Expose to userspace as system call or IOCTL.<br />Fixed length of parameter area must be made user accessible.<br />PCI Express core of accelerator should be able to dispatch special instruction to every unit in the accelerator.<br />Include helper registers, scratchpads, doorbells and ring buffers<br />15<br />Section 2: Building Blocks<br />
  16. 16. directCell Operation<br />16<br />Section 2: Building Blocks<br />SPU Threads<br />Application<br />Main Thread<br />SPU Tasks<br />Operating System<br />4<br />4<br />1<br />SPE<br />PPE<br />SPE<br />Host Processor<br />Host<br />Memory<br />SPU<br />Core<br />SPU<br />Core<br />Local Store<br />LS<br />Execution<br />Units<br />Local Store<br />LS<br />Execution<br />Units<br />MFC<br />MFC<br />L2<br />L2<br />DMA <br />MMIO<br />Registers<br />DMA <br />MMIO<br />Registers<br />6<br />3<br />EIB<br />CELL/B.E.<br />Memory<br />5<br />5<br />2<br />2<br />Southbridge<br />Southbridge<br />PCI Express Link<br />DMAEngine<br />
  17. 17. Prototype<br />Concept validation<br />HS21 Intel Xeon Blade connected to QS2x Cell/B.E. Blade via PCI Express 4x .<br />Special firmware on QS2x Cell/B.E. Blade to set PCI connector as endpoint.<br />Microsoft Windows as OS on HS21 blade.<br />Windows device driver, enabling user space access to QS2x.<br />Working and verified<br />DMA transfer from and to Cell/B.E. Memory from Windows application.<br />DMA transfer from and to Local Store from Windows application.<br />Access to Cell/B.E. MMIO registers.<br />Start of SPE thread from Windows (thread context is not preserved)‏.<br />SPE DMA to host memory via PCI Express.<br />Memory management code .<br />User libs on Windows to abstract Cell/B.E. usage (compatible to libspe )‏.<br />SPE Context save and restore (needed for proper multi thread execution)‏.<br />17<br />Section 3: Summary<br />
  18. 18. Project Review<br />Technology study proposed to target new application domains & markets<br />Use Cell as an acceleration device.<br />All system management done from host system (GPGPU-like accelerator)‏.<br />Enables Cell on Wintel platforms <br />Cell/B.E. Systems has no dependency on OS.<br />Compute intensive tasks will run as threads on SPEs.<br />Use MMIO and DMA operations via PCI Express to reach any memory-mapped resources of the Cell/B.E. System from the host, and vice versa.<br />Exhibits a new Runtime model for Processors<br />Show that a processor designed for standalone operation can be fully integrated into another host system.<br />18<br />Section 3: Summary<br />
  19. 19. New Features<br />Atomic Operations<br />TLP Processing Hints<br />TLP Prefix<br />Resizable BAR<br />Dynamic Power Allocation<br />Latency Tolerance Reporting<br />Multicast<br />Internal Error Reporting<br />Alternative Routing-ID Interpretation<br />Extended Tag Enable Default<br />Single Root I/O Virtualization<br />Multi Root I/O Virtualization<br />Address Translation Services<br />19<br />Section 4: PCI Express Gen 3<br />
  20. 20. 20<br />Thank you very much for your attention.<br />
  21. 21. 21<br />Atomic Operations<br />This optional normative ECN defines 3 new PCIe transactions, each of which carries out a specific Atomic Operation (“AtomicOp”) on a target location in Memory Space. <br />The 3 AtomicOps are <br />FetchAdd (Fetch and Add)<br />Swap (Unconditional Swap)<br />CAS (Compare and Swap). <br />Direct support for the 3 chosen AtomicOps over PCIe enables easier migration of existing highperformance SMP applications to systems that use PCIe as the interconnect to tightly-coupled accelerators, co-processors, or GP-GPUs.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Atomic Operations ECN<br />
  22. 22. 22<br />TLP Processing Hints<br />This optional normative ECR defines a mechanism by which a Requester can provide hints on a per transaction basis to facilitate optimized processing of transactions that target Memory Space. <br />The architected mechanisms may be used to enable association of system processing resources (e.g. caches) with the processing of Requests from specific Functions or enable optimized system specific (e.g. system interconnect and Memory) processing of Requests.<br />Providing such information enables the Root Complex and Endpoint to optimize handling of Requests by differentiating data likely to be reused soon from bulk flows that could monopolize system resources.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Processing Hints ECN<br />
  23. 23. 23<br />TLP Prefix<br />Emerging usage model trends indicate a requirement for increase in header size fields to provide additional information than what can be accommodated in currently defined TLP header sizes. The TLP Prefix mechanism extends the header size by adding DWORDS to the front of headers that carry additional information.<br />The TLP Prefix mechanism provides architectural headroom for PCIe headers to grow in the future. Switches and Switch related software can be built that are transparent to the encoding of future End-End TLPs. <br />The End-End TLP Prefix mechanism defines rules for routing elements to route TLPs containing End-End TLP Prefixes without requiring the routing element logic to explicitly support any specific End-End TLP Prefix encoding(s).<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, TLP Prefix ECN<br />
  24. 24. 24<br />Resizable BAR<br />This optional ECN adds a capability for Functions with BARs to report various options for sizes of their memory mapped resources that will operate properly. Also added is an ability for software to program the size to configure the BAR to.<br />The Resizable BAR Capability allows system software to allocate all resources in systems where the total amount of resources requesting allocation plus the amount of installed system memory is larger than the supported address space.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Resizable BAR ECN<br />
  25. 25. 25<br />Dynamic Power Allocation<br />DPA (Dynamic Power Allocation) extends existing PCIe device power management to provide active (D0) device power management substates for appropriate devices, while comprehending existing PCIe PM Capabilities including PCI-PM and Power Budgeting.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Dynamic Power Allocation ECN<br />
  26. 26. 26<br />Latency Tolerance Reporting<br />This ECR proposes to add a new mechanism for Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex such that central platform resources (such as main memory, RC internal interconnects, snoop resources, and other resources associated with the RC) can be power managed without impacting Endpoint functionality and performance.<br />Current platform Power Management (PM) policies guesstimate when devices are idle (e.g. using inactivity timers). Guessing wrong can cause performance issues, or even hardware failures. In the worst case, users/admins will disable PM to allow functionality at the cost of increased platform power consumption.<br />This ECR impacts Endpoint devices, RCs and Switches that choose to implement the new optional feature.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Latency Tolerance Reporting ECN<br />
  27. 27. 27<br />Multicast<br />This optional normative ECN adds Multicast functionality to PCI Express by means of an Extended Capability structure for applicable Functions in Root Complexes, Switches, and components with Endpoints. <br />The Capability structure defines how Multicast TLPs are identified and routed. It also provides means for checking and enforcing send permission with Function-level granularity. The ECN identifies Multicast errors and adds an MC Blocked TLP error to AER for reporting those errors.<br />Multicast allows a single Posted Request TLP sent from a source to be distributed to multiple recipients, resulting in a very high performance gain when applicable.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Multicast ECN<br />
  28. 28. 28<br />Internal Error Reporting<br />PCI Express (PCIe) defines error signaling and logging mechanisms for errors that occur on a PCIe interface and for errors that occur on behalf of transactions initiated on PCIe. It does not define error signaling and logging mechanisms for errors that occur within a component or are unrelated to a particular PCIe transaction.<br />This ECN defines optional error signaling and logging mechanisms for all components except PCIe to PCI/PCI-X Bridges (i.e., Switches, Root Complexes, and Endpoints) to report internal errors that are associated with a PCI Express interface. Errors that occur within components but are not associated with PCI Express remain outside the scope of the specification.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Internal Error Reporting ECN<br />
  29. 29. 29<br />Alternative Routing-ID Interpretation<br />For virtualized and non-virtualized environments, a number of PCI-SIG member companies have requested that the current constraints on number of Functions allowed per multi-Function Device be increased to accommodate the needs of next generation I/O implementations. <br />This ECR specifies a new method to interpret the Device Number and Function Number fields within Routing IDs, Requester IDs, and Completer IDs, thereby increasing the number of Functions that can be supported by a single Device.<br />Alternative Routing-ID Interpretation (ARI) enables next generation I/O implementations to support an increased number of concurrent users of a multi-Function device while providing the same level of isolation and controls found in existing implementations.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Alternative Routing-ID Interpretation ECN<br />
  30. 30. 30<br />Extended Tag Enable Default<br />The change allows a Function to use Extended Tag fields (256 unique tag values) by default; this is done by allowing the Extended Tag Enable control field to be set by default.<br />The obligatory 32 tags provided by PCIe per Function are not sufficient to meet the throughput and requirements of emerging applications. Extended tags allow up to 256 concurrent requests, but such capability is not enabled by default in PCIe.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Extended Tag Enable Default ECN<br />
  31. 31. 31<br />Single Root I/O Virtualization<br />The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology.<br />Within the industry, significant effort has been expended to increase the effective hardware resource utilization (i.e., application execution) through the use of virtualization technology. <br />The Single Root I/O Virtualization and Sharing Specification (SR-IOV) defines extensions to the PCI Express (PCIe) specification suite to enable multiple System Images (SI) to share PCI hardware resources.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Single Root I/O Virtualization Specification<br />
  32. 32. 32<br />Multi Root I/O Virtualization<br />Section 4: PCI Express Gen 3<br />The specification is focused on multi-root topologies; e.g., a server blade enclosure that uses a PCI Express® Switch-based topology to connect server blades to PCI Express Devices or PCI Express to-PCI Bridges and enable the leaf Devices to be serially or simultaneously shared by one or more System Images (SI). <br />Unlike the Single Root IOV environment, independent SI may execute on disparate processing components such as independent server blades.<br />The Multi-Root I/O Virtualization (MR-IOV) specification defines extensions to the PCI Express (PCIe) specification suite to enable multiple non-coherent Root Complexes (RCs) to share PCI hardware resources.<br />Source: PCI-SIG, Multi Root I/O Virtualization Specification<br />
  33. 33. 33<br />Address Translation Services<br />This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device.<br />The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure.<br />Section 4: PCI Express Gen 3<br />Source: PCI-SIG, Address Translation Services Specification<br />
  34. 34. 34<br />Disclaimer<br />IBM®, DB2®, MVS/ESA, AIX®, S/390®, AS/400®, OS/390®, OS/400®, iSeries, pSeries, xSeries, zSeries, z/OS, AFP, Intelligent Miner, WebSphere®, Netfinity®, Tivoli®, Informix und Informix® Dynamic ServerTM, IBM, BladeCenter and POWER and others are trademarks of the IBM Corporation in US and/or other countries.<br />Cell Broadband Engine is a trademark of Sony Computer Entertainment, Inc. in the United States, other countries, or both and is used under license there from. Linux is a trademark of Linus Torvalds in the United States, other countries or both. <br />Other company, product, or service names may be trademarks or service marks of others. The information and materials are provided on an &quot;as is&quot; basis and are subject to change.<br />
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