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# Digital 1 8

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Basics of digital electronics.

Basics of digital electronics.

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### Transcript

• 1. Chapter 1 Number System and Codes
• 2. Chapter Objectives
• Understand the number system used in Digital Circuits
• Understand the types of complements:
• 1’s complement
• 2’s complement
• 9’s complement
• 10’s complement
• Understand the types of codes in digital systems
• 3. Number System
• Number system is used to represent the numbers.
• The different types of number systems are:
• Decimal number
• Binary number
• Octal numbers
• 4. Decimal Number
• It uses digits from 0 to 9 for representing the numbers.
• It is represented with base 10.
• A decimal number can be represented using positional weights.
• Example:
• (198) 10 = 1 X 10 2 + 9 X 10 1 + 8 X 10 0
• 5. Binary Number
• It consists of only two digits, 0 and 1.
• It is represented with base 2.
• A binary number can be represented using positional weights.
• Example:
• (198) 10 = (11000110) 2
• = 1 X 2 7 + 1 X 2 6 + 0 X 2 5 + 0 X 2 4 + 0 X 2 3 + 1 X 2 2 + 1 X 2 1 + 0 X 2 0
• = 128 + 64 + 0 + 0 + 0 + 4 + 2 + 0
• = 198
• 6. Octal Number
• It uses digits from 0 to 7 for representing the numbers.
• It is represented with base 8.
• An octal number can be represented using positional weights.
• Example:
• (237) 8 = 2 X 8 2 + 3 X 8 1 + 7 X 8 0
• = 2 X 64 + 3 X 8 + 7 X 1
• = 128 + 24 + 7
• = (159) 10
• 7. Hexadecimal Number
• It uses 16 symbols, 0 to 9 and A to F for representing the numbers.
• It is represented with base 16.
• A hexadecimal number can be represented by using positional weights.
• Example:
• A3BH = (A3B) 16 = A X 16 2 + 3 X 16 1 + B X 16 0
• = 10 X 16 2 + 3 X 16 1 + 11 X 16 0
• = 2560 + 48 + 11
• = (2619) 10
• 8. Arithmetic Operations
• Arithmetic operations are performed in arithmetic unit of the digital systems by using binary numbers.
• The various types of arithmetic operations are:
• Binary subtraction
• Binary multiplication
• Binary division
• 9. Complements
• Complements are the binary representation of negative numbers in digital systems.
• The various types of complements are:
• 1’s complement: It is obtained by changing all 0’s to 1’s and all 1’s to 0’s, of a binary number.
• 2’s complement: It is obtained by adding 1 to the 1’s complement.
• 9’s complement: It is obtained by subtracting each digit in the number by 9.
• 10’s complement: It is obtained by adding 1 to the 9’s complement.
• 10. Binary Coded Decimal
• Binary Coded Decimal (BCD) is the combination of four digits, 8241, which represent the binary numbers.
• Example:
• BCD equivalent of 1 is 0001
• BCD equivalent of 2 is 0010
• BCD equivalent of 5 is 0101
• BCD equivalent of 9 is 1001
• 11. Codes
• Code is the symbolic representation of discrete information, which can be represented in the form of numbers and letters.
• Codes are classified in five groups:
• Weighted binary codes: These codes follow the positional weighting principle in which the position of the numbers represent the weight. The different types of weighted codes are:
• 8421 code
• 2421 code
• Reflective code
• Sequential code
• 12. Codes
• Non-weighted codes: These codes are not positionally weighted. Each position within the binary number is not assigned a fixed value. The different types of non-weighted codes are:
• Excess-3 code
• Gray code
• Error detecting codes: These codes are used to detect errors in the decimal numbers. The different types of error detecting codes are:
• Check sum
• Parity check
• 13. Codes
• Error correcting codes: These codes are used to correct the errors in the decimal numbers. The different types of error correcting codes are:
• Hamming codes
• Alphanumeric codes: These codes represent numbers, letters and special symbols. The different types of alphanumeric codes are:
• ASCII codes
• EBCDIC code
• Hollerith code
• 14. Chapter 2 Boolean Algebra and Minimization Techniques
• 15. Chapter Objectives
• Understand the concept of Boolean algebra
• Understand the logic operations available in Boolean algebra
• Understand the basic laws of Boolean algebra
• Understand the DeMorgan’s theorems and Karnaugh map technique
• 16. Boolean Algebra
• Mathematician George Boole defined Boolean algebra as the technique, which provides the rules for carrying out the logical operations.
• The logical operations available in Boolean algebra are:
• Logical AND operation: It is given as Y = A.B for two Boolean variables A and B. The values of AND operation for different values of A and B are:
• If A=0,B=0 then A.B = 0
• If A=1,B=0 then A.B = 0
• If A=0,B=1 then A.B = 0
• If A=1,B=1 then A.B = 1
• 17. Boolean Algebra(contd..)
• Logical OR operation: It is given as Y=A+B. The values of OR operation for different values of A and B are:
• If A=0, B=0 then A+B = 0
• If A=1, B=0 then A+B = 1
• If A=0, B=1 then A+B = 1
• If A=1, B=1 then A+B = 1
• Logical complementation operation: It is also known as the NOT operation and it converts the logical 1 to 0 and logical 0 to 1.
• If A is a Boolean variable, then the complement of A is represented by A* or A′.
• Alternatively, a bar over the variable is used to represent the complement of the variable.
• 18. Basic Laws of Boolean Algebra
• The basic laws of Boolean algebra are used to provide mathematical expressions for logical operations.
• The Boolean rules define only two variables, binary 1 and binary 0. The basic rules of Boolean algebra are:
• 0 + 0 = 0
• 0 + 1 = 1
• 1 + 0 = 1
• 1 + 1 = 1
• Boolean multiplication
• 0.0 = 0
• 0.1 = 0
• 1.0 = 0
• 1.1 = 1
• 19. Properties of Boolean Algebra
• The properties of Boolean algebra depend on the following operators:
• Two binary operators denoted by the symbols ‘+’ and ‘.’
• One unary operator denoted by either the bar ( ¯ ) symbol or prime ( ') symbol
• The various properties of Boolean algebra are:
• Commutative property : The order of a Boolean operation conducted on the variables makes no difference on the result. For example:
• Boolean addition is commutative, i.e. A+B = B+A
• Boolean multiplication is commutative, i.e. A.B = B.A
• 20. Properties of Boolean Algebra (Contd..)
• Associative property : A Boolean operation conducted on several variables provides the same result irrespective of their grouping. For example:
• Boolean addition is associative. It is represented as:
• A+(B+C) = (A+B)+C
• Boolean multiplication is associative. It is represented as:
• A.(B.C) = (A.B).C
• Distributive Property : Boolean algebra is distributive for both addition and multiplication operations.
• Boolean addition is distributive over the Boolean multiplication. It is represented as:
• A+B.C= (A+B).(A+C)
• Boolean multiplication is distributive over the Boolean addition. It is represented as:
• A.(B+C)= A.B+A.C
• 21. DeMorgan’s Theorems
• According to DeMorgan’s first theorem, the complement of the product of two binary variables is equal to the sum of the complements of two binary variables.
• It can be stated as:
• (AB) * = A * + B *
• According to DeMorgan’s second theorem, the complement of the sum of the two binary variables is equal to the product of the complements of two binary variables.
• It can be stated as:
• (A + B) * = A *. B *
• 22. Sum of Products and Product of Sums
• Sum of Products (SOP) and Product of Sums (POS) are the logical variables that are used to express logical functions.
• SOP : It is the logical sum of two or more logical product term. Basically, it is an OR operation of AND operated variables. For example:
• Y = AB+BC+AC
• POS : It is the logical product of two or more logical sum terms. Basically, it is an AND operation of OR operated variables. For example:
• Y = (A+B)(B+C)(A+C)
• 23. Karnaugh Map
• Karnaugh map is a systematic method for simplifying and manipulating switching expressions.
• It is used to represent the information contained in a truth table or the information available in the form of POS or SOP. The characteristics of a K-map are:
• In an n-variable K-map, there are 2 n cells and each cell matched to one combination of n variables.
• In an n-variable K-map, a collection of 2 m cells and each adjacent to m cells is known as a group.This group can be expressed by a product containing n-m variables where n is the number of variables in the K-map.
• 24. Chapter 3 Logic Gates
• 25. Chapter Objectives
• Understand the basic concepts of logic circuits
• Understand the types of basic logic gates
• Understand the two types of universal gates
• Understand the types of logic,which are:
• Positive logic
• Negative logic
• Mixed logic
• 26. Basic Concepts of Logic Circuits
• Logic circuit consists of three elements, which are:
• Input variables : The input variables are the inputs to the logic circuits, which are represented by 1 and 0. The input 1 implies the high voltage (High) or +5V and input 0 implies the low voltage (Low) or 0V.
• Output variables : The output variables are the resultant outputs of the two input variables. The resultant output depends upon the type of logic gate that is being used.
• Logic gate : A logic gate is an electronic circuit that has two inputs and one output. At any instant, every input is in one of the two binary conditions such as 0 and 1.
• 27. Types of Logic Gates
• The following are the types of the logic gates used in logic circuits:
• Basic logic gates
• OR gate
• AND gate
• NOT gate
• Universal logic gates
• NAND gate
• NOR gate
• 28. OR Gate
• The OR gate is used to represent the addition operation between the two inputs A and B.
• Output of the operation is represented by Y=A+B
• Output of the OR Gate is always:
• High or 1 if any of the input is High or 1
• Low or 0 if BOTH the inputs are Low or 0
A B Y=A+B
• 29. AND Gate
• The AND gate is used to represent the logical multiplication operation between the two inputs A and B.
• Output of AND operation is represented by Y = A . B
• Output of the AND Gate is always:
• High or 1 if both the inputs are High or 1
• Low or 0 if any of the input is Low or 0
A B Y=A . B
• 30. Not Gate
• The NOT gate is used to represent the logical complementation operation.
• If A is the input to NOT gate then Y i.e. output of NOT gate is represented by Y = A * where A * is the complement of A.
• Output of the NOT gate is always:
• High or 1 if the input is Low or 0
• Low or 0 if the input is High or 1
A Y=A*
• 31. NAND Gate
• The NAND gate is used to represent the contraction of NOT-AND gates.
• If A and B are two inputs then its output is represented by Y = (A . B) *
• Output of the NAND Gate is always:
• High or 1 if one or both of the inputs are low or 0
• Low or 0 if BOTH the inputs are high or 1
A B Y=(AB) *
• 32. NOR Gate
• NOR gate is used to represent the contraction of NOT-OR gates.
• If NOR gate has two inputs A and B then its output is represented by Y = (A+B) *
• Output of the NOR gate is always:
• High or 1 if both the inputs are low or 0
• Low or 0 if any one or both the inputs are high or 1
A B Y=(A+B) *
• 33. Universal Gates
• The NAND or NOR gates are known as universal gates. These gates are used to implement any gate like AND,OR and NOT gates.
• The following two gates are also used in logic circuits:
• Exclusive-OR (Ex-OR) gate : In Ex-OR gate, the output is high if only one input is in high state or 1. If both the inputs are same, then the output is low.
• Exclusive-NOR (Ex-NOR) gate : In Ex-NOR gate, the output is high if both the inputs are same, otherwise the output is low.
• 34. Mixed Logic
• In mixed logic circuits, the values of the inputs are not fixed as compared to positive and negative logic.
• In positive logic, the high is represented as +5V or TRUE and low is represented as 0V or FALSE. In negative logic, the high is represented as 0V or FALSE and low is represented as +5V or TRUE.
• In mixed logic, the user can assign any value of the inputs to the logic circuits.
• 35. Chapter 4 Logic Families
• 36. Chapter Objectives
• Understand the basics of digital Integrated Circuits (IC)
• Understand the different types of transistor logic
• Understand the concept of Metal-oxide Semiconductor (MOS) digital ICs
• Understand the different types of BiCMOS logic circuits
• 37. Digital Integrated Circuits
• Digital ICs operate with binary signals and are constructed with ICs.
• Characteristics of digital ICs are:
• Speed of operation
• Fan-in
• Noise immunity
• Digital ICs can be classified into two categories:
• MOS family: It includes the following Metal-oxide Semiconductor Field-effect Transistor (MOSFETs):
• p-channel MOSFET (PMOS)
• n-channel MOSFET (NMOS)
• Complementary MOSFET (CMOS)
• 38.
• Bipolar logic families: These ICs can be classified as saturated and non-saturated logic families.
• Saturated logic families consists of:
• Resistor-transistor Logic (RTL)
• Resistor-capacitor Transistor Logic (RCTL)
• Diode-transistor Logic (DTL)
• High Threshold Logic (HTL)
• Transistor-transistor Logic (TTL)
• Integrated-injection Logic (I 2 L)
• Non-saturated logic families consists of:
• Schottky TTL
• Emitter-coupled Logic (ECL)
Digital Integrated Circuits (Contd..)
• 39. Current-sourcing and Current-sinking
• The logic families are categorized on the basis of current flow from the output of one logic circuit to the input of another.
• If the output of a TTL gate is HIGH, a reverse emitter current of 40 mA flows from the driver gate transistor to the load gate transistor. Here, the driver gate transistor is known as current source.
• If the output of the TTL gate is LOW, an emitter current of 1.6 mA flows from the load gate transistor to the driver gate transistor. The driver gate transistor is known as current sink.
• 40. Resistor-transistor Logic
• RTL NOR gate consists of resistors and transistors.
• If the inputs of RTL are LOW, then the transistors are turned OFF. Therefore, the output of the circuit is at logic 1.
• If any of the inputs are at logic 1, then the transistors are turned ON. Thus, the output of the circuit is at logic 0.
• Characteristics of RTL family are:
• Operation speed is low and average power of dissipation is high.
• Highly sensitive to temperature but poor immunity to noise.
• 41. Resistor-capacitor-transistor Logic
• RCTL circuit consists of a capacitor with an input resistor to increase the speed and improve the immunity to noise.
• During the transient phase, the resistor is bypassed by the capacitor. Thus, the base current increases and the input capacitance is discharged quickly.
• 42. Diode-transistor Logic
• DTL family removes the problem of output voltage by increasing the load on the circuit.
• If the inputs to the diodes are HIGH, they are reverse-biased. If both the diodes and the transistors are switched ON, then the output is LOW.
• If any of the inputs to the diodes is LOW, the current flows through the other diode and the voltage to that diode drops down. Then, the base voltage becomes LOW and the transistor remains at logic 0 and the output is HIGH.
• 43. High Threshold Logic
• HTL NAND gate is constructed by replacing the second diode from the DTL NAND gate with the Zener diode and increasing the power supply.
• Resistor values of this gate are increased to obtain equal amount of current from DTL and HTL gates.
• These gates are useful in environments where the noise level is high.
• 44. Transistor-transistor Logic
• The 54/74 series of TTL family is classified into 5 divisions:
• Standard (SN 54/74)
• High-speed (SN54H/74H)
• Low-power (SN54L/74L)
• Schottky-diode-clamped (SN54S/74S)
• Low power schottky (SN54LS/74LS)
• 45. Transistor-transistor Logic (Contd..)
• Common characteristics are:
• Supply voltage for all the divisions is 5.0 V.
• Logical 0 output voltage is 0V to 0.4V.
• Logical 1 output voltage is 2.4V to 5V.
• Logical 0 input voltage is 0V to 0.8V.
• Logical 1 input voltage is 2V to 5V.
• Noise immunity is 0.4 V.
• 46. Integrated-injection Logic
• I 2 L is also called Merged Transistor Logic (MTL).
• It uses two types of bipolar junction to form a large number of IC gate on the chip. Types of bipolar junction are:
• n-p-n
• p-n-p
• It dissipates less power even if it is operated at high speed.
• 47. Emitter-coupled Logic
• ECL is a Current-mode Logic (CML).
• It reduces the saturated transistor delay by operating in active mode.
• The differential amplifier, which is the basic circuit of ECL, draws the constant current during the transition of circuit from one state to another.
• 48. MOS Digital Integrated Circuits
• MOS technology is derived from the basic MOS structure of metal electrode on the oxide insulator over a semiconductor substrate.
• They are commonly used in digital devices such as logic gates and registers.
• They can accommodate more number of circuit elements than bipolar ICs.
• Operating speed of MOS IC is less than bipolar ICs.
• 49. MOS Digital Integrated Circuits (Contd..)
• Characteristics of MOS logic are:
• Propagation delay is 50ns.
• Fan-out capacity of is unlimited.
• Draw less power because of large resistance.
• Simplest as they use only one basic element, NMOS transistor.
• 50. Complementary MOS Logic
• They are also called COSMOS or CMOS and are made using PMOS and NMOS transistors.
• Characteristics of CMOS are:
• Power consumption is very low.
• Propagation delay ranges from 25ns to 150ns that depends upon the power supply.
• CMOS can operate at voltage range of +3V to +15V.
• Fan-out of CMOS is 10.
• They have small power dissipation and improved noise immunity.
• 51. BiCMOS Logic Circuits
• BiCMOS is used for developing low voltage analog circuits, Very Large Scale Integration (VLSI) circuits and Application Specific Integrated Circuits (ASIC).
• Basic BiCMOS inverter circuit is formed from the complementary pairs of PMOSFET and NPMOSFET with NPN transistors.
• The switching speed of basic inverter can be improved by discharging the excess carriers from the transistors with additional NMOS devices.
• 52. Compatibility or Interfacing
• The output of the circuit should match with the inputs of other circuits. This is referred to as compatibility.
• An interface circuit is the one, which is connected between the drivers and the loads.
• The designer of the circuit should take care while matching the characteristics of current and voltage of two circuits of two different families.
• An interface circuit between the two families is required to match the output characteristics of the driver and the load.
• 53. Chapter 5 Arithmetic Circuits
• 54. Chapter Objectives
• Understand the basics of arithmetic circuits
• Understand the designing of combinational circuits
• Understand the types of circuits in digital system:
• Combinational logic circuit
• Sequential logic circuit
• 55. Basics of Arithmetic Circuits
• Arithmetic circuits contain logic gates and flip-flops.
• Arithmetic circuits can perform all the arithmetic operations.
• The two types of Arithmetic circuits are:
• Combinational logic circuit : The output at any time depends only on the input values of that time. Examples of combinational logic circuits are:
• Sequential logic circuit : The output at any time depends on the present input values as well as the past output values.
• 56. Designing Combinational Circuit
• The following steps are performed to design a combinational circuit:
• Identify inputs and outputs and draw block diagram.
• Draw a truth table to describe the circuit operation for different combination of inputs.
• Write the switching expressions for outputs.
• Simplify the switching expression with the help of algebraic or K-map method.
• Implement this simplified expression with the help of logic gates.
• 57. Half Adder
• It is used for performing arithmetic addition of two binary digits.
• It has two inputs and two outputs.
• The two outputs represent sum and carry bits.
• Logic Symbol: Here A and B are inputs and S and C are sum and carry respectively.
Half Adder A B Carry(C) Sum(S) Inputs Outputs
• 58. Full Adder
• It is used for performing arithmetic addition of three binary digits.
• It has three inputs and two outputs.
• The two outputs represent sum and carry bits.
• Logic Symbol: Here A, B and C in are inputs and S and C out are outputs.
C out Full Adder C in S A B Outputs Inputs
• 59. K-Map Simplification
• This method is used for simplifying S and C out logical expressions in Full Adder.
• Diagrammatically:
• (a) K-map for Sum (b) K-map for C out
0 1 0 1 1 1 0 1 0 0 10 11 01 00 C in AB 1 1 1 0 1 0 1 0 0 0 10 11 01 00 C in AB
• 60. Half Subtractor
• It is used for performing the arithmetic subtraction of two bits.
• It has two inputs and two outputs.
• The two outputs represent difference and borrow out.
• Logic Symbol: Here X (minuend) and Y (subtrahend) are inputs and D (difference) and B out (borrow out). are outputs.
Half Subtractor X Y B out D Inputs Outputs
• 61. Full Subtractor
• It is used for performing the arithmetic subtraction of three bits.
• It has three inputs and two outputs.
• The two outputs represent difference and borrow out.
• Logical Symbol: Here X (minuend), Y (subtrahend) and B in (borrow from previous stage) are inputs and D (difference) and B out (borrow out) are outputs.
Full Subtractor Inputs Outputs X Y B in D B out
• 62. Parallel Binary Adder
• In parallel binary adders, all the bits of augend and addend are fed into it simultaneously. Also, additions in each position take place at same time in these adders.
• Two or more parallel adders can be connected in cascade to perform the addition operation on large binary numbers.
• Most commonly used parallel binary adder is the IC 7483. It has:
• Four interconnected full-adders
• One look ahead carry circuitry
• 63. Parallel Binary Subtractor
• A parallel binary subtractor can be implemented by cascading several full-subtractors.
• A 4-bit parallel binary subtractor has four difference outputs and one borrow output.
• In a 4-bit parallel binary subtractor, the input of the least significant bit full-subtractor is connected to 0 and the output of the i th full-subtractor is fed as input to (i+1) th full-subtractor.
• 64. Controlled Inverter
• A controlled inverter is used to invert a binary digit, i.e. it helps in obtaining the complement of the binary digit.
• An Ex-OR gate can be used as a controlled inverter to obtain the complement of a binary digit as shown in the figure:
• Similarly, a group of Ex-OR gates can be used to invert a group of binary digits.
C X Y
• 65. 4-bit Parallel Adder/Subtractor
• In 4-bit parallel binary adder/subtractor both operations, addition and subtraction can be performed.
• A 4-bit parallel adder/subtractor has two 4-bit inputs
• It has ADD/SUB control line connected with input of the least significant bit of full-adder for addition and subtraction.
• For subtraction ADD/SUB input is kept high and for addition ADD/SUB input is kept low.
• 66. Fast Adder and Serial Subtractor
• In Fast adder, output is given only after the carry is propagated through each of the adders.E.g. 4-bit carry look ahead adder:
• 4-bit carry look ahead adder is based on the principle of looking at lower order bits of augend and addend if high order carry is generated.
• It reduces the carry delay by reducing the number of gates through which a carry signal must propagate.
• Serial subtractor can be obtained by converting serial adder using the 2’s complement system.
• For subtraction subtrahend stored in one register is 2’s complemented before adding to minuend in other register.
• 67. Serial Adder and BCD Adder
• A Serial adder performs the addition operation bit by bit.
• The Serial adder requires a simpler circuitry than parallel adder, but provides low speed of operation
• A BCD adder adds two 4-bit BCD numbers to produce a 4-bit sum output and a carry output. The following conditions need to be considered for the form of the sum:
• If the 4-bit sum is equal to or less than 9, the sum is in BCD form.
• If 4-bit sum is greater than 9 or if carry is generated, the sum is not in BCD form. To produce the BCD result, digit 6(0110) must be added to the 4-bit sum.
• 68. Binary Multiplier
• Binary multipliers are used for multiplication operation which involves partial product, addition and shifting.
• In binary multiplier:
• If multiplier bit is 1, then multiplicand is simply copied as partial product.
• If multiplier bit is 0, then partial product is 0.
• When a partial product is obtained , it is shifted one bit to the left of previous partial product
• The shifting of partial products is performed until all the multiplier bits are checked, which is then followed by addition of the partial products.
• 69. Binary Divider
• In Binary divider, the dividend is stored in dividend register, while the divisor is stored in divisor register. The division process involves the following steps:
• Shift the combined contents of X and Y registers to left by one bit.
• Subtract the content of divisor register from the content of X register.
• Put 1 in the LSB of dividend register in case there is no borrow in the previous register. Otherwise, adds the contents of X and dividend registers to restore the original content of X.
• Repeat steps 1 to 3 for n times, where n is the number of bits in the dividend.
• 70. Chapter 6 Combinational Circuits
• 71. Chapter Objectives
• Understand the different types of combinational circuits
• Understand the different types of encoders and decoders
• Understand the concept of parity bits
• Understand the concept and applications of magnitude comparator
• 72. Multiplexer
• Multiplexer (MUX) is a combinational circuit.
• It accepts many inputs and transmits the data over a single output.
• It is also known as data selector.
• The input line is selected by the set of selection lines.
• For n input lines, the number of selection lines will be m, where 2 m = n.
Select inputs Data inputs Data output MUX
• 73. Demultiplexer
• Demultiplexer (DEMUX) is a combinational circuit.
• It accepts one input and transmits the data over multiple outputs.
• It is also known as data distributor.
• The output line is selected by the set of selection lines.
• For n output lines, the number of selection lines will be m, where 2 m = n.
Select inputs Data input Data outputs DEMUX
• 74. Decoder
• Decoder is similar to demultiplexer, but it does not contain data input.
• It is a logic circuit and converts n-bit input to 2 n output lines in such a way that the output line will be activated for only one combination of input lines.
• If the number of input and output lines are same, then a decoder acts as a converter to convert the Binary code to Gray code or BCD to Excess-3 code.
• 75. Decoder (Contd..)
• An AND gate can be used as the basic binary decoder because the output of the AND gate is HIGH only when all the inputs are HIGH.
• For example, if the input binary number is 1110, then the last bit has to be inverted to make all the inputs HIGH.
A B Y=ABCD C D
• 76. Decoder (Contd..)
• Decoders can be classified as:
• 3-to-8 decoder : It has 3 inputs that are used to select one out of eight outputs and it is also known as 1-of-8 decoder.
• 4-to-16 decoder : It has 4 inputs that are used to select one out of sixteen outputs and it is also known as 1-of-16 decoder.
• BCD-to-decimal decoder : It accepts 4-bit BCD as the input and produces 10 outputs corresponding to each decimal digit.
• BCD-to-seven-segment decoder : It is used to display decimal digits from 0 to 9. It accepts decimal digits in BCD and generates the corresponding seven-segment code.
• 77. Liquid Crystal Display
• Liquid Crystal Display (LCD) operates at low voltage AC signal drawing less current.
• AC voltage is applied between the 7-segment and the backplane. Both of them act as capacitor and draw less current when AC signal is kept low.
• The segments in the display are connected to EX-OR gate with one input connected to 7-segment decoder and the other connected to the signal source.
• 78. Liquid Crystal Display (Contd..)
• If the input of the EX-OR gate is LOW, then the output becomes same with the input provided to the backplane.
• If the input of the EX-OR gate is HIGH, then the output becomes 180 o out of phase with the input provided to the backplane.
• 79. Encoders
• Encoders convert the input signal to the coded output signal.
• They have n input lines out of which only one remains active at a time and m output lines, where m<n.
Encoder ∙ ∙ ∙ ∙ ∙ ∙ n inputs m outputs
• 80. Encoders (Contd..)
• Types of encoders are:
• Octal-to-binary encoder: It performs the inverse of 3-to-8 decoder and has eight input lines. It produces 3-bit output corresponding to the input.
• Decimal-to-BCD encoder: It consists of ten input lines for ten decimal digits. It produces 4-bit output representing the BCD value of the input.
• Priority encoder: It includes the priority function in which the precedence is given to the input with the highest priority, if they all are HIGH.
• 81. Parity Bit
• Parity bit is an extra bit added to the data, which helps in detecting the presence of error in the data while transmitting it from one location to another.
• Types of parity bits are:
• Even parity : In even parity, an extra bit is added to the data to make the number of 1’s even.
• Odd parity : In odd parity, an extra bit is added to the data to make the number of 1’s odd.
• EX-NOR gate is used to generate the parity for the data and EX-OR gate is used to check the parity of the data.
• 82. Code Converter
• Code Converter is used to change the data from one binary code to another.
• For example, 7-segment decoder can be considered as a code converter that converts the decimal digits to 7-segment code.
• Types of code converter are:
• BCD-to-binary code converter
• Binary-to-gray code converter
• Gray code-to-binary converter
• 83. Magnitude Comparator
• Magnitude Comparator is used to compare the magnitude of two numbers A and B.
• It generates one of the following results:
• A = B
• A < B
• A > B
Magnitude comparator A B A = B A < B A > B
• 84. Magnitude Comparator (Contd..)
• Magnitude comparator uses EX-NOR gate to check whether the digits are equal or not.
• It uses AND gate to check whether the binary digit is less or greater than the second number.
• Comparators are applied:
• As part of address decoding circuitry in computers.
• To actuate circuitry for driving physical variable to the reference value.
• 85. Chapter 7 Flip-Flops
• 86. Chapter Objectives
• Understand the basics of Sequential Circuits
• Understand the concept of Latches and their types
• Understand the concept of Flip-Flops, their types and triggering
• Understand the process of realizing flip-flops
• Understand the application of flip-flops
• 87. Overview of Arithmetic Circuits
• Features of combinational circuits are:
• The output of the combinational circuit at any instant depends on the input signals present at that time.
• The output signals from these circuits are not fed back to the input of the circuit.
• The combinational circuits do not require memory elements and are thus faster.
• Features of sequential circuits are:
• The outputs of the sequential circuit at any instant depend on the present and past inputs.
• The output signals from these circuits are fed back to the input of the circuit.
• The sequential circuits require memory elements and are thus slower.
• 88. Sequential Circuits
• Sequential circuits are classified into two types:
• Synchronous or clocked circuit :
• It contains a timing device, known as master-clock generator to achieve synchronization.
• In practice, synchronization is achieved by applying clock pulses to various AND gates through which external inputs enter the circuit.
• The rate of pulse generation must be slow enough to permit the slowest circuit to respond.
• Asynchronous or unclocked circuit :
• In this circuit, an event occurs as soon as one event is completed.
• The events need not to wait for a clock pulse for their occurrence.
• An asynchronous circuit is faster in comparison to a synchronous circuit, but it is more unstable.
• 89. Latches
• A Latch is the simplest sequential circuit that can store one bit of information, i.e. logic 1 or 0.
• It is known as latch as it allows one bit of information to lock or latch.
• The following types of latches are available:
• Set-Reset (S-R) Latch :
• It can be implemented using NAND or NOR gates.
• It has two inputs and two outputs, where the two outputs complement each other.
• 90. Latches (contd..)
• NOR-based S-R Latch :
• It is also known as asynchronous sequential circuit.
• It can be implemented using two NOR gates connected back to back.
• The output from one gate acts as the input of the other.
• The state diagram gives the two stable states of S-R latch, 0 and 1.
• On SET input, the latch is set to 1 while on RESET it is reset to 0.
• NAND-based S-R Latch :
• It can be implemented using cross-coupled NAND gates.
• Its inputs are normally 1 and must be pulsed to 0 to change the latch output state.
• 91. Flip-Flops
• A Flip-Flop is a latch with additional control input that determines when the state of the circuit is to be changed.
• The additional control input can be either a clock or an enable input.
• Flip-Flops can be differentiated depending on its transition between two states. Various types of flip-flops are:
• S-R flip-flop:
• It consists of two additional AND gates at the inputs S and R. In this type of flip-flop:
• In this circuit, when the clock input is LOW, the output of both the AND gates are LOW and changes in S and R do not affect the output of the flip-flop.
• Again, when the clock input is HIGH, the value at S and R will be passed to the output of the AND gates and the output of the flip-flop will change as per the changes in S and R.
• 92. Flip-Flops (contd..)
• D flip-flop :
• It is also known as the Delay flip-flop having one input, D and two outputs Q and Q.
• A D flip-flop can be constructed by inserting an inverter between S and R of an S-R flip-flop where the symbol D is assigned to the S input.
• J-K flip-flop :
• A J-K flip-flop can be implemented through clocked S-R Flip-Flop by augmenting two AND gates.
• The inputs J and K acts like inputs S and R to set and reset the flip-flop respectively.
• When J = K = 1, the flip-flop output switches to the complement state, i.e. if Q = 0, it switches to Q = 1 and vice versa.
• 93. Flip-Flops (contd..)
• T flip-flop :
• It is also known as Toggle or Trigger Flip-Flop having a single data input, T, a clock input and two outputs Q and Q
• It is commonly seen in counters and sequential counting networks.
• It is obtained from a J-K flip-flop by connecting its J and K inputs together.
• The designation T comes from the ability of this flip-flop to toggle or complement its state.
• 94. Triggering Of Flip-Flops
• Triggering specifies the changes in the output of a flip-flop that occurs in synchronization with the clock.
• It can be of two types based on the particular time interval in the clock at which it occurs:
• Level triggering : The condition when the clock pulse goes high is known as level triggered flip-flop. They can be further classified as:
• Positive level triggered flip-flop : When clock is positive and flip-flop changes state it is called positive level triggered flip-flop.
• Negative level triggered flip-flop : When clock is negative and flip-flop changes state it is called negative level triggered flip-flop.
• 95. Triggering of Flip-Flops (contd..)
• Edge Triggering : The condition when flip-flop changes its state either at positive or negative edge of the clock pulse is known as edge-triggered flip-flop. They can be further classified as:
• Edge-triggered D flip-flop : In this flip-flop, a circuit containing capacitor and resistor is used. It is inserted between the clock and the input to the AND gates. Conditions for this flip-flop are:
• When clock input is LOW, the flip-flop retains its previous state irrespective of whether D = 0 or 1.
• When clock input is HIGH, the flip-flop takes the value of D.
• Edge-triggered J-K flip-flop : In this flip-flop, the two outputs are fed back to the opposite NAND gates. Conditions for this flip-flop are:
• When J = 0 and K = 0, it is called no change condition.
• When J = 1 and K = 1, it is called toggle operation.
• 96. Master-Slave Flip-Flops
• Master-slave flip-flop is constructed by serially connecting two separate flip-flops.
• Here, one flip-flop is known as the master, while the other as slave.
• A master-slave J-K flip-flop can be constructed using two J-K flip-flops, where one acts as the master and other as the slave.
• A master-slave J-K flip flop helps in handling the race-around condition, which is specified as:
• When J = K= 1 and Q = 0 and 1, the output oscillates between 0 and 1 within the time period.
• 97. Realization of Flip-Flops
• The steps of realizing flip-flop are:
• Obtain word description of the desired flip-flop (X).
• Obtain Present State-Next State (PS-NS) table for the desired flip-flop (X).
• Use the excitation table or application table of the chosen flip-flop (Y).
• Append the next state code or excitation input values in the Present State-Next State table.
• Use K-maps simplifying the logic expressions for excitation inputs of Y and design next state decoder logic.
• Use next state decoder logic and chosen flip-flop (Y) to draw a circuit for the desired flip-flop (X).
• 98. Applications of Flip-Flops
• Flip-flops are primarily used in counter circuits, frequency dividers, shift and storage registers.
• It can also help in accomplishing serial decoding, comparison and timing functions.
• Other functions of flip-flops include:
• Frequency Division : Flip-flops are used to divide the frequency of a periodic waveform.
• Shift Registers : Flip-flops are used in shift Registers for transferring the contents of one register to the other. If the flip-flop lies within the same register, then shifting takes place in one bit at a time.
• 99. Applications of Flip-Flops (contd..)
• Counters : Flip-flops can also be used as a binary counter where a set of flip-flops are connected in a manner so that they can count the sequence of input pulses presented to it in digital form.
• Parallel Data Storage : Flip-flops are helpful in parallel data storage. Various features are:
• Several bits of data can be stored simultaneously in a group of flip-flop. All the parallel data lines are connected to the input of flip-flops.
• Clock inputs of all the flip-flops are connected to common clock input, so that each flip-flop is triggered at the same time.
• The clear inputs are connected to common clear line, which resets all the flip-flops.
• 100. Chapter 8 Counters
• 101. Chapter Objectives
• Understand the different types of ripple counters
• Understand the different types of synchronous and asynchronous counters
• Understand the concept of presettable counters
• Understand the applications of counters
• 102. Asynchronous Counter
• Asynchronous Counter is also called ripple or serial counter.
• It is constructed using JK flip-flop.
• In this all the flip-flops are not controlled by a single clock.
• The clock is applied to the least significant bit stage of the counter and rest of the flip-flops are controlled by the output of the previous flip-flops.
• The propagation delay of the counter is the sum of individual delays of all the flip-flops.
• The MOD-number or modulus of the counter refers to the total number of states that the counter undergoes in each complete cycle. It is equal to 2 n , where n is the total number of flip-flops.
• 103. Ripple Counter with Decoded Outputs
• It consists of three master-slave JK flip-flops with decoding circuitry.
• In decoding the states of the ripple counter, the pulse of one clock duration takes place at the decoding gate outputs as the flip-flops change their states.
• The gate connected to the outputs of the counter is the decoding gate.
• The output of the decoding gate is high only when the contents of the counter is equal to the given state.
• 104. Ripple Counter with Decoded Outputs (Contd..)
• The decoding gates of asynchronous counter produces high output more than once. These undesired outputs are called glitches or false spikes.
• The glitches should be avoided by strobing the decoding gates with clock inputs.
• The maximum MOD-number that can be achieved using n flip-flops is 2 n .
• Ripple counter can be modified to produce MOD-number less than 2 n by skipping the states of counting sequence.
• 105. Counter Integrated Circuits
• Counter Integrated Circuits consist of four master-slave flip-flops.
• These flip-flops are internally connected to provide different types of counters.
• It uses two reset counters for resetting the counter to 0000.
• Types of counter ICs are:
• Decade counter: The master-slave flip-flops are connected to provide divide-by-2 and divide-by-8 counters.
• 4-bit binary ripple counter: The master-slave flip-flops are connected to provide divide-by-2 and divide-by-5 counters.
• 106. Asynchronous Down Counter
• A down counter using n flip-flops counts downwards from the maximum count of (2 n -1) to 0.
• In Asynchronous Down Counter, each flip-flop, except the LSB, changes its state when the inverted output of the preceding flip-flop goes from HIGH to LOW.
• It is used for calculating the desired number of input pulses that has occurred.
• The counter is preset to the desired number and allowed to countdown as the pulses are applied.
• 107. Up-down Counter
• Up-down Counter is a combination of up and down counter.
• It can count upwards as well as downwards.
• It is also called multimode counter.
• It uses logic gates to allow either the inverted or non-inverted output of one flip-flop to the clock input of the next flip-flop, depending upon the status of control inputs.
• If the control inputs are both 1 or 0, then the counter does not count upwards or downwards, because the clock inputs of all the flip-flops except, the LSB will be held constant at either 0 or 1. This condition is avoided.
• 108. Propagation Delay in Ripple Counter
• In ripple counter, the settling time becomes large due to presence of propagation delay (t pd ) of each flip-flop.
• The propagation delay of the first and second flip-flops is t pd and 2 t pd respectively.
• The maximum frequency used in asynchronous counter is 1/f max ≥ n t pd
• or f max ≥ 1/ n t pd.
• 109. Synchronous (Parallel) Counter
• Synchronous parallel counter is the simplest binary counter.
• Synchronous parallel counter requires less hardware and the speed of operation is low because of propagation delay.
• In this counter, all the flip-flops change their states simultaneously with negative transition of the clock input signal.
• The total propagation delay is the sum total of the time taken by one flip-flop to toggle and the time for new logic levels to propagate through one AND gate.
• 110. Synchronous (Parallel) Counter (Contd..)
• The propagation delay of synchronous counter is independent of the number of flip-flops used in the counter.
• A parallel counter can be modified using the inverted outputs of flip-flops to feed different logic gates. The resulting counter is called parallel down counter.
• The maximum frequency of operation of synchronous counter is:
• f max = 1/(t p + t g )
• Where, t p is propagation delay and t g is the propagation delay of one AND gate.
• 111. Problems with Synchronous Parallel Counter
• With the increase in the number of stages, the synchronous parallel counter requires:
• More number of AND gates
• More number of inputs per control gate
• 112. Synchronous Counter with Ripple Carry
• Synchronous counter with ripple carry is used to eliminate the problems associated with the synchronous counter with parallel carry.
• The clock frequency of ripple carry synchronous counter is less than that of synchronous counter with parallel carry.
• The propagation delay of one AND gate is double as compared to synchronous counter with parallel carry.
• 113. Synchronous/Asynchronous Counter
• It is a combination of synchronous and asynchronous counters.
• It has the speed of synchronous counter and simplicity of asynchronous counter.
• Input is applied only to the LSB flip-flop, similar to asynchronous counter.
• Output of the counter drives the clock input of all the other flip-flops so that they trigger simultaneously, similar to synchronous counter.
• 114. Presettable Counter
• The counter that starts counting from any state is called presettable counter.
• It is also known as programmable counter.
• It accepts the starting state using the PRESET and CLEAR inputs.
• Example of presettable counter is MOD-8 ripple UP counter.
• 115. Design of Synchronous Counters
• Steps of designing synchronous counter are:
• Draw the state diagram to describe the operation of the counter.
• Obtain the Present State-next State (PS-NS) table from the state diagram to remove redundant state.
• Make state assignment and document same in the above state table.
• Obtain the excitation table from PS-NS table.
• Draw the excitation maps of flip-flops and simplify the excitation functions.
• Draw the schematic diagram of the counter.
• 116. Implementation and Application of Counter
• Applications of counter are:
• The frequency of the pulse signal can be measured and displayed using a counter. Such counters are known as frequency counter.
• The time period of the signal can be measured by using counter.
• Digital clocks can be implemented using counters to display the time of day in hours, minutes and seconds.