excellent presentation of basics of digital electronics. If you add the logical diagrams for flip flops(master- slave, J-K, S-R,...) it would more easy for the students to understand. Very good.
Code is the symbolic representation of discrete information, which can be represented in the form of numbers and letters.
Codes are classified in five groups:
Weighted binary codes: These codes follow the positional weighting principle in which the position of the numbers represent the weight. The different types of weighted codes are:
Non-weighted codes: These codes are not positionally weighted. Each position within the binary number is not assigned a fixed value. The different types of non-weighted codes are:
Excess-3 code
Gray code
Error detecting codes: These codes are used to detect errors in the decimal numbers. The different types of error detecting codes are:
According to DeMorgan’s first theorem, the complement of the product of two binary variables is equal to the sum of the complements of two binary variables.
It can be stated as:
(AB) * = A * + B *
According to DeMorgan’s second theorem, the complement of the sum of the two binary variables is equal to the product of the complements of two binary variables.
Karnaugh map is a systematic method for simplifying and manipulating switching expressions.
It is used to represent the information contained in a truth table or the information available in the form of POS or SOP. The characteristics of a K-map are:
In an n-variable K-map, there are 2 n cells and each cell matched to one combination of n variables.
In an n-variable K-map, a collection of 2 m cells and each adjacent to m cells is known as a group.This group can be expressed by a product containing n-m variables where n is the number of variables in the K-map.
Logic circuit consists of three elements, which are:
Input variables : The input variables are the inputs to the logic circuits, which are represented by 1 and 0. The input 1 implies the high voltage (High) or +5V and input 0 implies the low voltage (Low) or 0V.
Output variables : The output variables are the resultant outputs of the two input variables. The resultant output depends upon the type of logic gate that is being used.
Logic gate : A logic gate is an electronic circuit that has two inputs and one output. At any instant, every input is in one of the two binary conditions such as 0 and 1.
The NAND or NOR gates are known as universal gates. These gates are used to implement any gate like AND,OR and NOT gates.
The following two gates are also used in logic circuits:
Exclusive-OR (Ex-OR) gate : In Ex-OR gate, the output is high if only one input is in high state or 1. If both the inputs are same, then the output is low.
Exclusive-NOR (Ex-NOR) gate : In Ex-NOR gate, the output is high if both the inputs are same, otherwise the output is low.
In mixed logic circuits, the values of the inputs are not fixed as compared to positive and negative logic.
In positive logic, the high is represented as +5V or TRUE and low is represented as 0V or FALSE. In negative logic, the high is represented as 0V or FALSE and low is represented as +5V or TRUE.
In mixed logic, the user can assign any value of the inputs to the logic circuits.
The logic families are categorized on the basis of current flow from the output of one logic circuit to the input of another.
If the output of a TTL gate is HIGH, a reverse emitter current of 40 mA flows from the driver gate transistor to the load gate transistor. Here, the driver gate transistor is known as current source.
If the output of the TTL gate is LOW, an emitter current of 1.6 mA flows from the load gate transistor to the driver gate transistor. The driver gate transistor is known as current sink.
RCTL circuit consists of a capacitor with an input resistor to increase the speed and improve the immunity to noise.
During the transient phase, the resistor is bypassed by the capacitor. Thus, the base current increases and the input capacitance is discharged quickly.
DTL family removes the problem of output voltage by increasing the load on the circuit.
If the inputs to the diodes are HIGH, they are reverse-biased. If both the diodes and the transistors are switched ON, then the output is LOW.
If any of the inputs to the diodes is LOW, the current flows through the other diode and the voltage to that diode drops down. Then, the base voltage becomes LOW and the transistor remains at logic 0 and the output is HIGH.
BiCMOS is used for developing low voltage analog circuits, Very Large Scale Integration (VLSI) circuits and Application Specific Integrated Circuits (ASIC).
Basic BiCMOS inverter circuit is formed from the complementary pairs of PMOSFET and NPMOSFET with NPN transistors.
The switching speed of basic inverter can be improved by discharging the excess carriers from the transistors with additional NMOS devices.
It is used for performing the arithmetic subtraction of three bits.
It has three inputs and two outputs.
The two outputs represent difference and borrow out.
Logical Symbol: Here X (minuend), Y (subtrahend) and B in (borrow from previous stage) are inputs and D (difference) and B out (borrow out) are outputs.
In parallel binary adders, all the bits of augend and addend are fed into it simultaneously. Also, additions in each position take place at same time in these adders.
Two or more parallel adders can be connected in cascade to perform the addition operation on large binary numbers.
Most commonly used parallel binary adder is the IC 7483. It has:
A parallel binary subtractor can be implemented by cascading several full-subtractors.
A 4-bit parallel binary subtractor has four difference outputs and one borrow output.
In a 4-bit parallel binary subtractor, the input of the least significant bit full-subtractor is connected to 0 and the output of the i th full-subtractor is fed as input to (i+1) th full-subtractor.
A Serial adder performs the addition operation bit by bit.
The Serial adder requires a simpler circuitry than parallel adder, but provides low speed of operation
A BCD adder adds two 4-bit BCD numbers to produce a 4-bit sum output and a carry output. The following conditions need to be considered for the form of the sum:
If the 4-bit sum is equal to or less than 9, the sum is in BCD form.
If 4-bit sum is greater than 9 or if carry is generated, the sum is not in BCD form. To produce the BCD result, digit 6(0110) must be added to the 4-bit sum.
In Binary divider, the dividend is stored in dividend register, while the divisor is stored in divisor register. The division process involves the following steps:
Shift the combined contents of X and Y registers to left by one bit.
Subtract the content of divisor register from the content of X register.
Put 1 in the LSB of dividend register in case there is no borrow in the previous register. Otherwise, adds the contents of X and dividend registers to restore the original content of X.
Repeat steps 1 to 3 for n times, where n is the number of bits in the dividend.
Decoder is similar to demultiplexer, but it does not contain data input.
It is a logic circuit and converts n-bit input to 2 n output lines in such a way that the output line will be activated for only one combination of input lines.
If the number of input and output lines are same, then a decoder acts as a converter to convert the Binary code to Gray code or BCD to Excess-3 code.
3-to-8 decoder : It has 3 inputs that are used to select one out of eight outputs and it is also known as 1-of-8 decoder.
4-to-16 decoder : It has 4 inputs that are used to select one out of sixteen outputs and it is also known as 1-of-16 decoder.
BCD-to-decimal decoder : It accepts 4-bit BCD as the input and produces 10 outputs corresponding to each decimal digit.
BCD-to-seven-segment decoder : It is used to display decimal digits from 0 to 9. It accepts decimal digits in BCD and generates the corresponding seven-segment code.
Parity bit is an extra bit added to the data, which helps in detecting the presence of error in the data while transmitting it from one location to another.
Types of parity bits are:
Even parity : In even parity, an extra bit is added to the data to make the number of 1’s even.
Odd parity : In odd parity, an extra bit is added to the data to make the number of 1’s odd.
EX-NOR gate is used to generate the parity for the data and EX-OR gate is used to check the parity of the data.
A Flip-Flop is a latch with additional control input that determines when the state of the circuit is to be changed.
The additional control input can be either a clock or an enable input.
Flip-Flops can be differentiated depending on its transition between two states. Various types of flip-flops are:
S-R flip-flop:
It consists of two additional AND gates at the inputs S and R. In this type of flip-flop:
In this circuit, when the clock input is LOW, the output of both the AND gates are LOW and changes in S and R do not affect the output of the flip-flop.
Again, when the clock input is HIGH, the value at S and R will be passed to the output of the AND gates and the output of the flip-flop will change as per the changes in S and R.
Edge Triggering : The condition when flip-flop changes its state either at positive or negative edge of the clock pulse is known as edge-triggered flip-flop. They can be further classified as:
Edge-triggered D flip-flop : In this flip-flop, a circuit containing capacitor and resistor is used. It is inserted between the clock and the input to the AND gates. Conditions for this flip-flop are:
When clock input is LOW, the flip-flop retains its previous state irrespective of whether D = 0 or 1.
When clock input is HIGH, the flip-flop takes the value of D.
Edge-triggered J-K flip-flop : In this flip-flop, the two outputs are fed back to the opposite NAND gates. Conditions for this flip-flop are:
When J = 0 and K = 0, it is called no change condition.
When J = 1 and K = 1, it is called toggle operation.
Flip-flops are primarily used in counter circuits, frequency dividers, shift and storage registers.
It can also help in accomplishing serial decoding, comparison and timing functions.
Other functions of flip-flops include:
Frequency Division : Flip-flops are used to divide the frequency of a periodic waveform.
Shift Registers : Flip-flops are used in shift Registers for transferring the contents of one register to the other. If the flip-flop lies within the same register, then shifting takes place in one bit at a time.
Counters : Flip-flops can also be used as a binary counter where a set of flip-flops are connected in a manner so that they can count the sequence of input pulses presented to it in digital form.
Parallel Data Storage : Flip-flops are helpful in parallel data storage. Various features are:
Several bits of data can be stored simultaneously in a group of flip-flop. All the parallel data lines are connected to the input of flip-flops.
Clock inputs of all the flip-flops are connected to common clock input, so that each flip-flop is triggered at the same time.
The clear inputs are connected to common clear line, which resets all the flip-flops.
Asynchronous Counter is also called ripple or serial counter.
It is constructed using JK flip-flop.
In this all the flip-flops are not controlled by a single clock.
The clock is applied to the least significant bit stage of the counter and rest of the flip-flops are controlled by the output of the previous flip-flops.
The propagation delay of the counter is the sum of individual delays of all the flip-flops.
The MOD-number or modulus of the counter refers to the total number of states that the counter undergoes in each complete cycle. It is equal to 2 n , where n is the total number of flip-flops.
It consists of three master-slave JK flip-flops with decoding circuitry.
In decoding the states of the ripple counter, the pulse of one clock duration takes place at the decoding gate outputs as the flip-flops change their states.
The gate connected to the outputs of the counter is the decoding gate.
The output of the decoding gate is high only when the contents of the counter is equal to the given state.
104.
Ripple Counter with Decoded Outputs (Contd..)
The decoding gates of asynchronous counter produces high output more than once. These undesired outputs are called glitches or false spikes.
The glitches should be avoided by strobing the decoding gates with clock inputs.
The maximum MOD-number that can be achieved using n flip-flops is 2 n .
Ripple counter can be modified to produce MOD-number less than 2 n by skipping the states of counting sequence.
A down counter using n flip-flops counts downwards from the maximum count of (2 n -1) to 0.
In Asynchronous Down Counter, each flip-flop, except the LSB, changes its state when the inverted output of the preceding flip-flop goes from HIGH to LOW.
It is used for calculating the desired number of input pulses that has occurred.
The counter is preset to the desired number and allowed to countdown as the pulses are applied.
Up-down Counter is a combination of up and down counter.
It can count upwards as well as downwards.
It is also called multimode counter.
It uses logic gates to allow either the inverted or non-inverted output of one flip-flop to the clock input of the next flip-flop, depending upon the status of control inputs.
If the control inputs are both 1 or 0, then the counter does not count upwards or downwards, because the clock inputs of all the flip-flops except, the LSB will be held constant at either 0 or 1. This condition is avoided.
Synchronous parallel counter is the simplest binary counter.
Synchronous parallel counter requires less hardware and the speed of operation is low because of propagation delay.
In this counter, all the flip-flops change their states simultaneously with negative transition of the clock input signal.
The total propagation delay is the sum total of the time taken by one flip-flop to toggle and the time for new logic levels to propagate through one AND gate.
The propagation delay of synchronous counter is independent of the number of flip-flops used in the counter.
A parallel counter can be modified using the inverted outputs of flip-flops to feed different logic gates. The resulting counter is called parallel down counter.
The maximum frequency of operation of synchronous counter is:
f max = 1/(t p + t g )
Where, t p is propagation delay and t g is the propagation delay of one AND gate.