8051 Presentation

A N I NTRODUCTION T O 8051 M ICROCONTROLLER A ND I TS A PPLICATION Presented by S ANJOY B ANERJEE LECTURER

PART 1
THE 8051 ARCHITECTURE

It is a programmable computer but not itself a general purpose system. It is a hardware platform with Microprocessor and I/O devices which support required tasks and implement software that perform the required processing. EMBEDDED SYSTEM

EMBEDDED COMPUTERS
Microcontrollers are available in different levels of sophistications.
8 bit micro-controller for low cost
application includes on board
Memory &I/O devices .
16 bit micro-controller is for more
sophisticated applications.

CHARACTERISTICS OF EMBEDDED SYSTEM
Proper functionality
Complex algorithms
User interface
Real time
Cost of manufacturing
Power consumption

Microprocessor
Microprocessor is an Central Processing Unit of a Digital Computer, which contains an arithmetic and logic unit (ALU), a Program Counter (PC), a Stack Pointer (SP), some working Register, a clock timing circuit, and interrupt circuits.
To make a digital computer ,one must add memory usually RAM and ROM, parallel and serial I/O lines. In addition with some special purpose devices such as interrupt handlers and counter. And also required some mass storage devices usually floppy disk drive, hard disk drive, and other I/O peripherals, such as keyboard and CRT display .

CPU Read/Write RAM ROM Printer Keyboard Monitor Disk DATA BUS CONTROL BUS ADDRESS BUS Internal Organisation Of Computers

Microcontroller
A Microcontroller which is also known as a true computer on a single chip. It has a CPU which contain ALU, PC, SP, REGISTERS. In addition with a fixed amount of RAM,ROM,I/O ports including serial communication, and timer are all embedded together on a single chip. In some microcontroller an ADC and DAC (PWM o/p) also embedded in a single chip.

(a) General- Purpose Microprocessor System (b) Microcontroller CPU General- Purpose Microproc- essor RAM ROM I/O PORT Timer Serial COM Port CPU RAM ROM I/O Timer Serial COM Port

DIFFERENCE BETWEEN MICROPROCESSOR & MICROCONTROLLER
Microprocessor contains no RAM, ROM, I/O ports on the chip itself.
The addition of external RAM, ROM & I/O ports makes the whole system bulkier and much more expensive.
It can’t use in a small circuitry system.
Microprocessor have the advantage of versatility, such that the designer can decide the amount of RAM,ROM & I/O ports as needed.
Micro controller has a C.P.U in addition to a fixed amount of RAM, ROM, I/O ports and timer all on a single chip.
Because of embedded system there is no external RAM, ROM,timer,I/O ports & external memory in a micro controller system.So it is less expensive.
Micro controller is ideal for many application in which cost and space are critical.
It is not possible in a micro controller system.

A MICROCONTROLLER SURVEY
4 bit microcontroller
Serial bit I/O 2K 128 2 42:35 TLCS47 Toshiba LED display 1K 64 ---- 28:11 TMS 1000 TI 1K 32 ---- 16:11 MSM6411 OKI Serial bit I/O 1K 64 1 28:23 COP420 National 10 bit ROM 512 32 ----- 24:10 HMCS40 Hitachi Features ROM RAM Counter Pins:I/o Model Manufacturer

Contd.
Low cost, 124k EM, A/D, serial port 4K 256 2 28:22 Z86C83 ZILOG Features ROM RAM Counter Pins:I/O Model Manufacturer 2K 64 1 40:32 6500/1 Rockwell Serial port, WDT, A/D 8K 256 3 68:48 87C552 PHILIPS Serial port, WDT, A/D 8K 256 2 52:40 68HC11 Motorola Serial bit I/O 1K 64 1 28:24 COP820 National RC oscillator, self reset, low cost 1K 25 0 18:12 PIC 16C56 Microchip 128K EM, serial port 4K 128 2 40:32 8051 Intel 112k EM,A/D, serial port 4K 256 2 68:55 TMS370C050 TI

Contd.
Features ROM RAM Counter Pins:I/O Model Manufacturer 64K EM, serial port, A/D, PWM 16K 512 4 68:52 HPC16164 National 64K EM, serial port, A/D, PWM 8K 232 2 68:40 80C196 Intel 1M EM, A/D, serial port, PWM 32K 1K 5 84:65 H8/532 Hitachi

Choice of Processors Processors Microcontroller Microprocessor DSP 8 bit : 8085 Z80 6800 16 bit : 8086 Z8000 68000 32 bit : Pentium PowerPC 68000 8 bit : 8051 & derivatives Microchip PIC series 16 bit : Intel 80196 Microchip PIC series Texas MSP series 32 bit : ARM based Microcontrollers PowerPC based microcontrollers 16/32 bit : Blackfin ADSP-BF53x SHARC ADSP-21xxx Texas TMS320 series

ARM-7 based µC from NXP

16 bit MCU from Texas Architecture of MSP430F2013

MCUs Architecture
Von Neumann – contains single memory for storing control program & data, contains single bus for transferring data to/from CPU. Most computers use this.
Harvard – separate memory for program & data, with separate buses, increases speed since program & data can be fetched simultaneously, buts needs twice as many address & data pins. PIC MCUs use this
Modified Harvard – Single data & address bus externally, but two separate buses internally. Program & data information is separated by multiplexing method.

MCUs Architecture Memory (program +data) CPU Memory (program) Memory (data) CPU Von Neumann Harvard ADDRESS DATA ADDRESS ADDRESS DATA DATA

INSTRUCTION SET
Complex Instruction Set Computer – 8051 compatibles, Motorola 68HC11
Reduced Instruction Set Computer – PIC series, AVR series
In CISC type MCUs, a no. of instructions are available. RISC type MCUs have a min. set. Complex arithemetic, logical instructions are omitted. This reduces the complex instruction decoding process, thus making them faster. RISC MCUs have fixed length instructions to simplify the fetch & decoding cycle. Addresses & data are directly embedded in the instruction, thus allowing them to be fetched in a single cycle. For this the data bus width needs to be same as the instruction bus. Only 20% of most CISC type instructions are used.

Features of 8051
8 bit CPU with register A and B
16 bit Program Counter and Data Pointer
8 bit Program Status Word
8 bit Stack Pointer
Internal ROM and Internal RAM
4 Ports of each 8 bit, P0-P3
2 timers of each 16 bit, T0 and T1
Full Duplex serial data Transmitter/ Receiver
Control Registers: TCON,TMOD,SCON,PCON,IE,IP
2 external and 3 internal interrupt sources
Oscillator and Clock circuit

Arithmetic And Logic Unit PSW A B Special Function Register RAM PC DPTR DPH DPL ROM Port 0 Latch Port 1 Latch Port 2 System Timing System Interrupts Timer Data Buffers Memory Controls Latch Port 3 Latch Register Bank 0 Register Bank 1 Register Bank 2 Register Bank 3 Byte/Bit Address TLO THO TL1 TH1 TMOD TCON Special Function Register PCON SCON SBUF IP IE EA ALE PSEN XTAL 1 XTAL 2 RESET VCC GND 16-Bit Address Bus I/O A0-A7 D0-D7 I/O I/O A8-A15 I/O Interrupt Counter Serial Data RD-WR Internal RAM Structure 8051 family micro controller

8051 ARCHITECTURE

Features of the 8051 6 Interrupt sources 1 Serial port 32 I/O pins 2 Timer 128 bytes RAM 4K bytes ROM Quantity Feature

Comparison of 8051 Family Members 6 8 6 Interrupt sources 1 1 1 Serial port 32 32 32 I/O pins 2 3 2 Timers 128 256 128 RAM 0K 8K 4K ROM(on-chip program space in bytes) 8031 8052 8051 Feature Various 8051 Micro controllers

8751:- UV – EPROM version.
AT89C51:- Flash memory version from Atmel corporation.
DS5000 series from Dallas semiconductor in the form of NV – RAM.
Table 1: Versions of 8051 From Atmel (All ROM Flash)
Table 2: Various Speeds of 8051 From Atmel Table 3:- Versions of 8051 From Dallas Semiconductor’s Soft Micro controller 40 3V 8 3 32 128 8K AT89LV52 40 5V 8 3 32 128 8K AT89C52 20 3V 6 2 15 128 2K AT89C2051 20 3V 3 1 15 64 1K AT89C1051 40 3V 6 2 32 128 4K AT89LV51 40 5V 6 2 32 128 4K AT89C51 Packaging Vcc Interrupt Timer I/O pins RAM ROM Part Number Commercial DIP plastic 40 20 MHz AT89C51-20PC Commercial DIP plastic 40 16 MHz AT89C51-16PC commercial DIP plastic 40 12 MHz AT89C51-12PC Use Packaging Pins Speed Part Number Packaging Vcc Interrupt Timer I/O pins RAM ROM Part Number 40 3V 6 2 32 128 32K DS5000T-8 20 5V 6 2 32 128 8K DS5000-8 40 5V 6 2 32 128 32K DS5000-32 40 5V 6 2 32 128 8K DS5000-8

8051 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIN DESCRIPTION

PIN DESCRIPTION Contd.
As per pin diagram out of 40 pins, 32 pins are assigned for ports P0,P1,P2 and P3, where each ports takes 8 pins.
The rest of the pins are Vcc, GND,XTAL1, XTAL2, RST, EA’/VPP,ALE/PROG’, AND PSEN’.
Vcc: Pin 40 provides supply Voltage. The voltage source is 5V.
GND: Pin 20 is grounded.
XTAL1 & XTAL2 : 8051 needs external clock to run it. Most often a crystal is connected to XTAL1 (19) and XTAL2(18) for supplying operating frequency.
RST: Pin 9 is the Reset pin. It is an input pin and is active high. Upon applying a high pulse to this pin the 8051 will reset and terminate all the activities.

PIN DESCRIPTION Contd.
EA’/VPP: Pin 31 is the External access pin, generally we connected this pin with the Vcc, but when we use the external memory then this pin must be connected to Ground.
The VPP signal is used at the time of EPROM programming, where we supply a 21V through this pin.
ALE/PROG’: ALE (pin 30) stands for Address Latch Enable. This is an output pin and is active high. This pin is used for de-multiplexing the data and address bus by connecting to the enable pin of 74LS373 latch.
PROG’ is used at the time of EPROM programming. A 50 ms pulse is connected to the ground through this pin for EPROM programming.
PSEN’: PSEN’ (pin 29) stands for Program Store Enable. This is an output pin and connected to the external ROM.

Oscillator and Clock
8051 has on chip oscillator but requires an external clock to run it. Most often a Quartz Crystal oscillator is connected to XTAL 1 and XTAL 2 pins with 2 nos of 30 pf capacitors.

Oscillator and Clock contd .
If we use any external frequency source other than crystal oscillator, it will be connected to XLAT1 and XLAT 2 is left unconnected.
Time to execute a one cycle instruction is given by
T=(c x 12d)/ crystal frequency

Oscillator and Clock contd .

Reset Circuit

I/O PORT PINS AND THEIR FUNCTION
Four Ports P0,P1,P2and P3 of each 8 bit
All Ports upon RESET are configured as output Port
To use them as input Port, it must be programmed.
All Ports are bit accessible.

P0 PORT
P0 pins may serve as an inputs, outputs, when used together ,as a bidirectional low order address and data bus for external memory.
To configure it as an input port, a logical 1 must be written to the corresponding port0 latch by program.
It is used as a data bus during internal EPROM programming

P0 PORT contd.

P1& P2 PORT
P1 AND P2 may be used as an input or output port.
They does not required external pull-up resistors.
P2 supply the high-order address bus for external memory or input/output devices.

P3 PORTS
P3 may be used
as an input or output port.
The alternate uses of P3 are shown in table:
-- External memory read pulse RD’ P3.7 -- External memory write pulse WR’ P3.6 TMOD External timer 1 input T1 P3.5 TMOD External timer o input T0 P3.4 TCON.3 External interrupt 1 INT1’ P3.3 TCON.1 External interrupt 0 INT0’ P3.2 SBUF Serial data output TXD P3.1 SBUF Serial data input RXD P3.0 SFR Use Name Pin

REGISTER
A and B CPU register
Program Counter and Data Pointer
Flags and program Status Word (PSW)
Internal RAM
Some Special Function Register
8 bit Stack Pointer

A AND B CPU REGISTER
The A (Accumulator) register is used for many operation, including Addition, Subtraction, Integer Multiplication, Division and other logical operation.
The A register is also used for all data transfers between the 8051 and any external memory.
The B register is used with the A register for Multiplication and Division operation and has no other function other than as a location where data may be stored.

PROGRAM COUNTER AND DATA POINTER
Program Counter (PC) and Data Pointer (DPTR) are two 16 bit register.
PC and DPTR are used to hold the address of a Memory.
PC is used to hold the address of the next memory location which is to be executed.
The PC has no internal Address.
The DPTR register is made up of two 8 bit register named DPH and DPL.
DPTR is used to hold the memory address for internal and external code memory and external data memory.

PROGRAM STATUS WORD AND FLAGS
Program Status Word (PSW) is a 8 bit register.
PSW contains 4 math Flag, user program flag F0 and the register select bits RS1 and RS0
PSW register is bit addressable, so all the flags can be set or reset by the programmer at will. The PSW structure is shown bellow.
P ---- OV RS0 RS1 F0 AC CY 0 1 2 3 4 5 6 7

FLAGS Contd.
Flags are 1 bit register which are grouped inside the PSW and PCON.
Flags are provided to store the result of certain program instruction.
8051 has 4 math flags which include Carry flag (C), Auxiliary Carry (AC), Overflow (OV) and Parity (P), and 3 user flags are named F0,GF0, and GF1.
GF0 and GF1 are store in PCON register.
Carry flag is set when there is a carry in the 7 th bit of accumulator, this flag is used in arithmetic, jump, rotate, and Boolean instruction.

FLAGS Contd.
Auxiliary Carry flag is set when there is a carry form 3 rd bit to 4 th bit of accumulator. This flag is used in BCD arithmetic operation.
Overflow flag is set when there is any overflow in math operation.
Parity flag is set to 1 when the number of 1’s in A register is odd.
The three user flags are general purpose flags programmers can be set or reset by the programmer at will.
RS0 and RS1 are two register bank select bits which are used to select the specific register bank of internal RAM.

FLAGS Contd. Select register bank 3 1 1 Select register bank 2 0 1 Select register bank 1 1 0 Select register bank 0 0 0 REGISTER RS1 RS0

8051 FLAG BITS AND THE PSW REGISTER
PSW : It is 8 bits wide but use only 6 bits .There are 4 conditional flags (CY,AC,P & OV) , 2 user-definable flags (PSW.1 & PSW.5) and 2 register bank selector(RS1 & RS0).
CY PSW.7 Carry flag. AC PSW.6 Auxiliary carry flag. F0 PSW.5 Available to the user for general purpose. RS1 PSW.4 Register Bank selector bit 1. RS0 PSW.3 Register Bank selector bit 0. OV PSW.2 Overflow flag. -- PSW.1 User definable bit. P PSW.0 Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of 1 bits in the accumulator. P OV RS0 RS1 F0 AC CY 18H – 1FH 3 1 1 10H – 17H 2 0 1 08H – 0FH 1 1 0 00H – 07H 0 0 0 Address Register Bank RS0 RS1

Problem1: Show the status of the CY, AC, and P flags after the addition of 38H and 2FH in the following instructions. MOV A, #38H ADD A, #2FH Problem2: Show the status of the CY, AC, and P flags after the addition of 9CH and 64H in the following instructions. MOV A, #9CH ADDC A, #64H

INTERNAL RAM
There are 128 bytes of RAM in 8051 and their assigned address are 00H to 7FH.
A total of 32 bytes from location 00 to 1FH are assigned for register banks.
A total of 16 bytes from location 20H to 2FH are assigned for bit addressable read/ write memory.
A total of 80 bytes form location 30H to 7FH are used for normal read/ write storage memory, which is called Scratch Pad.

INTERNAL RAM Contd.

INTERNAL RAM Contd. BANK 0 BANK 1 BANK 2 BANK 3 WORKING REGISTER R0 0 R1 1 R2 2 R3 3 R4 4 R5 5 R6 6 R7 7 NAME ADD NAME ADD R0 18 R1 19 R2 1A R3 1B R4 1C R5 1D R6 1E R7 1F NAME ADD R0 8 R1 9 R2 A R3 B R4 C R5 D R6 E R7 F NAME ADD R0 10 R1 11 R2 12 R3 13 R4 14 R5 15 R6 16 R7 17

INTERNAL RAM Contd. 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 BYTE ADD BIT ADDRESS B I T A D D R E S S A B L E R E G I S T E R BYTE ADD GENERAL PURPOSE 30 7F 07 06 05 04 03 02 01 00 0F 0E 0D 0C 0B 0A 09 08 17 16 15 14 13 12 11 10 1F 1E 1D 1C 1B 1A 19 18 27 26 25 24 23 22 21 20 2F 2E 2D 2C 2B 2A 29 28 37 36 35 34 33 32 31 30 3F 3E 3D 3C 3B 3A 39 38 47 46 45 44 43 42 41 40 4F 4E 4D 4C 4B 4A 49 48 57 56 55 54 53 52 51 50 5F 5E 5D 5C 5B 5A 59 58 67 66 65 64 63 62 61 60 6F 6E 6D 6C 6B 6A 69 68 77 76 75 74 73 72 71 70 7F 7E 7D 7C 7B 7A 79 78

PSW Bits Bank Selection Example: State the contents of the RAM locations after the following program: SETB PSW.4 ; select bank 2 MOV R0,#99H ; load R0 with value 99H MOV R1,#85H ; load R1 with value 85H MOV R2,#3FH ; load R2 with value 3FH MOV R7,#63H ; load R7 with value 63H MOV R5,#12H ; load R5 with value 12H Solution: By default, PSW.3=0 and PSW.4; therefore, the instruction “SETB PSW.4” sets RS1=1 and RS0=0, thereby selecting register bank 2. Register bank 2 uses RAM location 10H-17H. After the execution of the above program we have the following: RAM location 10H has value 99H RAM location 11H has value 85H RAM location 12H has value 3FH RAM location 17H has value 63H RAM location 15H has value 12H 1 1 Bank 3 0 1 Bank 2 1 0 Bank 1 0 0 Bank 0 RS0 (PSW.3) RS1 (PSW.4)

SPECIAL FUNCTION REGISTER
Special Function Register (SFR) are areas of memory that control specific functionality of the 8051 microcontroller.
The SFRs allow the user to access the ports, serial communication, control and access timers, configure the 8051’s interrupt system and power control system.
Some SFRs can be accessed with bit operations also, i.e they are bit addressable Special Function Registers.

SPECIAL FUNCTION REGISTER Contd..
SCON: (Serial Control) SCON is used to configure the behavior of the 8051’s serial port.
SBUF: (Serial Buffer) SBUF is used to send and received data via serial port.
IE: (Interrupt Enable) IE register is used to enable and disable specific interrupt.
IP: (Interrupt Priority) IP register is used to specify the priority of each interrupt.

SPECIAL FUNCTION REGISTER Contd..
PCON: (Power Control) PCON register is used to control the 8051’s power control mode.
TCON: (Timer Control) TCON is used to control the 8051’s timer and counter operation.
TMOD: (Timer Mode) TMOD is used to control the mode of operation of timer and counter.
TL0/TH0: (Timer 0 Low/High )
TL1/TH1: (Timer 0 Low/High )

SPECIAL FUNCTION REGISTER Contd .. 8D Timer 1 High byte TH1 8B Timer 1 low byte TL1 8C Timer 0 high byte TH0 8A Timer 0 low byte TL0 88 Timer/ Counter control TCON 89 Timer/ Counter mode control TMOD 81 Stack pointer SP 99 Serial port data buffer SBUF 98 Serial port control SCON 0D0 Program status word PSW 87 Power control PCON 0B0 Input/output port latch P3 0A0 Input/output port latch P2 90 Input/output port latch P1 80 Input/output port latch P0 0B8 Interrupt priority IP 0A8 Interrupt enable control IE 82 Addressing external moeory DPL 83 Addressing external moeory DPH 0F0 Arithemetic B 0E0 Accumulator A Internal RAM Address (Hex) Function Name

The Stack and Stack Pointer
The Stack is used to store data temporary during any program execution.
The 8 bit Stack Pointer is used to hold an internal Ram address which is called the top of stack.
Generally 8051 used Bank1 of internal Ram as the Stack. So the default Stack pointer address is 07 h.
When data is placed on the stack the SP increments before storing data on the Stack.
When data is retrieved from the Stack, the byte is read from the stack , and then SP decrements.
The Stack is used during PUSH, POP, CALL, RET instruction.

A MICROCONTROLLER DESIGN

Process of memory block selector:
Using simple logic gates :
D7 D0 A0 A11 CS RD WR 4K*8 A12 A13 A14 A15 D7 D0 A0 – A11 MEMR MEMW Logic gate as Decoder

D7 D0 A0 A11 CE OE Vpp 4K*8 A12 A13 A14 A15 D7 D0 A0 – A11 MEMR Vcc 74LS138 as Decoder GND Vcc Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C G2A G2B G1
Using the 74LS138 3-8 decoder:

RD WR EA P3.7 P3.6 PSEN P2.7 P0.0 P0.7 ALE P2.0 AD0 2864 (2764) 8K*8 PROGRAM ROM Vpp OE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 8031 A0 Vcc A12 A8 D7 D0 Connection to External program ROM G CONNECTION WITH EXTERNAL PROGRAM ROM

OFF CHIP ON-CHIP OFF CHIP ON-CHIP OFF CHIP 8031/51 EA=GND 0000 FFFF 8051 EA=Vcc 8052 EA=Vcc 0000 0FFF 1000 FFFF 0000 1FFF 2000 FFFF On chip and off-chip program code Access On chip-off chip ROM

RD WR P3.7 P3.6 PSEN P2.7 P0.0 P0.7 ALE P2.0 AD0 8K*8 DATA ROM Vpp OE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 8051 A0 Vcc A12 A8 D7 D0 8051 Connection to External Data ROM A15 A14 A13 G Connection with external data ROM

EA PSEN P3.7 P3.6 P2.7 P0.0 P0.7 ALE P2.0 8051 8031 Connection to External Data ROM and External program ROM RD WR AD0 8K*8 DATA ROM Vpp OE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 A0 Vcc A12 A8 D7 D0 A15 A14 A13 G 2864 (2764) 8K*8 PROGRAM ROM Vpp OE CE A12 A8 A7 A0 D0 D0 Vcc D7 Connection to External Data ROM and External program ROM

RD WR P3.7 P3.6 PSEN P2.7 P0.0 P0.7 ALE P2.0 AD0 8K*8 DATA RAM OE WE CE A12 A8 A7 A0 D7 D0 AD7 D Q A7 OC 74LS373 8051 A0 A12 A8 D7 D0 8051 Connection to External data RAM G A14 A13 A15 A13 Connection with external data RAM

Programming the Flash

PART 2 INSTRUCTION SET AND PROGRAMMING THE 8051

INSTRUCTION SET OF 8051 MICROCONTROLLER
MOVING DATA INSTRUCTION
LOGICAL OPERATION
ARITHMETIC OPERATION
JUMP AND CALL INSTRUCTION

MOVING DATA INSTRUCTION
There are 28 mnemonics that copy data from a source to a destination, they may be divided in the following three main types.
MOV destination, source
PUSH source or POP destination
XCH destination, source
The following four addressing modes are used to access data.
Immediate addressing mode
Register addressing mode
Direct addressing mode
Indirect addressing mode

IMMEDIATE ADDRESSING MODE
In immediate addressing mode data are transferred in the register directly.
Copy the immediate 16 bit number nn to the DPTR register Copy the immediate data byte n to the Rr register Copy the immediate data byte n to the A register Operation MOV DPTR,#1234h MOV R0,#0A0H MOV A,#0A0H Example 2/24 1/12 1/12 Cycles/ T-state 3 2 2 Bytes MOV DPTR,#nn MOV Rr,#n MOV A,#n Mnemonics

REGISTER ADDRESSING MODE
The data are transferred through register to register using register addressing mode occur between register A and R0 to R7. It is not possible to move the data in between R0 to R7 using register addressing mode.
MOV R5,A MOV A,R0 Example 1 1 Bytes Copy the immediate data byte n to the Rr register Copy the immediate data byte n to the A register Operation 1/12 MOV Rr,A 1/12 MOV A,Rr Cycles/T-state Mnemonics

DIRECT ADDRESSING MODE
In Direct addressing mode all data are moves or transferred through their direct address.
MOV 5CH,# 77H MOV 5CH,77H (location of internal RAM) MOV 0FH,R2 (OFH is R7 of Bank 1) MOV R0, 07H (R7) MOV 90H,A (P1) MOV A, 80H (P0) Example 3 3 2 2 2 2 Bytes 2/24 Copy the data from register Rr to direct address add. MOV add,Rr 2/24 Copy the data from direct address add. to the Rr register MOV Rr,add 1/12 Copy the data from register A to direct address add. MOV add,A 1/12 Copy the data from direct address add. to the A register MOV A,add 2/24 Copy the immediate data byte n to the direct address add MOV add,#n 2/24 Copy the data from direct address add1 to the direct address add2 MOV add1,add2 Operation Cycles/T-state Mnemonics

INDIRECT ADDRESSING MODE
The Indirect addressing mode uses a register to hold the actual address that will finally be used in data moves, the register itself is not the address, but rather the number in the register. In this mode only R0 and R1 register is used, often called a data pointer .
MOV A, @R0 MOV 80H,@R1 MOV @R0,A MOV @R1,80H MOV @R0,#80H Example 1 2 1 2 2 Bytes 2/24 Copy the content of the address in Rp to add MOV add,@RP Cycles/T-state Operation Mnemonics 1/12 Copy the content of the address in Rp to the A register MOV A, @Rp 1/12 Copy the data in A to the address in Rp MOV @Rp,A 2/24 Copy the contents of add to the address in Rp MOV @Rp,add 1/12 Copy the immediate byte n to the address in Rp. MOV @RP,#n

EXTERNAL DATA MOVES
The 8051 always access the external memory using Indirect addressing modes. Where we uses MOVX instruction, which specify the external memory .
MOV R1,#80H MOVX A,@R1 MOV R0,#7FH MOVX @R0,A MOV DPTR,#8000H MOVX A,@DPTR MOV DPTR,#8000H MOVX A,@DPTR Example 1 1 1 1 Bytes 2/24 Copy the content of the external address in Rp to A MOVX A,@Rp Cycles/ T-state Operation Mnemonics 2/24 Copy data from A register to the external address in Rp MOVX @Rp,A 2/24 Copy data from A register to the external address in DPTR MOVX @DPTR,A 2/24 Copy the content of the external address in DPTR to A MOVX A,@DPTR

CODE MEMORY READ-ONLY DATA MOVES
Code Memory Read-Only Data Moves: The 8051 always access the external code memory using Indirect addressing modes. Where we uses MOVC instruction and the A register in conjunction with DPTR or PC, which specify the external code memory .
MOV A,#56H MOV C A,@A+PC MOV DPTR,#1234H MOV A,#56H MOV C A,@A+DPTR Example 1 1 Bytes 2/24 Copy the code byte, found at the ROM address formed by adding A and the DPTR, to A. MOVC A,@A,+DPTR 2/24 Copy the code byte, found at the ROM address formed by adding A and the PC, to A. MOVC A,@A,+PC Cycles/ T-state Operation Mnemonics

DATA EXCHANGE
Exchange instruction actually move data in two directions, form source to destination and destination to source. Here the XCH instruction is used
XCHD A,@R0 XCH A,@R1 XCH A,80H XCH A, R3 Example 1 1 2 1 Bytes 1/12 Exchange the bytes between register A and address add. XCH A,add 1/12 Exchange the bytes between register A and register Rr. XCH A, Rr 1/12 Exchange the bytes between register A and address in Rp XCH A,@Rp 1/12 Exchange the lower nibble between register A and the address in Rp XCHD A,@Rp Cycles/ t-state Operation Mnemonics

PUSH AND POP
Push opcode copies data from the source address to stack.
Pop opcode copies data from the stack to the destination address.
Cycles/ t-state Bytes Example Operation Mnemonics 2/24 2 Pop 01h Copy the data from the internal RAM address contained in SP to add, and decrement the SP. POP add 2/24 2 Mov 81h,#30h Mov Ro,#0ACh Push 00h Increment sp, copy the data in add to the internal RAM address contained in SP PUSH add

STACK IN THE 8051: When the 8051 is powered up , the SP register contains value 07 i.e RAM location 08 is the first location being used for the stack by the 8051.
PUSH: The storing of a CPU register in the stack is called a PUSH.
EX. MOV R6,#25H MOV R1,#12H MOV R4,#0F3H PUSH 6 PUSH 1 PUSH 4 Start SP = 07 Start SP = 08 Start SP = 09 Start SP = 0A After PUSH 6 After PUSH 1 After PUSH 4 0B 0A 09 08 25 0B 0A 09 08 25 12 0B 0A 09 08 25 12 F3 0B 0A 09 08

POP: The loading the contents of the stack back into a CPU register is called a POP. EX. POP 4 ;POP stack into R4 POP 1 ;POP stack into R1 POP 6 ;POP stack into R6 Start SP = 0B Start SP = 0A Start SP = 09 Start SP = 08 6C 76 F9 54 0B 0A 09 08 6C 76 F9 0B 0A 09 08 6C 76 0B 0A 09 08 6C 0B 0A 09 08 After P0P 3 After POP 5 After POP 2

BIT LEVEL DATA MOVE
The bit level data move opcodes operate on any addressable RAM or SFR bit.
NOTE: only carry Flag will be affected. Cycles/ t-state Bytes Example Operation Mnemonics 2/24 2 MOV 7Fh,C Copy the carry flag to the address bit. MOV b ,C 1/12 2 MOV C,7Fh Copy the address bit to the carry flag. MOV C, b

PROGRAM
1. write an ALP in 8051 to transfer a data from internal RAM location 30h to external RAM location 8000h.
2. write an ALP in 8051 to transfer a data from external RAM location 9000h to external RAM location 8000h.
3. write an ALP in 8051 to transfer a block of data. 10 data are available in internal RAM location starting from 30h, Copy those data to external RAM starting from 8000h.
4. write an ALP in 8051 to transfer a block of data. 10 data are available in external RAM location starting from 9000h, Copy those data to external RAM starting from 8000h.
5. write an ALP in 8051 to convert a decimal code to equivalent ASCII code.

LOGICAL OPERATION
Logical operation includes AND ,OR, XOR, Complement and Clear operation.
LOGICAL AND OPERATION
Cycles/ t-state Bytes Example Operation Mnemonics 3 2 1 1 2 2 AND each bit of RAM address with the same bit of immediate data n , put the result in RAM AND each bit of A with the same bit of direct RAM address, put the result in RAM. AND each bit of A with the same bit of register pointer Rp, put the result in A. AND each bit of A with the same bit of register Rr, put the result in A. AND each bit of A with the same bit of direct RAM address, put the result in A. AND each bit of A with the same bit of immediate date n, put the result in A. ANL add,#n ANL add,A ANL A,@Rp ANL A,Rr ANL A,add ANL A, #n 2/24 ANL 7fh,#n 1/12 ANL 90h,A 1/12 ANL A,@R0 1/12 ANL A,R0 1/12 ANL A,80h 1/12 ANL A, #60h

LOGICAL OR OPERATION Cycles/ t-state Bytes Example Operation Mnemonics 2/24 3 ORL 7fh,#n OR each bit of RAM address with the same bit of immediate data n , put the result in RAM ORL add,#n 1/12 2 ORL 90h,A OR each bit of A with the same bit of direct RAM address, put the result in RAM. ORL add,A 1/12 1 ORL A,@R0 OR each bit of A with the same bit of register pointer Rp, put the result in A. ORL A,@Rp 1/12 1 ORL A,R0 OR each bit of A with the same bit of register Rr, put the result in A. ORL A,Rr 1/12 2 ORL A,80h OR each bit of A with the same bit of direct RAM address, put the result in A. ORL A,add 1/12 2 ORL A, #60h OR each bit of A with the same bit of immediate date n, put the result in A. ORL A, #n

LOGICAL XOR OPERATION Cycles/ t-state Bytes Example Operation Mnemonics XRL add,#n XRL add,A XRL A,@Rp XRL A,Rr XRL A,add XRL A, #n 2/24 3 XRL 7fh,#n XOR each bit of RAM address with the same bit of immediate data n , put the result in RAM 1/12 2 XRL 90h,A XOR each bit of A with the same bit of direct RAM address, put the result in RAM. 1/12 1 XRL A,@R0 XOR each bit of A with the same bit of register pointer Rp, put the result in A. 1/12 1 XRL A,R0 XOR each bit of A with the same bit of register Rr, put the result in A. 1/12 2 XRL A,80h XOR each bit of A with the same bit of direct RAM address, put the result in A. 1/12 2 XRL A, #60h XOR each bit of A with the same bit of immediate date n, put the result in A.

COMPLEMENT OPERATION NOTE: No flags are affected by the byte level logical operations unless the direct RAM address is the PSW. Cycles/ t-state Bytes Example Operation Mnemonics 1/12 1 CPL A Complement each bit of A, CPL A 1/12 1 CLR A Clear each bit of A register to 0. CLR A

BIT LEVEL LOGICAL OPERATION
Bit level logical operation also includes AND, OR and Complement operation.
Set the address bit to 1 Set the carry flag to 1 Clear the address bit to 0 Clear the carry flag to 0 Complement the address bit Complement the Carry Flag OR C and complement of the address bit, put the result in C OR C and the address bit, put the result in C AND C and complement of the address bit, put the result in C AND C and the address bit, put the result in C Operation SETB 20H SETB C CLR 81H CLR C CPL 81H CPL C ORL C,/80H ORL C,70H ANL C,/80H ANL C,70H Example 2 1 2 1 2 1 2 2 2 2 Bytes 1/12 1/12 1/12 1/12 1/12 1/12 2/24 2/24 2/24 2/24 Cycles/ t-state SETB b SETB C CLR b CLR C CPL b CPL C ORL C,/b ORL C,b ANL C,/b ANL C,b Mnemonics

ROTATE AND SWAP INSTRUCTION SWAP A RRC A RR A RLC A RL A Example Interchange the nibble of register A Rotate the A register and C Flag one bit position to the right Rotate the A register one bit position to the right Rotate the A register and C Flag one bit position to the left Rotate the A register one bit position to the left OPERATION 1 1 1 1 1 Bytes 1/12 RRC A 1/12 SWAP A 1/12 RR A 1/12 RLC A 1/12 RL A Cycles/ t-state MNEMONICS

ARITHMETIC OPERATION
Arithmetic operation includes the basic four operation Addition, Subtraction, Multiplication, Division, Incrementing and Decrementing operation .
Cycles/ t-state Bytes Example OPERATION MNEMONICS 1 1 2 1 1 INC DPTR INC @R0 INC 80h INC R5 INC A Add a 1 to the 16 bit DPTR register. Add a 1 to the content of memory address in Rp Add a 1 to the content of the direct memory address. Add a 1 to the Rr register Add a 1 to the A register INC DPTR INC @Rp INC add INC Rr INC A 2/24 1/12 1/12 1/12 1/12

DECREMENTING OPERATION NOTE: No math flags are affected in increment and decrement operation. Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 DEC @R1 Subtract a 1 to the content of memory address in Rp DEC @Rp 1/12 2 DEC 20h Subtract a 1 to the content of the direct memory address. DEC add 1/12 1 DEC R4 Subtract a 1 to the Rr register DEC Rr 1/12 1 DEC A subtract a 1 to the A register DEC A

ADDITION OPERATION Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 ADD A,@R1 Add A with the content of memory address in Rp, put the result in A. ADD A,@Rp 1/12 2 ADD A, 80h Add A with the content of the direct address, put the result in A. ADD A,add 1/12 1 ADD A,R6 Add A with the content of register Rr, put the result in A. ADD A,Rr 1/12 2 ADD A,#0a0h Add A with the immediate numberr, put the result in A. ADD A,#n

ADDITION OPERATION Note: In addition operation all math flag will change. Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 ADDC A,@Rp Add A with the content of memory address in Rp and the carry flag, put the result in A. ADDC A,@Rp 1/12 2 ADDC A,add Add A with the content of the direct address and the carry flag, put the result in A. ADDC A,add 1/12 1 ADDC A,Rr Add A with the content of register Rr and the carry flag, put the result in A. ADDC A,Rr 1/12 2 ADDC A,#n Add A with the immediate numberr and the carry flag, put the result in A. ADDC A,#n

SUBTRACTION OPERATION NOTE: All math flag will be affected. Cycles/ t-state Bytes Example OPERATION MNEMONICS 1/12 1 SUBB A, @R1 Subtract the content of the address in Rp and the carry flag from A, put the result in A. SUBB A, @Rp 1/12 1 SUBB A,R0 Subtract Rr and the carry flag from A, put the result in A. SUBB A,Rr 1/12 2 SUBB A,50h Subtract the content of address and the carry flag from A, put the result in A. SUBB A,add 1/12 2 SUBB A,#40h Subtract immediate number n and the carry flag from A, put the result in A. SUBB A,#n

ADDITION AND DIVISION OPERATION NOTE: In multiplication and division operation carry flag always set to 0, and the Ov flag will be set. Cycles/ t-state Bytes Example OPERATION MNEMONICS 4/48 1 DIV AB Divide A by B, put the integer part of quotient in register A, and the integer part of the reminder in B DIV AB 4/48 1 MUL AB Multiply A by B, put the lower byte of the product in A, put the higher byte of the product in B. MUL AB

JUMP AND CALL INSTRUCTION
Jump instruction are divided into three category
Bit Jump
Byte Jump
Unconditional Jump
1. BIT JUMP
Jump relative if the addressable bit is set to 1,and clear the addressable bit JBC b,radd Jump relative if the addressable bit is reset to 0 JNB b,radd Jump relative if the addressable bit is set to 1 JB b,radd Jump relative if the carry flag is reset to 0 JNC radd Jump relative if the carry flag is set to 1 JC radd Operation Mnemonics

BYTE JUMP Jump to the relative address if A is not 0 JNZ radd Jump to the relative address if A is 0 JZ radd Decrement thedirect address by 1 and jump to the relative address if the result is not 0. DJNZ add,radd Decrement the Rn by 1 and jump to the relative address if the result is not 0. DJNZ Rn,radd Compare the contents of the address in Rp with the immediate data, if they are not equal then jump to the relative address CJNE @Rp,#n,radd Compare the Rn with the immediate data, if they are not equal then jump to the relative address CJNE Rn,#n,radd Compare the A with the immediate data, if they are not equal then jump to the relative address CJNE A,#n,radd Compare the A with the address, if they are not equal then jump to the relative address CJNE A,add,radd operation Mnemonics

UNCONDITIONAL JUMP Not operation NOP Jump to the relative address SJMP radd Jump to the long range address LJMP ladd(a16) Jump to the short range address AJMP sadd(a11) Jump to the address formed by adding A with DPTR JMP @A+DPTR Operation Mnemonics

CALL INSTRUCTION Return from interrupt subroutine. RETI Return from subroutine. RET Call the subroutine located in long address. LCALL ladd(a16) Call the subroutine located in short address. ACALL sadd(a11) OPERATION MNEMONICS

Address Range
Relative address: This is the difference between two 16 bit numbers.
Short address: This address is generated by 11bit address. And maximum range is 2K bytes.
Long address: This address is generated by 16 bit address. And maximum range is 64K bytes.
Short address generation for AJMP instruction. Short address generation for ACALL instruction. A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 1 0 0 0 0 A 8 A 9 A 10 1 0 0 0 1 A 8 A 9 A 10

Calculating short jump address:
1 st byte is the opcode
2 nd byte is the relative address
Target address is relative to the value of PC
Example: Using the following list file, verify the jump forward address calculation.
Line PC OPCODE Mnemonic Operand
01 0000 ORG 0000
02 0000 7800 MOV R0,#0
03 0002 7455 MOV A,#55H
04 0004 6003 JZ NEXT
05 0006 08 INC R0
06 0007 04 AGAIN: INC A
07 0008 04 INC A
08 0009 2477 NEXT: ADD A,#77H
09 000B 5005 JNC OVER
10 000D E4 CLR A
11 000E F8 MOV R0,#A
12 000F F9 MOV R1,#A
13 0010 FA MOV R2,#A
14 0011 FB MOV R3,#A
15 0012 2B OVER: ADD A,#R3
16 0013 50F2 JNC AGAIN
17 0015 80FE HERE: SJMP HERE
18 0017 END

First notice that the JZ and JNC instructions both jump forward. The target address for a forward jump is calculated by adding the PC of the following instruction to the second byte of the short jump instruction, which is called the relative address. In line 4 the instruction “JZ NEXT” has opcode of 60 and operand of 03 at the address of 0004 and 0005. The 03 is the relative address, relative to the address of the next instruction INC R0, which is 0006. By adding 0006 to 3, the target address of the label NEXT, which is 0009, is generated. In the same way for line 9, the “JNC OVER” instruction has opcode and operand of 50 and 05 where 50 is the opcode and 05 the relative address. Therefore, 05 is added to 000D, the address of instruction “CLR A”, giving 12H, the address of label OVER. (b) Solution: In that program list, “JNC AGAIN” has opcode 50 and relative address F2H. When the relative address of F2H is added to 15H, the address of the instruction below the jump, we have 15H +F2H= 07 (the carry is dropped). Notice that 07 is the address of label AGAIN. Look also at “SJMP HERE”, which has 80 FE for the opcode and relative address, respectively. The PC of the following instruction, 0017H, is added to FEH, the relative address, to get 0015H, address of the HERE label (17H+FEH). Notice that FEH is –2 and 17H+(-2)= 15H.

Write a program in 8051 assembly language to transfer 10 numbers in the internal RAM starting from 30H from external RAM, data are stored from memory location 8050H.
MOV DPTR,#8050H
MOV R5,#0AH
MOV R1,#30H
BACK: MOVX A,@DPTR
MOV @R1,A
INC DPTR
INC R1
DJNZ R5,BACK
HERE:SJMP HERE

ASSEMBLER DIRECTIVES
ORG: The ORG directives is used to indicate the beginning of the address.
EQU (equate): This is used to define a constant without occupying a memory location.
Ex. COUNT EQU 25
……… .. ………….
MOV R3,#COUNT
END: This indicates to the assembler the end of the source file.

DATA TYPES & DIRECTIVES
The 8051 micro controller has only one data type of 8 bits & the size of each register is 8 bits. Data may be unsigned or signed.
DB is used to define data, that can be in decimal, binary or ASCII formats.
Ex. ORG 500H ;
DATA1 DB 28 ;Decimal(1C inhex)
DATA2 DB 00110101B ;Binary (35 in hex)
DATA3 DB 39H ;Hex
ORG 510H
DATA4 DB “2591” ;ASCII NUMBER

ASSEMBLY LANGUAGE: By which we command the CPU is called an Assembly language ,it is a series of statements or lines.
FEATURES OF ASSEMBLY LANGUAGE:
One instruction appears per line
Labels, which give names to memory locations, start in the first column
Instructions must start in the second column or after to distinguish them from labels
Comments run from some designated comment character to the end of the line
ASSEMBLY LANGUAGE INSTUCTION:
MOV: EX.MOV A,#55H ;Load value 55H into reg. A
MOV R0,A ;Copy contents of A into R0
;(now A=R0=55H)
ADD:EX.ADD A,R7 ;add to A content of R7
;where A=A+R7

CPU to execute an instruction takes a certain number of clock cycles. These clock cycles are referred as ‘Machine Cycles’. The length of the machine cycle depends on the frequency of the crystal oscillator. One machine cycle lasts for 12 oscillator periods. Therefore, to calculate the machine cycle, we take 1/12 of the crystal frequency, then take the inverse. Ex.: for 16 MHz crystal oscillator calculation machine cycle is as followed: 16MHz/12=1.333MHz Machine cycle=1/1.333MHz=0.75microseconds TIME DELAY GENERATION AND CALCULATION

Delay program using 8 bit register
MOV R0,#FFH
HERE: DJNZ R0, HERE
MOV R0,#255
HERE1: MOV R1,#200
HERE: DJNZ R1,HERE
DJNZ R0,HERE1
MOV R0,#FFH
HERE2: MOV R1,#FFH
HERE1: MOV R2,#FFH
HERE: DJNZ R2,HERE
DJNZ R1,HERE1
DJNZ R0,HERE2

Example1: Find the size of the delay in the following program, if the crystal frequency is 11.0592 MHz. MOV A,#55H AGAIN: MOV P1,A ACALL DELAY CPL A SJMP AGAIN ;……………..Time delay DELAY: MOV R3,#200 HERE: DJNZ R3,HERE RET Solution: From Table A-1 in Appendix A, the following machine cycles for each instruction of the DELAY subroutine. Machine cycle DELAY: MOV R3,#200 1 HERE: DJNZ R3,HERE 2 RET 1 Therefore, the total time delay=[(200*2)+1+1]*1.085  s=436.17  s.

Example 2: For a machine cycle of 1.085  s, find the time delay in the following subroutine. DELAY: Machine cycle MOV R2,#200 1 AGAIN: MOV R3,#250 1 HERE: NOP 1 NOP 1 DJNZ R3,HERE 2 DJNZ R2,AGAIN 2 RET 1 For the HERE loop, (4*250)1.085  s= 1085  s. The AGAIN loop repeats the HERE loop 200 times; therefore, 200*1085  s= 217000, if we do not include the overhead. However, the instructions “MOV R3,#250” and “DJNZ R2,AGAIN” at the beginning and end of the AGAIN loop add (3*200*1.085  s)= 651  s to the time delay. As a result we have 217000+651= 217651  s= 217.651 milliseconds for total time delay associated with the above DELAY subroutine.

1. Write a program to get the x value from P1 and send x 2 to P2, continuously
Solution:

ORG 0
MOV DPTR, #300H ; LOAD LOOK-UP TABLE ADDRESS
MOV A, #0FFH ; A=FF
MOV P1, A ; CONFIGURE P1 AS INPUT PORT
BACK: MOV A, P1 ; GRT X
MOVC A, @A+DPTR ; GET X SQUARE FROM TABLE
MOV P2, A ; ISSUE IT TO P2
SJMP BACK ; KEEP DOING IT
ORG 300H
XSQR_TABLE:
DB 0, 1, 4, 9, 16, 25, 36, 49, 64, 81
END
Answer the following questions for this example.
Indicate the content of ROM locations 300 – 309H.
At what ROM locations is the square of 6, and what value should be there?
Assume that P1 has a value of 9: what value is at P2 (in binary)?

Solution:
All values are in hex.
300 = (00) 301 = (01) 302 = (04) 303 = (09)
304 = (10) 4 * 4 = 16 = 10 in hex
305 = (19) 5 * 5 = 25 = 19 in hex
306 = (24) 6 * 6 = 36 = 24H
307 = (31) 308 = (40) 309 = (51)
(b) 306H; it is 24H
© 01010001B which is 51H and 81 in decimal (9 2 = 81).

TIMER/COUNTER Timer: To generate time delay. Counter : To count any external event. Both timer0 & timer1 registers are 16 bit wide. 8051 has 8 – bit architecture. So 16 – bit timer is accessed as two separate registers of low byte (TL0/TL1) & high byte (TH0/TH1). clock source of timer is the 1/12 of the crystal frequency.

Timer 0 register: D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 TH0 TL0 Timer 1register: Timer 1 is same as timer 0 but the high and low bytes referred to as TH1 & TL1. TMOD register: Both timer 0 and timer 1 use the same register,called TMOD, to set the various timer operation modes. M0 M1 C/T GATE M 0 M1 C/T GATE (MSB) (LSB) GATE: Gating control when set.Timer/counter is enabled only while the INTx pin is high and the TRx control pin is set.When cleared ,the timer is enabled whenever the TRx control bit is set. C/T: Cleared for timer operation and set for counter operation. M1: Mode bit 1. M0: Mode bit 0.
M1 M0 Mode Operating Mode
0 0 0 13-bit timer mode
0 1 1 16-bit timer mode
0 2 8-bit auto reload
1 1 3 Split timer mode
EX.: Find the value for TMOD if we want to program timer 0 in mode 2, use 8051 XTAL
for the clock source, and use instructions to start and stop the timer.

XTAL oscillator 12 T0 pin Pin 3.4 C / T = 0 C / T = 1 TR0 Gate INT0 pin Pin 3.2 Timer/counter 0 When GATE=1 in TMOD

TF1 TCON.7 Timer 1 overflow flag.Set by hardware when timer/counter 1 overflows.Cleared by hardware as the processor vectors to the interrupt service routine. TR1 TCON.6 Timer 1 run control bit.Set by software to turn timer/counter 1on/off. TF0 TCON.5 Timer 0 overflow flag.Set by hardware when timer/counter 0 overflows.Cleared by hardware as the processor vectors to the interrupt service routine. TR0 TCON.4 Timer 0 run control bit.Set by software to turn timer/counter 0 on/off. IE1 TCON.3 External interrupt 1 edge flag.Set by CPU when the external interrupt edge(H-to-L transition) is detected.Cleared by CPU when the interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit.Set/cleared by software to specify falling edge/low-level triggered external interrupt. IE0 TCON.1 External interrupt 0 edge flag.Set by CPU when the external interrupt edge(H-to-L transition) is detected.Cleared by CPU when the interrupt is processed. IT0 TCON.0 Interrupt 0 type control bit.Set/cleared by software to specify falling edge/low-level triggered external interrupt. IT0 IE0 IT1 IE1 TR0 TF0 TR1 TF1 (MSB) (LSB) TIMER CONTROL REGISTER (TCON)

MODE 1 16 BIT TIMER/COUNTER MODE 0 13 BIT TIMER/COUNTER XTAL oscillator 12 THX TLX TF TF goes high overflow When FFFF 0 flag C / T = 0 TR XTAL oscillator 12 THX(8 BIT) TLX(5 BIT) TF TF goes high overflow When FF1F 0 flag C / T = 0 TR

Mode 1 programming:
It is a 16 bit timer is; therefore ,it allows values of 0000 to FFFFH to be loaded into the timer registers TL & TH.
After TH and TL are loaded with a 16-bit initial value,the timer must be started.This is done by “SETB TR0” for timer 0.
After the timer is started , it starts to count up.It counts up until it reaches its limit TF(timer flag).This timer flag can be monitored.
After the timer reaches its limit and rolls over, in order to repeat the process the registers TH and TL must be reloaded with the original value, and TF must be reset to 0.
EX. Creating a square wave of 50% duty cycle (with equal position high and low) on the P1.5 bit.Timer 0 is used to generate the time delay.
MOV TMOD,#01 ;Timer 0,mode 1 (16-bit mode)
HERE: MOV TL0,#0F2H ;TL0=F2H, the low byte
MOV TH0,#0FFH ;TH0=FFH, the high byte
CPL P1.5 ;toggle P1.5
ACALL DELAY
SJMP HERE ;load TH,TL again
;----------------delay using timer 0
DELAY:
SETB TR0 ;start the timer 0
AGAIN JNB TF0,AGAIN ;monitor timer flag 0 until
;it rolls over
CLR TR0 ;stop timer 0
CLR TF0 ;clear timer 0 flag
RET

CALCULATION OF TIME DELAY & SQUARE WAVE
GENERATION OF CRYSTAL FREQUENCY 12MHz
MODE1:
In hex:
(FFFF – YYXX+1) * 1microsec, where YYXX are TH, TL initial value respectively (for 12 MHz crystal oscillator).
(b) In decimal:
(65536 – nnnnn) * 1microsec, nnnnn will be converted into hex value.
DELAY=[[{256-(THX+1)}x256 + (256-TLX)]X12] / F osc
Problem 1 : To create a square wave of 50% duty cycle, timer delay 14
microsecond with crystal freq. 12 MHz.
Problem 2: Calculate the actual freq. Generated in problem 1.
Problem 3: What is the possible largest time delay excluding overhead due
to the instruction in the loop.

Delay=(256-TLX)X12/ F osc TL0 (8BIT) TF0 TH0 (8 BITS) TF1 INTERRUPT INTERRUPT PULSE INPUT F/12 TR1 BIT IN TCON MODE 3, TWO 8 BIT TIMER USING TIMER 0 MODE2 AUTO RELOAD OF TL FROM TH XTAL oscillator 12 TL TF TF goes high When FF 0 C / T = 0 TR Overflow flag TH reload

MODE 2 PROGRAMMING:
8 bit timer, range is 00 to FFH to be loaded into the timer register TH
2. After loading copy to TL automatically.
3. Start timer by SETB instruction.
Timer starts to count up by incrementing the TL register up to FFH, rolls over to 00, set the timer flag, TL is reloaded automatically with the original value in TH register.
Clear TF.
EX.: MOV TMOD, #20H
MOV TH1, #5H
SETB TR1
BACK: JNB TF1, BACK
CPL P1.0
CLR TF1
SJMP BACK
Find the freq. Of the square wave generated on pin 1.0 & the smallest
Frequency achievable in this program.

Find the delay generated by timer 0 in the following code, using both of the methods of Figure 9-4. Do not include the overhead due to instructions. CLR P2 . 3 ; clear P2 . 3 MOV TMOD, #01 ; Timer 0, mode 1 (16 – bit mode) HERE: MOV TL0, #3EH ; TL0 = 3E, low byte MOV T01, #0B8H ; TH0 = B8, high byte SETB P2 . 3 ; set high P2 . 3 SETB TR0 ; start the timer 0 AGAIN: JNB TF0, AGAIN ; monitor the timer flag 0 CLR TR0 ; stop the timer 0 CLR TF0 ; clear timer 0 flag for next round CLR P2 . 3 Solution: (a) (FFFF – B83E + 1) = 47C2H = 18370 in decimal and 18370*1.085  s = 19.93145 ms. (b) Since TH – TL = B83EH = 47166 (in decimal) we have 65536 – 47166 = 18370. This means that the timer counts from B83EH to FFFF. This plus rolling over to 0 goes through a total of 18370 clock cycles, where each clock is 1. 085  s in duration. Therefore, we have 18370*1.085  s =19.93145 ms as the width of the pulse. Modify TL and TH in Example above to get the largest time delay possible. Find the delay in ms. In your calculation, exclude the overhead due to the instructions in the loop. Solution: To get the largest delay we make TL and TH both 0. This will count up from 0000 to FFFFH and then roll over to zero. CLR P2 . 3 ; clear P2 . 3 MOV TMOD, #01 ; Timer 0, mode 1 (16 – bit mode) HERE: MOV TL0, # 0 ; TL0 = 0, the low byte MOV TH0, # 0 ; TH0 =0, the high byte SETB P2 . 3 ; set high P2 . 3 SETB TR0 ; start timer 0 AGAIN: JNB TF0, AGAIN ; monitor the timer flag 0 CLR TR0 ; stop timer 0 CLR TF0 ; clear timer 0 flag CLR P2 . 3 Making TH and TL both zero means that the timer will count from 0000 to FFFF, and then roll over to raise the TF flag. As a result, it goes through a total of 65536 states. Therefore, we have delay = (65536-0) x 1. 085  s = 71. 1065 ms.

Assuming that XTAL = 11.0592 MHz, write a program to generate a square wave of 2 kHz frequency on pin P1.5.
Solution:
Here we must toggle the bit to generate the square wave. Look at the following steps.
T = 1 / f = 1 / 2 kHz = 500  s the period of square wave.
1 / 2 of it for the high and low portion of the pulse is 250  s.
250  s / 1.085  s = 230 and 65536 – 230 = 65306 which in hex is FF1AH.
TL = 1A and TH = FF, all in hex. The program is as follows:

MOV TMOD, #10H ; timer 1, mode 1 (16 – bit)
AGAIN: MOV TL1, #1AH ; TL1 = 1A, low byte of timer
MOV TH1, #0FFH ; TH1 = FF, Hi byte
SETB TR1 ; start the timer 1
BACK: JNB TF1, BACK ; stay until timer rolls over
CLR TR1 ; stop timer 1
CPL P1.5 ; comp. P1.5 to get hi, lo
CLR TF1 ; clear timer flag 1
SJMP AGAIN ; reload timer since mode 1
; is not auto-reload

Counters: When C/T=1, in TMOD register the timer is used as a counter and gets its pulses from pin 14 and 15.This pins are called T0 and T1& belongs to port 3. EX. Assuming that clock pulses are fed into pin T1, write a program for counter 1 in mode 2 to count the pulses and display the state of the TL1 count on P2. MOV TMOD,#01100000B MOV TH1,#0 SETB P3.5 AGAIN SETB TR1 BACK MOV A,TL1 MOV P2,A JNB TF1,BACK CLR TR1 CLR TF1 SJMP AGAIN

TH0 TL0 TF0 TR0 Timer 0 External Input Pin 3.4 C / T = 1 Overflow flag TF0 goes high When FFFF 0 Timer/Counter 0 with External Input (Mode 1) TL0 TF0 TR0 Timer 0 External Input Pin 3.4 C / T = 1 Overflow flag TF0 goes high When FF 0 Timer/Counter 0 with External Input (Mode 2) TH0 reload

Assuming that clock pulses are fed into pin T1, write a program for counter 1 in mode 2 to count the pulses and display the state of the TL1 count on P2. Solution: MOV TMOD, #0110000B ; counter 1, mode 2, C/T= 1; external pulses MOV TH1, # 0 ; clear TH1 SETB P3 . 5 ; make T1 input AGAIN: SETB TR1 ; start the counter BACK: MOV A, TL1 ; get copy of count TL1 MOV P2, A ; display it on port 2 JNB TF1, BACK ;keep doing it if TF =0 CLR TR1 ; stop the counter CLR TF1 ; make TF=0 SJMP AGAIN ; keep doing it Notice in the above program the role of the instruction “SETB P3 . 5”. Since ports are set up for output when the 8051 is powered up, we make P3 . 5 an input port by making it high. In other words. We must configured (set high) the T1 pin (pin P3 . 5) to allow pulses to be fed into it. P2 To LEDs P3.5 T1 8051 P2 is connected to 8 LEDs And input T0 to pulses.

8051 SERIAL COMMUNICATION
Serial communication is used for transferring data between two systems located at distances of feet to millions of miles apart.
Data must be converted in serial bits.
To send data using parallel-in serial-out register.
To receive data using serial-in parallel-out register.
5. Protocol has to be maintained between sender and receiver.
Types of serial communication data:
Synchronous:Transfer a block of data.
Asynchronous:Transfer a single byte at a time.
Start and stops bit:In asynchronous serial communication , each character is placed in between start and stop bits. This is called framing.
space Stop bit Goes out last 0 1 0 mark Start bit 1 0 0 0 0 d7 d0 Goes out first Data transfer rate:The rate of data transfer in serial communication is stated in bps.

Transmitter Transmitter Receiver Transmitter Receiver Receiver Receiver Transmitter Receiver Transmitter Simplex Half Duplex Full Duplex Simplex, Half & full duplex Transfers

Methods of Serial Communication
Synchronous &
Asynchronous
The Synchronous method transfers a block of data (characters) at a time while the Asynchronous transfers a single byte at a time. Special IC chips made by many manufacturers for serial data communications, commonly referred to as UART and USART. The 8051 chip has a built-in UART.

8051 CONNECTION TO RS232: RS232 is the most widely used serial I/O interfacing standard. In RS232 1 is represented by –3 to –25 V & 0 is represented by +3 to +25V. For conversion from TTL to RS232 standard, MAX232 IC chip is used. 1 3 4 5 T1 IN R1 OUT T2 IN R2 OUT + C1 C2 + 11 12 10 9 TTL SIDE 15 RS232 side 16 2 6 + C3 + 14 13 7 8 8051 P3.1 TXD P3.0 RXD 10 12 11 11 MAX232 14 13 2 3 DB-9 5 C4

SERIAL COMMUNICATION WITH 8051: Baud rate is to be selected with the help of Timer 1 with auto reload mode. Clock for 8051 UART circuitry: Divide machine cycle by 32 before it is used by timer 1 to set the baud rate. For various baud rates, TH1 must be loaded with the following values: (XTAL = 11.0592 MHz), Why TH1? BAUD RATE TH1 (decimal) TH1(hex) 9600 -3 FD 4800 -6 FA 2400 -12 F4 1200 -24 E8

SBUF register: SBUF is an 8-bit register used solely for serial communication in the 8051.For a byte of data to be transferred via the TXD line, it must be placed in the SBUF register.Similarly it holds the byte of data received by 8051’s RXD line. SCON register: The SCON register is an 8-bit register used to program the start bit,stop bit,and data bits of data framing. R1 T1 RB8 TB8 REN SM2 SM1 SM0 SM0 SCON.7 Serial port mode specifier SM1 SCON.6 Serial port mode specifier SM2 SCON.5 used in mode 2 & 3,set to 1 when bit 9 of received data is 1 and a interrupt is generated. REN SCON.4 Set/cleared by software to enable/disable reception. TB8 SCON.3 transmitted bit 8 in modes 2 & 3, set/cleared by program RB8 SCON.2 received bit 8 in mode 2 & 3, stop bit in mode 1, not used in mode 0. T1 SCON.1 Transmit interrupt flag.Set by hardware at the beginning of the stop bit in mode 1. Must be cleared by software. R1 SCON.0 Receive interrupt flag.Set by hardware halfway through the stop bit time in mode 1.Must be cleared by software.

SM0 SM1 0 0 : Serial mode 0, shift register, baud = f/12 0 1 : Serial mode 1, 8 bit UART, baud = variable 1 0 : 9 bit UART, baud = f/32 or f/64 1 1 : 9 bit UART, baud = variable REN: receive enable bit (SCON.4) When it is high, it allows the 8051 to receive data on the RXD pin, TI: Transmit interrupt (SCON.1) When 8051 finishes the transfer of 8 bit character, TI flag will be high to indicate that it is ready to transfer another byte. RI: Receive interrupt (SCON.0) When 8051 receives data, it places the byte in SBUF register (excluding start and stop bit) and raises RI flag to indicate that a byte is in SBUF to pick up.

Mode 0 : in mode 0 SBUF configures to receive or transmit 8 data bits using RXD pin for both functions. Pin TXD is connected to the internal shift frequency pulse source to supply shift pulses to external circuits. Here the baud rate is fixed at 1/12 of the oscillator frequency.
Mode 1 : In mode 1 8051’s UART becomes a 10 bit full-duplex receiver/transmitter that may receive and transmit data at the same time. Pin RXD receive all data. Pin TXD transmit all data.
10 bit data is configured as a start bit, 8 data bits and a stop bits. A TI flag is set once when all ten bits have been send.
The RI flag is set when it received ten data. Of the original 10 bit start bit is discarded, the 8 data bits go to SBUF register, and stop bit go to RB8 of TCON register.
Timer 1 is used to generate baud rate. Typically timer1 is used in mode 2 as an auto reload mode, which generate the baud frequency.
2 SMOD oscillator frequency
f baud = ------------ X --------------------------
32d 12d X [256 –(TH1)]

Mode 2 : Here 11 bits are transmitted, a start bits, 9 data bits and a stop bits. The ninth data bit is copied from TB8 in SCON during transmit and stored in RB8 of SCON during receive.both start and stop bit are discarded. Baud rate is as follows:
2 SMOD
F baud = ----------- x oscillator frequency
64d
Functions of RI and TI flag will be same as mode 1.
Mode 3 : mode 3 is identical to mode 2except that the baud rate is determined exactly as in mode 1, using timer 1 to generate communication frequency. Baud rate is:
2 SMOD oscillator frequency
f baud = ------------ X --------------------------
32d 12d X [256 –(TH1)]

POWER MODE CONTROLL(PCON) REGISTER
BIT SYMBOL FUNCTION
SMOD Serial baud rate modify bit. Set to 1 by program to
double the baud rate using timer 1 for modes 1, 2 and 3,
cleared to 0 by program to use timer 1 baud rate.
------ not implemented
GF1 General purpose user flag bit 1, se/ cleared by program
GF0 General purpose user flag bit 0, se/ cleared by program
PD Power down bit, set to 1 by program to enter power
down mode.
0 IDL Idle mode bit, set to 1 by program to enter into idle mode
IDL PD GF0 GF1 ---------- --------- -------- SMOD

Programming the 8051 for serial communication
The TMOD register is loaded with the value 20H, indicating the use of timer 1 in mode 2 (8-bit auto-reload) to set the bud rate.
The TH1 is loaded with one of the values of baud rate for serial data transfer (assuming XTAL =11.0592 MHz).
The SCON register is loaded with the value 50H, indicating serial mode 1, where an 8-bit data is framed with start and stop bits.
TR1 is set to 1 to start timer 1.
T1 is cleared by the “CLR T1” instruction.
The character byte to be transferred serially is written into the SBUF register.
The T1 flag bit monitored with the use of the instruction “JNB T1,xx” to see if the next character, go to step 5.

With XTAL = 11.0592 MHz. Find the TH1 value needed to have the following baud rates. (a) 9600, (b) 2400, (c) 1200 Solutions: With XTAL = 11.0592 MHz, we have: The machine cycle frequency of the 8051 = 11.0592 MHz / 12 = 921.6 kHz, and 921.6 kHz / 32 = 28,800 Hz is the frequency provided by UART to timer 1 to set baud rate. (a) 28,800 / 3 = 9600 where – 3 = FD (hex) is loaded into TH1 (b) 28,800 / 12 = 2400 where – 12 = F4 (hex) is loaded into TH1 © 28,800 / 24 = 1200 where – 24 = E8 (hex) is loaded into TH1 Notice that dividing 1/12 th of the crystal frequency by 32 is the default value upon activation of the 8051RESET pin. We can change this default setting. XTAL oscillator 12 32 By UART Machine cycle freq. 921.6 kHz 28800 Hz To timer to set the baud rate

Program for the 8051 to transfer letter “’A” serially at 4800 baud rate. MOV TMOD, # 20H ;timer1, mode 2 MOV TH1,# 0FAh ; MOV SCON,# 50h ; 8bit, 1 stop bit, REN enabled SETB TR1 ; MOV SBUF,#”A” HERE: JNB T1, HERE CLR TI 1. Write a program to transfer the message “FINE” serially at 2400 baud rate, 8 bit data, 1 stop bit. 2. Program 8051 to receive bytes of data serially and put them in P1. Set the baud rate 2400, 8-bit data, 1 stop bit.

Interrupts & Polling
Two ways by which a micro controller can serve several devices.
Interrupt: The program associated with interrupt is called Interrupt
service routine. Many devices can be served by assigning priority, but
not at the same time. In interrupt method the micro controller can ignore
a device request for service.
Polling: In polling, the micro controller continuously monitors the
status of a given device; when the condition is met, it performs the
service. The main disadvantage of polling is that it wastes much of the
micro controller’s time. It is not possible to assign priority and ignore a
device for service since polling method checks all devices in a round-
robin process.

Steps in executing interrupt: After activation of an interrupt, the micro controller goes through the following steps: 1. Finishes the instruction it is executing and saves the address of the next instruction on the stack. 2. Saves the current status of all the interrupts. 3. Jumps to a fixed location in memory called the interrupt vector table that holds the address of the interrupt service routine. 4. The micro controller gets the address of the ISR from the interrupt vector table, jumps to it and starts to execute it. 5. After executing RETI instruction, the micro-controller returns to the place from where it was interrupted and starts to execute from that address.

INTERRUPT PROGRAMMING: An interrupt is an external event that interrupts the micro controller to inform it that a device needs its service.The 8051 has 6 interrupts, 5 of which are user-accessible.
Reset: When this reset pin is activated, the 8051 jumps to address location 0000.
2. Two interrupts are set aside for the timers: One for timer 0 and one for timer 1.Memory locations 000BH and 001BH in the interrupt vector table belong to timer 0 and timer 1 respectively.
3. Two interrupts are set aside for external hardware interrupts.Memory locations 0003H and 0013H in the interrupt vector table belong to INT0 and INT1 respectively.
4. Serial communication has a single interrupt that belongs to both receive and transfer.The interrupt vector table location 0023H belongs to this interrupt.

EX0 ET0 EX1 ET1 ES ET2 --- EA D7 D0 IE REGISTER EA IE.7 Disable all interrupts.If EA=0, no interrupt is acknowledged.If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. -- IE.6 Not implemented, reserved for future use.* ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt (8952). ES IE.4 Enables or disables the serial port interrupt. ET1 IE.3 Enables or disables timer 1overflow interrupt. EX1 IE.2 Enables or disables external interrupt 1. ET0 IE.1 Enables or disables timer 0 overflow interrupt. EX0 IE.0 Enables or disables external interrupt 0. * User software should not write 1s to reserved bits.These bits may be used in future Flash micro controllers to invoke new features.

0023 Serial COM interrupt (R1 and T1) 001B Timer 1 interrupt (TF1) P3.3 (13) 0013 External hardware interrupt 1 (INT1) 000B Timer 0 interrupt (TF0) P3.2 (12) 0003 External hardware interrupt 0 (INT0) 9 0000 Reset pin ROM Location (Hex) Interrupt Interrupt Vector Table for the 8051

Write a program to create a square wave that has a high portion of 1085 micro second and a low portion of 15 micro second. Use Timer1. ORG 0000H LJMP MAIN ORG 001BH LJMP ISR_T1 ORG 0040H MAIN: MOV TMOD,#10H ;timer1, mode 1 MOV P0,#0FFH MOV TL1,#18H MOV TH1,#0FCH MOV IE,#88H ;enable timer 1 interrupt SETB TR1 BACK: MOV A,P0 MOV P1,A SJMP BACK ISR_T1: CLR TR1 CLR P2.1 ; start of low portion MOV R2,#4H HERE: DJNZ R2, HERE MOV TL1, #18H MOV TH1,#0FCH SETB TR1 SETB P2.1 RET1 END Write a program to generate a square wave of 100 Hz frequency on pin 1.4 using interrupt for timer 0.XTAL = 12 MHz.

External interrupt: There are two activation levels for the external hardware interrupts. 1.Level triggered: In level triggered mode, INT0 and INT1 pins are normally high and if a low level signal is applied to them, it triggers the interrupt. Must be held in low state until the start of execution of ISR. Must be removed before RETI. IE0 (TCON.1) 0003 1 0 Level-triggered INT0 (Pin 3.2) IE1 (TCON.3) 0013 1 0 Level-triggered INT1 (Pin 3.3) 0 1 Edge-triggered Edge-triggered IT0 IT1

IT0 TCON.0 Interrupt 0 type control bit IE0 TCON.1 Interrupt 0 edge flag IT1 TCON.2 Interrupt 1 type control bit IE1 TCON.3 Interrupt 1 edge flag TR0 TCON.4 Timer 0 run control bit TF0 TCON.5 Timer 0 overflow flag TR1 TCON.6 Timer 1 run control bit TF1 TCON.7 Timer 1 overflow flag Edge triggered: To make the interrupts edge triggered interrupts,we must program the bits (IT0 AND IT1) of the TCON register. For edge triggered interrupt, source must be held high at least one m/c cycle and then held low for at least one m/c cycle. IT0 IE0 IT1 IE1 TR0 TF0 TR1 TF1 D7 D0

Problem1: Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low , it should turn on an LED which is connected to pin P1.3. It should stay on for a fraction of a second. Problem2: Write the same program using edge triggered interrupt. What difference will you observe if you run the two programs using a switch.

SERIAL COMMUNICATION INTERRUPT: Serial interrupt is invoked using TI or RI flags and interrupt vector table at 0023h. *Clear RI/TI flag before RETI instruction. Problem: Write a program in which the 8051 gets data from P1 and sends it to P2 continuously while incoming data from serial port is sent to P0. XTAL = 12 MHz, baud rate 9600. TI RI 0023H Serial interrupt is invoked by TI or RI flags

IP REGISTER (bit addressable) PT2: Timer 2 int. priority bit PS: Serial port int. priority bit PT1: Timer 1 int. priority bit PX1: External int.1 priority bit PT0: Timer 0 int. priority bit PX0: External int.0 priority bit Problem: To make timer int. 1 highest priority, what will be the value in IP register. What will be the sequence in which the interrupts are serviced. PX0 PT0 PX1 PT1 PS PT2 ----- -----

INTEGRATED CIRCUIT TO BUILD AN MICROCONTROLLER BASED EMBEDDED SYSTEM
Interfacing with external memory.
Interfacing with external I/O port.
Interfacing with seven segment display.
Interfacing with LCD.
Interfacing with keyboard.

Memory address decoding :
CPU provides the address of the data desired.
Decoding circuitry locates the selected memory block.
Methods of decoding the address:
CS pin of memory chips must be activated.
Data bus of CPU connected to the data pins of memory chip.
Control signals RD connected with OE (o/p enable) and WR connected with WE (write enable) of memory chip.

8 2 5 5 A PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Interfacing with 8255A

10 K +5V Interfacing with LCD Two Line X 20 Character Intelligent LCD Display +5V 1 2 3 14 13 12 11 10 9 8 7 5 4 6 Enable High EN
P2.2
P2.0
P2.1
1 P1.0
2 P1.1
3 P1.2
4 P1.3
5 P1.4
6 P1.5
7 P1.6
8 P1.7
D7 D6 D5 D4 D3 D2 D1 D0 R/W RS G

RS, register select: If RS=0, the instruction command code register is selected, allowing the user to send a command such as clear display, cursor at home, etc. if RS=1 the data register is selected, allowing the user to send data to be displayed on the LCD. R/W, read/write: R/W=1 when reading; R/W=0 when writing. E, enable: When data is supplied to data pins, a high-to-low pulse must be applied to this pin in order for the LCD to latch in the data present at the data pins. This pulse be a minimum of 450 ns wide. D0 – D7: To display letters and numbers, we send ASCII codes for the letters A – Z, and a – z, and numbers 0 – 9 to these pins while making RS=1. We also use RS=0 to check the busy flag bit to see if the LCD is ready to receive information. It is recommended to writing any data to the LCD.

The 8 bit data bus DB7 14 The 8 bit data bus DB6 13 The 8 bit data bus DB5 12 The 8 bit data bus DB4 11 The 8 bit data bus DB3 10 The 8 bit data bus DB2 9 The 8 bit data bus DB1 8 The 8 bit data bus DBO 7 Enable (active high) E 6 R/W=0 write, R/W=1 read R/W 5 R=0 command register, R=1 data register RS 4 Power supply to control contrast Vee 3 +5v power supply Vcc 2 Ground Vss 1 DESCRIPTION SYMBOL PIN

80h Force cursor to beginning of 1 st line C0h force cursor to beginning of 2 nd line B/F=1/0 busy/notbusy Current address BF 1 0 DL=1/0;8/4 bit per character N=1/0; 2/1 rows of character F=1/0; 5x10/5x7 dots per character 0 0 F N DL 1 0 0 0 0 S/C=1/0 screen/cursor R/L=1/0; shift one space R/L 0 0 R/L S/C 1 0 0 0 0 0 D=1/0; screen on/off, C=1/0; cursor on/off, B=1/0;blink/notblink B C D 1 0 0 0 0 0 0 S=1/0;shift screen /cursor I/O=1/0; cursor R/L, screen L/R S I/O 1 0 0 0 0 0 0 0 clear home curser only 0 1 0 0 0 0 0 0 0 0 Clear LCD and memory home curser 1 0 0 0 0 0 0 0 0 0 FUNCTION D0 D1 D2 D3 D4 D5 D6 D7 R/W RS

Write a program to display ARDENT in a LCD screen.
ORG 0000H
MOV DPTR,#CONF
ACALL CONF_DISP
MOV DPTR,#MSG1
ACALL DISPLAY
HERE: SJMP HERE
CONF:
DB 38H,0EH,06H,01H,C0H,FFH
MSG1:
DB: 41H,52H,44H,45H,4EH,54H,FFH
CONF_DISP:
CLR A
MOVC A,@A+DPTR
INC DPTR
CJNE A,#FFH,COMD
RET
COMD:
ACALL COMNWRT
ACALL DELAY
SJMP CONF_DISP

DISPLAY:
CLR A
MOVC A,@A+DPTR
INC DPTR
CJNE A,#FFH,DATA
RET
DATA:
ACALL DATAWRT
ACALL DELAY
SJMP DISPLAY
COMNWRT:
MOV P1,A
CLR P2.0
CLR P2.1
SETB P2.2
NOP
NOP
CLR P2.2
RET

DATAWRT:
MOV P1,A
SETB P2.0
CLR P2.1
SETB P2.2
NOP
NOP
CLR P2.2
RET
DELAY:
MOV R1,#50H
HERE2: MOV R2,#FFH
HERE1: DJNZ R2,HERE1
DJNZ R1,HERE2
RET

INTERFACING A STEPPER MOTOR 31 A 40 9 T 8 9 P2.3 18 C P2.4 5 P2.5 19 1 P2.6 LS373 LATCH ULN 2803A STEPPER MOTOR +12V +5V

Full step operation with one coil energized Full step operation with two coil energized 1 0 0 0 4 0 1 0 0 3 0 0 1 0 2 0 0 0 1 1 D C B A STEP 1 0 0 1 4 1 1 0 0 3 0 1 1 0 2 0 0 1 1 1 D C B A STEP

Half step operation with two coil energized 1 0 0 1 8 1 0 0 0 7 1 1 0 0 6 0 1 0 0 5 0 1 1 0 4 0 0 1 0 3 0 0 1 1 2 0 0 0 1 1 D C B A STEP

Write a program to run a stepper motor in full step configuration.
MOV A,#66H
BACK: MOV P2,A
RR A
ACALL DELAY
SJMP BACK
DELAY:
MOV R2,#50H
H1: MOV R3,#FFH
H2: DJNZ R3,H2
DJNZ R2,H1
RET

Interfacing With ADC
• Input:
• analog signal with a voltage
e.g., pressure, light intensity, temperature,
sound
• Output
• digital value representing the voltage
• 8-bit, 10-bit, 12-bit, 16-bit, 24-bit etc
depends on the specific ADC's precision

Purposes of ADC
• Digitize a signal
• The world is analog; computer is digital
=> bridge the real world & computer
• Benefits
• no more noise due to processing
• can be stored/retrieved like any data
• separate timing handling from processing

ADC0808: Multi-(analog)-channel
Easy interface to all microprocessors
Operates with 5 VDC
Adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to 5V input range with single 5V power supply
Outputs meet TTL voltage level specifications

Pin Description

Pin Description contd.
• IN0..IN7: analog input channels
• SC, EOC: (=WR, INTR)
start conv, end-of-conv
• OE: (=RD) output enable
• C B A : 3-bit channel select
• ALE: clock for latching CBA
Do-D7: digital output

Analog Channel Selection

Timing Diagram

Interfacing 8051 With ADC0809

Pin Connection between 8051 and ADC0809
ALE BIT P2.4
OE BIT P2.5
SC BIT P2.6
EOC BIT P2.7
ADDR_A BIT P2.0
ADDR_B BIT P2.1
ADDR_C BIT P2.2
DATA P1

Assembly Program
ORG 0000H
SETB P2.7 ;configure P2.7 as input
;port pin (EOC)
CLR P2.4 ;clear ALE
CLR P2.6 ;clear SC (start conversion)
CLR P2.5 ;clear OE (output enable)
BACK: CLR P2.2 ;ADDR_C
CLR P2.1 ;ADDR_B (select channel=1)
SETB P2.0 ;ADDR_A
ACALL DELAY
SETB P2.4 ; latch address (set ALE)
ACALL DELAY

Assembly Program contd.
SETB P2.6 ;start conversion (set SC)
ACALL DELAY
CLR P2.4 ;clear ALE
CLR P2.6 ; clear SC
HERE: JB P2.7, HERE ; check EOC
HERE1: JNB P2.7, HERE1 ;check EOC
SETB P2.5 ;set OE
ACALL DELAY
MOV A, P1 :save data in A register
CLR P2.5 :clear OE
SJMP BACK

Interfacing with Seven segment decoder a b c d e f g Segment pattern a b c d e f g Common cathode Segment circuit

Connection with 8051(CA)

Connection with 8051(CC)

67 98 9 7F 80 8 07 F8 7 7D 82 6 6D 92 5 66 99 4 4F B0 3 5B A4 2 06 F9 1 3F C0 0 Data for CC .gfedcba(d7-d0) Data for CA .gfedcba(d7-d0) Display

Program in CA Mode
HERE: MOV P2,#0C0H
ACALL DELAY
MOV P2,#0F9H
ACALL DELAY
MOV P2,#0A4H
ACALL DELAY
MOV P2,#0B0H
ACALL DELAY
MOV P2,#99H
ACALL DELAY
MOV P2,#92H
ACALL DELAY
MOV P2,#82H
ACALL DELAY

Program in CA Mode (CONTD.)
MOV P2,#0F8H
ACALL DELAY
MOV P2,#80H
ACALL DELAY
MOV P2,#98H
ACALL DELAY
SJMP HERE

Program in CC Mode
HERE: MOV P2,#3FH
ACALL DELAY
MOV P2,#06H
ACALL DELAY
MOV P2,#5BH
ACALL DELAY
MOV P2,#4FH
ACALL DELAY
MOV P2,#66H
ACALL DELAY
MOV P2,#6DH
ACALL DELAY
MOV P2,#7DH
ACALL DELAY

Program in CC Mode (CONTD.)
MOV P2,#07H
ACALL DELAY
MOV P2,#7FH
ACALL DELAY
MOV P2,#67H
ACALL DELAY
SJMP HERE

Seven-segment Display circuit Used for Svnseg Program +5V a b c d e f g Display 1 a b c d e f g Display 1 a b c d e f g Display 1 a b c d e f g Display 1 Q a Q b Q c Q d Q e Q f Q g Chose R for brightness Q 1 Q 2 Q 3 Q 4 cc cc cc cc 7 P1.6 6 P1.5 5 P1.4 4 P1.3 3 P1.2 2 P1.1 1 P1.0 12 P3.2 13 P3.3 14 P3.4 15 P3.5 Q 1 – Q 4 B > 1000 8031

Program to display
HERE: SETB P3.5
MOV P1,#06H
SETB P3.4
MOV P1,#5BH
SETB P3.3
MOV P1,#4FH
SETB P3.2
MOV P1,66H
ACALL DELAY
SJMP HERE

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