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    2 data preparation process 2 data preparation process Presentation Transcript

    • Day 2Data Preparation Process Session Speaker Ajaya Kumar.s 1
    • PEMP VSD531Session objectivesAfter completing this session, students will be able• To understand the physical design flow• To understand the need for physical design• To know about the tools used for physical design ©M.S.Ramaiah School Of Advanced Studies 2
    • PEMP VSD531Session Topics• Detailed Physical Design Flow• Foundry Files, Parameters, Rules and Guidelines• Processing the Cells ©M.S.Ramaiah School Of Advanced Studies 3
    • PEMP VSD531 Physical Design Input DataTypes of data that are required to start a physical design are• Technology and library files• Circuit description of the design in the form of netlist representation• Timing requirements or design constraints• Floorplan or the physical layout structure ©M.S.Ramaiah School Of Advanced Studies 4
    • PEMP VSD531 Technology and library files• Technology File (tf)• Library Exchange Format (LEF)• Design Exchange Format (DEF)• Physical library (PLIB)• Physical Design Exchange Format (PDEF) ©M.S.Ramaiah School Of Advanced Studies 5
    • PEMP VSD531 Technology and library files Cont…• Cell Library Format File (CLF)• Advanced Library Format (ALF)• Top Design Format File (TDF)• Table Look up (TLU)• Interconnect Technology Files (ITF) ©M.S.Ramaiah School Of Advanced Studies 6
    • PEMP VSD531 Technology rule basics• Manufacturing grid• Routing grid• Standard cell placement tile• Routing layer definition• Placement and routing blockage layer definition• Via definition• Conducting layer density rule• Metal layer slotting rule• Routing layer physical profile• Antenna definition• Fringe Cap Section• Place and Route Rule Section ©M.S.Ramaiah School Of Advanced Studies 7
    • PEMP VSD531 Technology rule basics Cont..Manufacturing grid : Manufacturing grid is determined by the smallest geometry that a semiconductor foundry can process. All drawn geometries during physical design must snap to this manufacturing grid.Routing grid Routing grids or tracks are used by physical synthesis and place-and-route tools during detail routing. The routing tracks can be grid-based, gridless based, or subgrid-based.Standard cell placement tile Standard cell placement tile is used during the placement phase. The placement tile is defined by one vertical routing track and the standard cell height. ©M.S.Ramaiah School Of Advanced Studies 8
    • PEMP VSD531 Technology rule basics Cont..Routing layer definition Routing layer definition is used to define the layers that are used to route the design. These definitions include wire width, routing pitch, and preferred routing direction such as vertical, horizontal, or diagonal.Placement and routing blockage Placement and routing blockage layer definitions are internal to physical design tools and are used to define “keep-out” regions for standard cell placement and routing.Via definition Via definition defines the layer, size, and type for connection between overlapping geometries of conductor for different conductive layers. This cut layer, or via, can be a single via, stacked via, or array of via. ©M.S.Ramaiah School Of Advanced Studies 9
    • PEMP VSD531 Technology rule basics Cont..Conducting layer density Conducting layer density rule defines the percentage of area of the chip that is required for processes that are using Chemical Mechanical Polishing (CMP) for each physical layer in the design.Metal layers slotting Configuration of metal layers slotting rule defines the minimum layer width that may need to have slotting features (i.e. a cut inside a wide routing layer). This rule varies between foundries and is used to limit mechanical stress for a given conducting layerPhysical profile Physical profile for each layer is used to define and include conductor thickness, height, and interlayer dielectric thickness. Definition of the electrical interconnect profile includes resistance and dielectric constants. ©M.S.Ramaiah School Of Advanced Studies 10
    • PEMP VSD531 Technology rule basics Cont..Antenna definition Antenna definition for each layer configures the physical design tools for automatic antenna repair. Antenna phenomena occur during the metallization process when some wires connected to the polysilicon gates of transistors are left unconnected until the upper conducting layers are deposited. A long wire connected to the gate of MOSFT can act as a capacitor or antenna that collects charges during the plasma-etching step. If this energy build-up on the floating transistor gate is suddenly discharged, the transistor could suffer permanent damage due to gate oxide breakdown. ©M.S.Ramaiah School Of Advanced Studies 11
    • PEMP VSD531 Technology rule basics Cont..FringeCap Section A FringeCap section specifies capacitance information for interconnect layers when they are overlapping or parallel to each other. • Capacitance per unit area when objects on different layers overlap (interfringe) • Capacitance per unit length when objects on the same layer are separated by the minimum spacing specified in the technology file Layer section (intrafringe) ©M.S.Ramaiah School Of Advanced Studies 12
    • PEMP VSD531 Technology rule basics Cont.. FringeCap Section (Interfringe)Interfringe and Intrafringe FringeCap 4 { number = 4 layer1 = "M2“ layer2 = "M3" minFringeCap = 0.00022 nomFringeCap = 0.00022 maxFringeCap = 0.00022 FringeCap Section (Intrafringe) FringeCap 4 { number = 4 layer1 = "M2" layer2 = "M2" minFringeCap = 0.00017 nomFringeCap = 0.00017 maxFringeCap = 0.00017 } ©M.S.Ramaiah School Of Advanced Studies 13
    • PEMP VSD531 Technology rule basics Cont..Place and Route Rule Section PRRule Section The PRRule section of a technology file defines cell row spacing.Cell Row Spacing When using double-back cell rows in your floorplan, you specify the following row spacing rules: • Between top edge and top edge • Between bottom edge and bottom edge ©M.S.Ramaiah School Of Advanced Studies 14
    • PEMP VSD531 Technology rule basics Cont..Row Spacing Rule for Double-Back CellsRow Spacing Rule for Non-Double-Back Cells ©M.S.Ramaiah School Of Advanced Studies 15
    • PEMP VSD531 Technology rule basics Cont..PitchDefines the predominant separation distance between the centers of objects on the layer. Placeand route tool uses the pitch you specify to generate wire tracks in the unit tile. ©M.S.Ramaiah School Of Advanced Studies 16
    • PEMP VSD531 Technology rule basics Cont..Library Exchange Format (LEF)The Library Exchange Format (LEF) is a method of providing library informationfrom a third-party database to milkyway.LEF defines the elements of an IC process technology and associated library ofcell models and contains library information for a class of designs.It includes:• Layer definition• Via• Placement• Site type, and macro cell definitions ©M.S.Ramaiah School Of Advanced Studies 17
    • PEMP VSD531 Technology rule basics Cont..Tech Library Exchange Format (LEF) ExampleTYPE ROUTING ; DIRECTION HORIZONTAL ; PITCH 0.200 ; OFFSET 0.000 ; HEIGHT 0.5900 ; THICKNESS 0.1800 ; FILLACTIVESPACING 0.300 ; WIDTH 0.09 ; MAXWIDTH 12.0 ; AREA 0.042 RESISTANCE RPERSQ 0.1600000000 ; CAPACITANCE CPERSQDIST 0.0001711111 ACCURRENTDENSITY AVERAGE FREQUENCY 500 WIDTH 0.090 1.000 12.000 ; ©M.S.Ramaiah School Of Advanced Studies 18
    • PEMP VSD531 Technology rule basics Cont..Cell Library Exchange Format (LEF) Example PIN VSSMACRO BUFTHVTD20 DIRECTION INOUT ; CLASS CORE ; USE ground ; FOREIGN BUFTHVTD20 0.000 0.000 ; SHAPE ABUTMENT ; ORIGIN 0.000 0.000 ; PORT SIZE 16.560 BY 3.690 ; LAYER METAL1 ; SYMMETRY x y ; RECT 6.840 -0.310 16.560 0.310 ; SITE core ; RECT 6.580 -0.310 6.840 0.500 ; PIN Z PIN VDD DIRECTION INOUT ;PIN OE USE power ; ANTENNAGATEAREA 1.071 ; SHAPE ABUTMENT ; DIRECTION INPUT ; PORT PORT LAYER METAL1 ; LAYER METAL1 ; RECT 2.490 3.380 16.560 4.000 ; RECT 5.980 1.085 6.180 1.640 ; RECT 2.230 3.190 2.490 4.000 ; RECT 4.935 1.085 5.980 1.245 ; RECT 0.000 3.380 2.230 4.000 ; RECT 4.475 1.085 4.935 1.375 END END VDD ©M.S.Ramaiah School Of Advanced Studies 19
    • PEMP VSD531 Technology rule basics Cont..contact_layer ( "CONT" ); routing_layer ( "METAL1" ) { default_routing_width : 0.16; spacing : 0.18; pitch : 0.41; routing_direction : horizontal; res_per_sq : 7.7e-05; coupling_cap : 9.13e-05; cap_per_sq : 0.0001163; fringe_cap : 6.9e-05; height : 0.89; thickness : 0.3; max_current_density : 14.3; min_area : 0.122; min_enclosed_area : 0.2; min_width : 0.16; spacing_check_style : diagonal; spacing_table ( "fat_spacing" ) { index_1 ( "0, 0.3, 10.001" ); index_2 ( "0, 0.3, 10.001" ); index_3 ( "0, 1" ); values ( "0.18, 0.18", "0.18, 0.22", "0.6, 0.6", "0.18, 0.22","0.18, 0.22","0.6, 0.6", "0.6, 0.6", "0.6, 0.6", "0.6, 0.6" ); } /* end spacing_table */ ©M.S.Ramaiah School Of Advanced Studies 20
    • PEMP VSD531 Technology rule basics Cont..Physical Design Exchange Format (PDEF) Physical Design Exchange Format (PDEF) information defines the elements of an IC design relevant to physical layout, including the netlist and design constraints. ©M.S.Ramaiah School Of Advanced Studies 21
    • PEMP VSD531 Technology rule basics Cont..Advanced Library Format (ALF) define the Signal Electromigration on Interconnectsanalysis LAYER METAL1 { PURPOSE = routing ; LIMIT { CURRENT ave_limit { MEASUREMENT = average ; MAX { HEADER { TEMPERATURE { TABLE { 85 100 105 110 120 125 } } WIDTH { TABLE { 0.16 1 12 } } } TABLE { 0.533 0.316 0.268 0.229 0.168 0.145 3.332 1.973 1.673 1.430 1.051 0.905 39.983 23.681 20.077 17.160 12.613 10.862 } } } CURRENT rms_limit { MEASUREMENT = rms ; MAX { HEADER { TEMPERATURE { TABLE { 105 110 115 } } WIDTH { TABLE { 0.16 0.32 0.64 1 5 12 } } } TABLE { 3.537 3.537 3.537 5.639 5.639 5.639 9.523 9.523 9.523 13.760 13.760 13.760 59.939 59.939 59.939 140.486 140.486 140.486 } } } CURRENT peak_limit { MEASUREMENT = peak ; MAX { HEADER { TEMPERATURE { TABLE { 105 110 115 } } WIDTH { TABLE { 0.16 1 12 } } } TABLE { 5.883 5.883 5.883 36.770 36.770 36.770 441.235 441.235 441.235 } } ©M.S.Ramaiah School Of Advanced Studies 22
    • PEMP VSD531 Technology rule basics Cont..Table Look up (TLU)TLUPlus models are a set of CapTable and ResModel generated by grdgenxo (Start-RCXT) from ITF or provided by the foundry. It contains unit wire caps at differentspacing and widths and unit layer resistance to allow extraction engine look upappropriate values during the extraction.The output of TLUPlus file will be a binary file.• Units of pf and micron (for both ITF and technology files)• Nominal operating condition (for CapTable names only)• Table dimension 5x16 (width vs. spacing)• Grid points are multiples of minimum width and spacing values ©M.S.Ramaiah School Of Advanced Studies 23
    • PEMP VSD531 Technology rule basics Cont..Benefits• Single process description can be used at design and verification stages• Advanced process effects such as metal fill and conformal dielectrics, are directly taken into account in the CapTable generation of TLUPlus• TLUPlus uses more accurate engine to create the cap table than capGen which was used in TLU• Quicker timing closure and quicker time to market ©M.S.Ramaiah School Of Advanced Studies 24
    • PEMP VSD531 Technology rule basics Cont..Interconnect Technology Files (ITF) ITF stands for interconnect technology format. It models advanced processing information like width-and-spacing dependent RPSQ/Etch, temperature coefficients of the second order, which the traditional technology file does not have. comboITF, which is the combination of min/nom/max ITF, cap unit of the CapTable, res unit of the ResModel and mapping file, will provide a means for extraction to calculate RC according to the same ResModel presented in the ITF ©M.S.Ramaiah School Of Advanced Studies 25
    • PEMP VSD531 Technology rule basics Cont..Cell Library Format File (CLF) CLF file function descriptions for cell definition functions used by place and route tool.Cell Definition Functions:The purpose of a CLF file is to provide timing information for timing driven placeand route. The CLF file provides Astro with information about cells in the library.The Synopsys application uses this information during• Pin and blockage extraction• Pad placement• Clock tree synthesis ©M.S.Ramaiah School Of Advanced Studies 26
    • PEMP VSD531 Digital Standard Cell Library DeliverablesN Type Description .doc, .txt Databook / User guide, Layer usage file .sdb, .slib Symbols .db, .lib Synthesis .v Verilog simulation models .vhd VHDL / Vital simulation models .sp HSPICE netlists .rcx Extracted RC netlists for different corners .gds GDSII layout views .drc, .lvs, .erc Report files .lef LEF files .fram, .cel Fram views, layout views and runset files .plib Physical compiler views ©M.S.Ramaiah School Of Advanced Studies 27
    • PEMP VSD531 Physical structure of digital cell VDD The selection of physical structure of digital cell is aimed at providing maximum cell density inW1 digital designs. It is more important to provide minimal area for the most frequently used cells. In general, these are usually NAND cells with two inputs, and D flip-flops W4 Minimum center-to-center distance W3 W2 H dtrackW1 VSS d1 d2 Minimum spacing Minimum width ©M.S.Ramaiah School Of Advanced Studies 28
    • PEMP VSD531 Physical structure of double height digital cell VDD HW1 Symbol VDD W5 Parameter Value L W4 H W3 Cell height 2.88 um W2 H Power rail width W1 0.16 um Vertical grid W2 0.32 umW1 Horizontal grid W3 0.32 um VS S NWell height W4 1.68 um W2 W3 H W5 W4 VDDH to VDDL height (Fig. 8.3) 0.72 umW1 VDD H 29 ©M.S.Ramaiah School Of Advanced Studies
    • PEMP VSD531 Processing CellsActivity Flow ©M.S.Ramaiah School Of Advanced Studies 30
    • PEMP VSD531 Data Preparation Using MilkywayThe Milkyway Environment ©M.S.Ramaiah School Of Advanced Studies 31
    • PEMP VSD531 Data Preparation Using Milkyway Cont…The Milkyway and the data preparation functions can perform several tasksessential for cell library and data preparation, including the following:• Creating cell libraries• Importing cell data• Specifying technology information• Writing technology information to a file• Removing cell hierarchy• Specifying power and ground port types• Optimizing the standard cell layout• Extracting pin and blockage information• Setting place and route boundaries• Defining wire tracks ©M.S.Ramaiah School Of Advanced Studies 32
    • PEMP VSD531 Data Preparation Using Milkyway Cont…Flow for Creating a Milkyway Library From LEF ©M.S.Ramaiah School Of Advanced Studies 33
    • PEMP VSD531 Data Preparation Using Milkyway Cont…Standard Cells wire tracks ©M.S.Ramaiah School Of Advanced Studies 34
    • PEMP VSD531 Data Preparation Using Milkyway Cont…Place and Route Boundary ©M.S.Ramaiah School Of Advanced Studies 35
    • PEMP VSD531 Data Preparation Using Milkyway Cont…Flow for Importing and Exporting a DEF File ©M.S.Ramaiah School Of Advanced Studies 36
    • PEMP VSD531 Design ConstraintsDesign constraints are ASIC design specifications that are applied during logic andphysical synthesis. Each tool attempts to meet two general design constraints • Timing constraints • Design rule constraintsTiming constraints are user-specified and are related to speed, area, and the powerconsumption of the ASIC design.Timing constraints utilized by physical design tools are performance related.The mostbasic timing constraints are as follows • System clock definition and clock delays • Multiple cycle paths • Input and output delays • Minimum and maximum path delays • Input transition and output load capacitance • False paths ©M.S.Ramaiah School Of Advanced Studies 37
    • PEMP VSD531 Timing Constraints Cont..Multiple cycle paths Multiple cycle paths are for ASIC designs that have a non-single cycle clock timing requirement. This directs the physical design tools to avoid optimization of data paths that have non-single clock behavior.Input and output delays Input and output delays are used to constrain the boundary of external paths in an ASIC design. These constraints specify point-to-point delays from external inputs to the first registers and from registers to the outputs of an ASIC design.Minimum and maximum path delays Minimum and maximum path delays provide greater flexibility for physical synthesis tools that have a point-to-point optimization capability. This means that one can specify timing constraints from one specific point (e.g. pin or port) in the ASIC design to another, provided such a path exists between the two specified points ©M.S.Ramaiah School Of Advanced Studies 38
    • PEMP VSD531 Timing Constraints Cont..Input transition and output load capacitance Input transition and output capacitance loads are used to constrain the input slew rate and output capacitance of an ASIC device input and output pins. These constraints have a direct effect on the final ASIC design timing.False paths False paths are used to specify point-to-point non-critical timing either internal or external to an ASIC design. Properly identifying these non critical timing paths has a great impact on physical design tools’ performance. ©M.S.Ramaiah School Of Advanced Studies 39
    • PEMP VSD531 Design Rule ConstraintsDesign rule constraints are imposed upon ASIC designs by requirements specified ina given standard cell library or within physical design tools.Design rule constraints have precedence over timing constraints because they haveto be met in order to realize a functional ASIC design. There are four types of majordesign rule constraints• Maximum number of fan-outs• Maximum transitions• Maximum capacitance• Maximum wire length ©M.S.Ramaiah School Of Advanced Studies 40
    • PEMP VSD531 Design Rule Constraints Cont..Maximum number of fan-outs Maximum number of fan-outs specify the number of destinations that one cell can connect to for each standard cell in the library. This constraint can also be applied at the ASIC design level during the physical synthesis to control the number of connections one cell can make.Maximum transition constraint Maximum transition constraint is the maximum allowable input transitions for each individual cell in the standard cell library. Apart from each element in the standard cell library, this constraint can be applied to a specific net or to an entire ASIC design. ©M.S.Ramaiah School Of Advanced Studies 41
    • PEMP VSD531 Design Rule Constraints Cont..Maximum capacitance constraint Maximum capacitance constraint behaves similarly to maximum transition constraint, but the cost is based on the total capacitance that a particular standard cell can drive any interconnection in the ASIC design. It should be noted that this constraint is fully independent of maximum transition, and therefore, it can be used in conjunction with maximum transition.Maximum wire length constraint Maximum wire length constraint is useful for controlling the length of wire to reduce the possibility of two parallel long wires of the same type. Parallel long wires of the same type may have a negative impact on the noise injection and may cause crosstalk. ©M.S.Ramaiah School Of Advanced Studies 42
    • PEMP VSD531 Detailed Physical Design FlowDesign Specs Fnl. Design • Architectural optimization (timing) • Inter-group buses, bandwidth • Clock, SI, test; validation Synthesis ConstraintsLib.+CWLM Floor-plan & PG • Floorplanning and custom WLMLib.+CWLM • Power distribution (Internal, I/O) Placement • I/O driver, padring design • Board-level timing, SI Physical re-synth • Row definitions • Placement of cells Clock distribution • Congestion analysis Route, scan re-order • Placement-based re-synthesis • Noise minimization, isolation Timing analysis, IPO • Clock distribution Fnl., pwr., SI ECO • Full routing • Scan stitching, re-ordering Reqmts. ERC, DRC, LVS • Full RC back-annotation • Hierarchical timing, electrical and SI analysis and Tape-out ©M.S.Ramaiah School Of Advanced Studies IPO/ECO 43
    • PEMP VSD531 Session Summary• Technology, ckt description, timing and design constraint file are the basic input for the physical design• The format in which the digital libraries are supplied as a design kit in the suitable format wrt EDA tools are studied• Besides being the name for the data preparation tool, Milkyway is the name for the unified database the tool interacts with.• Libraries contain information about design cells, standard cells, macro cells, and so on. They contain physical descriptions, such as metal, diffusion, and polygon geometries. Libraries also contain logical information (functionality and timing characteristics) for every cell in the library. ©M.S.Ramaiah School Of Advanced Studies 44