1 introduction to vlsi physical design

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1 introduction to vlsi physical design

  1. 1. Day 1Introduction to VLSI Physical Design Session Speaker Ajaya Kumar.s 1
  2. 2. PEMP VSD531Session Objectives To understand the Physical design flow To understand the need for Physical design To know about the tools used for physical design To understand the concepts of CMOS process parameters To know the issues of scaling and its effects ©M.S.Ramaiah School Of Advanced Studies 2
  3. 3. PEMP VSD531Session Topics• Technology Evolution• Scaling Issues• Design Principles• Verification and Simulation• Detailed Physical Design Flow• Foundry Files, Parameters, Rules and Guidelines ©M.S.Ramaiah School Of Advanced Studies 3
  4. 4. PEMP VSD531Technology Evolution: Cost and IntegrationDrivers Moore’s Law is about cost Increased integration, decreased cost more possibilities for semiconductor-based products Pentium 4 die shot: 2.2cm ©M.S.Ramaiah School Of Advanced Studies 4
  5. 5. PEMP VSD531Sense of Scale (Scaling) What fits on a VLSI Chip today? State of the art logic chip 0.13mm (2 l) 20mm on a side (400mm2) 0.13mm drawn gate length 0.5μm wire pitch 8-level metal For comparison 32b RISC processor 8K l x 16Kl 0.5mm SRAM (8 l) about 32l x 32l per bit 8K x 16K is 128Kb, 16KB DRAM 64b FP 8l x 16l per bit Processor 8K x16K is 1Mb, 128KB 20mm 32b RISC (40,000 wire pitches) Processor 320,000 l ©M.S.Ramaiah School Of Advanced Studies 5
  6. 6. PEMP VSD531MOS Transistor Scaling (1974 to present) S=0.7 Met Poly [0.5x per 2 nodes] al Pitc Pitc h h (Typical (Typical DRAM) MPU/ASIC) Decreased transistor/feature sizes Increased variability (tox, BEOL, DFM, SEU, etc.) Short channel effect, leakage power ©M.S.Ramaiah School Of Advanced Studies 6
  7. 7. PEMP VSD531 SEMATECH Prototype BEOL stack, 2000 Passivation Wire Dielectric Etch Stop Layer Via Global (up to 5) Dielectric Capping Layer Copper Conductor with Barrier/NucleationIntermediate (up to 4) Layer Local (2) Pre Metal Dielectric Tungsten Contact Plug Reverse-scaled global interconnects Growing interconnect complexity Performance critical global interconnects ©M.S.Ramaiah School Of Advanced Studies 7
  8. 8. PEMP VSD531 Intel 130nm BEOL Stack Intel 6LM 130nm process with vias shown (connecting layers)Aspect ratio = thickness / minimum width ©M.S.Ramaiah School Of Advanced Studies 8
  9. 9. PEMP VSD531 Interconnect Capacitance: Parallel Plate ModelILD = interlevel dielectric L W T HILD Bottom plate of SiO2 cap can be another metal Substrate layer Cint = eox * (W*L / tox) ©M.S.Ramaiah School Of Advanced Studies 9
  10. 10. PEMP VSD531Line Dimensions and Fringing Capacitance Lateral cap w S Capacitive coupling Crosstalk effect Signal integrity ©M.S.Ramaiah School Of Advanced Studies 10
  11. 11. PEMP VSD531Interconnect Evolution and Modeling Needs Before 1990, wires were thick and wide while devices were big and slow Large wiring capacitances and device resistances Wiring resistance << device resistance Model wires as capacitances only In the 1990s, scaling (by scale factor S) led to smaller and faster devices and smaller, more resistive wires Reverse scaling of properties of wires RC models became necessary In the 2000s, frequencies are high enough that inductance has become a major component of total impedance ©M.S.Ramaiah School Of Advanced Studies 11
  12. 12. PEMP VSD531Evolving Interconnects Affect Timing Interconnect capacitance > gate input capacitance Better prediction Interconnect resistance no longer ignorable Better modeling: distributed R(L)C network, AWE, etc. Effective capacitance < total load capacitance Interconnect delay > gate delay for sub-micron technologies ©M.S.Ramaiah School Of Advanced Studies 12
  13. 13. PEMP VSD531Sub-Wavelength Optical Lithography ©M.S.Ramaiah School Of Advanced Studies 13
  14. 14. PEMP VSD531…Complexity of PhotomasksHow many wafers, on average, are printed with a mask set? ©M.S.Ramaiah School Of Advanced Studies 14
  15. 15. PEMP VSD531Summary of Technology ScalingScaling of 0.7x every three (two?) years .25u .18u .13u .10u .07u .05u 1997 1999 2002 2005 2008 2011 5LM 6LM 7LM 7LM 8LM 9LMInterconnect delay dominates system performance consumes up to 70% of clock cycleCross coupling capacitance is dominating cross capacitance 100%, ground capacitance 0% ground capacitance is 90% in .18u huge signal integrity implications (e.g., guardbands in static analysis approaches)Multiple clock cycles required to cross chip whether 3 or 15 not as important as fact of “multiple” > 1 ©M.S.Ramaiah School Of Advanced Studies 15
  16. 16. PEMP VSD531New Materials Implications Lower dielectric permittivity reduces total capacitance doesn’t change cross-coupled / grounded capacitance proportions Copper metallization reduces RC delay avoids electromigration (factor of 4-5 ?) thinner deposition reduces cross cap Multiple layers of routing enabled by planarization; 10% extra cost per layer reverse-scaled top-level interconnects relative routing pitch may increase room for shielding ©M.S.Ramaiah School Of Advanced Studies 16
  17. 17. PEMP VSD531Technical Issues Manufacturability (chip cant be built) antenna rules minimum area rules for stacked vias CMP (chemical mechanical polishing) area fill rules layout corrections for optical proximity effects in subwavelength lithography; associated verification issues Signal integrity (failure to meet timing targets) crosstalk induced errors timing dependence on crosstalk IR drop on power supplies Reliability (design failures in the field) electromigration on power supplies hot electron effects on devices wire self heat effects on clocks and signals ©M.S.Ramaiah School Of Advanced Studies 17
  18. 18. Noise Analog design concerns are due to physical noise sources because of discreteness of electronic charge and stochastic nature of electronic transport processes example: thermal noise, flicker noise, shot noise Digital circuits due to large, abrupt voltage swings, create deterministic noise which is several orders of magnitude higher than stochastic physical noise still digital circuits are prevalent because they are inherently immune to noise Technology scaling and performance demands make noisiness of digital circuits a big problem
  19. 19. PEMP VSD531Silicon Complexity Challenges Silicon Complexity = impact of process scaling, new materials, new device/interconnect architectures Non-ideal scaling (leakage, power management, circuit/device innovation, current delivery) Coupled high-frequency devices and interconnects (signal integrity analysis and management) Manufacturing variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools) Scaling of global interconnect performance (communication, synchronization) Decreased reliability (soft error uncertainty, gate insulator tunneling and breakdown, joule heating and electromigration) Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost) ©M.S.Ramaiah School Of Advanced Studies 19
  20. 20. PEMP VSD531In a PDA… Reference Design: personal digital assistant (PDA) Composed of CPU, DSP, peripheral I/O, and memory ©M.S.Ramaiah School Of Advanced Studies 20
  21. 21. PEMP VSD531 …Implemented With an SoC 0.18um / 400MHz / 470mW (typical)MM Application MP3 PWR CPG Processor Area JPEG PWM RTC Simple Moving Picture FICP SSP CPU 6.5MTrs. Sound I2C GPIO I-cache D-cache Max 400MHz USB 32KB 32KB USB OSTSpecification MMC DMA controller MMC I2SAvailable Time MEM LCD 6-10Hr KEY UART AC97 Cnt. Cnt. Data Transfer Area Peripheral Area SDRAM Flash LCD 100MHz 64MB 32MB 4 – 48MHz ©M.S.Ramaiah School Of Advanced Studies 21
  22. 22. PEMP VSD531Design Principles (Traditional) Partition the problem (hirarchical design) Different abstraction levels: RTL, gate-level, switch-level, transistor-level Orthogonize concerns Abstraction vs. implementation Logic vs. timing Constrain the design space to simplify the design process Balance between design complexity and performance E.g., standard-cell methodology ©M.S.Ramaiah School Of Advanced Studies 22
  23. 23. PEMP VSD531Design Principles(State of the Art) Integrate the problem (design closure) Back-annotation, predictability Balance design metrics Area/timing/power/signal integrity/reliability Explore the design space Balance between design complexity and performance Platform-based SoC design ©M.S.Ramaiah School Of Advanced Studies 23
  24. 24. PEMP VSD531Design Methodologies (+ business models) Full-Custom (high effort, leading-edge performance, high-volume) Semi-Custom (strong infrastructure, economical in lower volumes) ASIC (Application-Specific Integrated Circuit) Standard Cell/Gate Array/Via Programmable/Structured ASIC FPGA Special Analog (custom layout, I/Os and sense amps) Mixed-Signal / RF (unique to each process, no scaling) System-on-Chip ( System-in-Package) Various components: IP blocks, ASIC, FPGA, memory, uP, RF, etc. Define implementation platform, hardware-software co-design Performance vs. complexity ©M.S.Ramaiah School Of Advanced Studies 24
  25. 25. PEMP VSD531 Flow Wire Model Standard Cell Library Device model r,s, m Schematic Entry 3-D RLC Layers Cell Modeling Tool Layout rules Characterization Layout Entry Synthesis Library (Timing/Power/Area) Parasitic Extraction Library Place & Route Library (Ports)C-Model Verilog Structural Global Synthesis Block Layout P & R Behavioral Model Layout Model Verilog Floorplan Floorplan Structural RTL P&R DRC/ERC/LVS Static/Dynamic Timing w/extract Functional Functional Power/Area Scan/Testability Static Timing Clock Routing/Analysis ©M.S.Ramaiah School Of Advanced Studies 25
  26. 26. PEMP VSD531 Traditional Taxonomy Behavioral Level Design IO Pad Placement Front End Logic Design and Power/Ground Simulation Stripes, Rings Routing Logic Synthesis Logic Partitioning Die Planning Global Placement Detail Placement Simulation Floorplanning Clock Tree Synthesis and RoutingDesign Verification Timing Verification Extraction and Delay Calc. Timing Global Routing Verification Test Generation LVS DRC Detail Routing Back End ERC ©M.S.Ramaiah School Of Advanced Studies 26
  27. 27. PEMP VSD531Generic Flow Steps Library preparation Physical design Library data preparation •Physical floorplanning Design data preparation •Place and route Logic design •RC extraction Specification to RTL •Formal verification RTL simulation •Physical verification Hierarchical floorplanning •Release to manufacturing Synthesis Design for test Formal verification Engineering change order Gate level simulation Static timing analysis ©M.S.Ramaiah School Of Advanced Studies 27
  28. 28. PEMP VSD531Library and Design Data Models and technology data required to execute the design flow Power, timing: ALF, DCL, OLA, .lib, STAMP Layout: LEF, DEF, GDSII Delays and path timing, parasitics: SDF, GCF, SDC, DSPF, RSPF, SPEF, SPICE Layout rules: Dracula, Calibre “deck” ©M.S.Ramaiah School Of Advanced Studies 28
  29. 29. PEMP VSD531High-Level Synthesis (Behavior RTL)Scheduling Assignment of each operation to a time slot corresponding to a clock cycle or time intervalResource allocation Selection of the types of hardware components and the number for each type to be included in the final implementationModule binding Assignment of operation to the allocated hardware componentsController synthesis Design of control style and clocking schemeCompilation of the input specification language to the internal representationParallelism extraction usually via data flow analysis techniques… ©M.S.Ramaiah School Of Advanced Studies 29
  30. 30. PEMP VSD531Architecture Level Floorplanning Defines the basic chip layout architecture Define the standard cell rows and I/O placement locations Place RAMs and other macros Separate gate array, memory, analog, RF blocks Define power distribution structures such as rings and stripes Allow space for clock, major buses, etc. Rules of thumb for cell density are used to initially calculate design size ©M.S.Ramaiah School Of Advanced Studies 30
  31. 31. PEMP VSD531Logic Synthesis Conversion of RTL to gate-level netlist Targeted to a foundry-specific library Can be performed hierarchically (block by block) Timing-driven Clock information Primary input arrival times, primary output required times Input driving cells, output loading False paths, multi-cycle paths Interconnect delay may be calculated based on a “wireload model” which uses fanout to estimate delay Clock parameters (insertion delay, skew, jitter, etc.) are assumed to be attainable later in place and route ©M.S.Ramaiah School Of Advanced Studies 31
  32. 32. PEMP VSD531Formal Verification RTL description and gate level netlist are compared to verify functional equivalence, thereby verifying the synthesis results Formal methods Graph isomorphism Binary Decision Diagram (BDD) Emerging technology that supplements the more traditional gate-level simulation approach FV also performed after place-and-route (if gate netlist changes) ©M.S.Ramaiah School Of Advanced Studies 32
  33. 33. PEMP VSD531RTL Simulation RTL code, written in Verilog, VHDL or a combination of both, is simulated to verify functional correctness Testbenches apply input stimulus to the design Several methods are used to verify the outputs Self-checking testbenches automatically verify output correctness and report mismatches Results can be stored in a file and compared to previous results Waveform displays can be used to interactively verify the outputs ©M.S.Ramaiah School Of Advanced Studies 33
  34. 34. PEMP VSD531Gate-Level Simulation Covers both functionality and timing Correctness is only as good as the test vectors used Especially critical for non-synchronous designs, verification of false path and multi-cycle path constraints Cell timing is included in the simulation models and interconnect delay is passed from the synthesis run Worst case PVT conditions are used to analyze for setup violations, and best case PVT conditions are used to analyze for hold violations PVT = Process, Voltage, Temperature ©M.S.Ramaiah School Of Advanced Studies 34
  35. 35. PEMP VSD531Static Timing Analysis Verifies that design operates at desired frequency Implicitly assumes correct timing constraints (!), e.g., boundary conditions Timing constraints are similar to those used by logic synthesis Verifies setup and hold times at FF inputs; can also check timing from and to PI’s and PO’s; can also check point-to-point delay values (with blocking of pins, etc.) As with gate-level simulation, both best- and worst-case analysis is performed Typically performed on full-chip (not block) basis May require modified constraints for inter-block issues: multiple clock domains, multi-cycle paths, etc. For compatibility with timing-driven layout flow, helps to have simple / single set of constraints Other issues: incremental analysis, … ©M.S.Ramaiah School Of Advanced Studies 35
  36. 36. PEMP VSD531Block-Level Physical FloorplanningReconcile logical and physical hierarchiesCells that are interconnected want to be close together Take advantage of RTL hierarchy Generate a physical hierarchy RTL hierarchy = best physical hierarchyOften bundled within the same cockpit as the place and route toolGive placement some initial clues to reduce complexity ©M.S.Ramaiah School Of Advanced Studies 36
  37. 37. PEMP VSD531Place and RouteAutomatically place the standard cellsGenerate clock treesAdd any remaining power bus connectionsRoute clock linesRoute signal interconnectsDesign rule checks on the routes and cell placementsTiming driven tools Require timing constraints and analysis algorithms similar to those used during the static timing analysis step ©M.S.Ramaiah School Of Advanced Studies 37
  38. 38. PEMP VSD531RC(L) Extraction Calculate resistance and capacitance (and inductance) of interconnects Based on placement of cells Routing segments Calculate capacitive (inductive) effects of adjacent segments Extract capacitance between metal segments RC(L) data transferred back to Static timing analysis (back annotation) Gate level simulation Replaces wire load model used in synthesis Drive delay calculation, signal integrity analysis (crosstalk, other noise), static timing Q: How do parasitics and noise affect performance? ©M.S.Ramaiah School Of Advanced Studies 38
  39. 39. PEMP VSD531Physical Verification DRC – Design Rule Check Spacing, min dimension rules LVS – Layout Versus Schematic Verifies that layout and netlist are equivalent at the transistor level Electrical Rule Check Dangling nets, floating nodes GDSII (Stream Format) Final merge of layout, routing and placement data for mask production ©M.S.Ramaiah School Of Advanced Studies 39
  40. 40. PEMP VSD531Release to Manufacturing Final edits to the layout are made Metal fill and metal stress relief rules are checked Manufacturing information such as scribe lanes, seal rings, mask shop data, part numbers, logos and pin 1 identification information for assembly are also added DRC and LVS are run to verify the correctness of the modified database ‘Tapeout’ documentation is prepared prior to release of the GDSII to the foundry Pad location information is prepared, typically in a spreadsheet Cadence’s Virtuoso is used for custom-manual edits of the mask layers Manufacturing steps generation of masks silicon processing wafer testing assembly and packaging manufacturing test ©M.S.Ramaiah School Of Advanced Studies 40
  41. 41. PEMP VSD531More Design Metrics and Techniques Cost minimization Area Synthesis (technology mapping) Cell area Wirelength Placement, routing Timing Performance optimization Gate Interconnect Logic transformation, transistor sizing Power Buffering, re-routing Dynamic Static Power minimization Leakage Gating (sleep transistors), variant Vdd Signal Integrity Process optimization Crosstalk (capacitive, inductive) Dual-Vth Supply voltage drop (IR drop, LdI/dt) Signal Integrity Reliability Sizing, net ordering, shielding Variation (Vdd, thermal, process variation (tox, BEOL)) P/G design, placement, synthesis Electromigration Reliability Hot electron effect (SEU) Statistical design optimization Design margin ©M.S.Ramaiah School Of Advanced Studies 41
  42. 42. PEMP VSD531Wireload Model Helps delay estimation at synthesis stage Gate delay = f(input slew, load cap) Cap Wire cap = f’(fanout number) Empirical 2 5 10 15 Different for each technology, library, tool, #Pins design, and design stage Statistical (from library), custom (multiple iterations), structural (look at adjacent 15 nets) … 10 Large deviation remains % Est Error 5 Routing obstacles (hard IP blocks, macros, 0 etc.) 0 5 10 15 -5 Routing algorithms/implementations (timing -10 driven, net ordering, details) Design ©M.S.Ramaiah School Of Advanced Studies 42
  43. 43. PEMP VSD531Interconnect Statistics Local Interconnect SLocal = S Technology SGlobal = S Die Global Interconnect What are some implications? ©M.S.Ramaiah School Of Advanced Studies 43
  44. 44. PEMP VSD531Constructive Interconnect Prediction Statistical models have their limitations Critical paths and the law of small numbers Statistics properties, e.g., average wirelength Extreme statistics properties, e.g., critical path length Implementation details Routing congestion, e.g., horizontal effect Timing optimization, e.g., layer assignment Via blockage, pin accessability, wrong way routing, etc. Predict by construction (physical synthesis) try a fast (global) router ©M.S.Ramaiah School Of Advanced Studies 44
  45. 45. PEMP VSD531Goal: Design Convergence What must converge? logic, timing, power, SI, reliability in a physical embedding support front-end signoff with a predictable back-end Achieve Convergence through Predictability correct by construction (“assume, then enforce”) constraints and assumptions passed downstream; not much goes upstream ignores concerns via guardbanding separates concerns as able (e.g., FE logic/timing vs. BE spatial embedding) construct by correction (“tight loops”) logic-layout unification; synthesis-analysis unification, concurrent optimization elimination of concerns reduced degrees of freedom, pre-emptive design techniques e.g., power distribution, layer assignment / repeater rules ©M.S.Ramaiah School Of Advanced Studies 45
  46. 46. PEMP VSD531“Physical Prototyping Philosophy” RTL Prototype delivers accurate physical data Functionality known Levels of accuracy Gates Placement-acknowledgeable synthesis (PKS) Including global route Physical Prototype Post-detailed-route (In-Place Timing / routability known Optimization, i.e., IPO) Hierarchical timing budgeting:Floorplan / Placement Chip-level CTS, top-level route and IPO, power analysis and grid design Routing Block-level synthesis, placement, IPO, routing “Handoff with enough physical information to ensure correct results” ©M.S.Ramaiah School Of Advanced Studies 46
  47. 47. PEMP VSD531Pictures of the Pieces… Place Full Chip Power Detailed Trial Route Timing Planning RC Extraction Closure Delay Calc / STA IPO Power IR Drop Hierarchical Clock Analysis Full Chip Tree Synthesis Physical 100ps skew 150ps 130ps skew skew Prototype 50ps skew 50ps 120ps skew skew Block-Level Partition Optimization “Tape Out Every Day” ©M.S.Ramaiah School Of Advanced Studies 47
  48. 48. PEMP VSD531 Session SummaryAfter completing this session, students will be able• Technology and interconnect evolutions are the major sets for the physical design• New materials with respect to scaling are the key issues for the physical design• ASIC design flow like front end and backend with necessary inputs from the foundry are the constraints involved in the process ©M.S.Ramaiah School Of Advanced Studies 48

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