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The basic computer has three instruction code formats which are :-
MEMORY- REFERENCE INSTRUCTION
A memory – reference instruction uses 12 bits to specify an address and 1 bit to specify the addressing mode I. I is equal to 0 for direct address and to 1 for indirect address
REGISTER- REFERENCE INSTRUCTION
A register reference instruction specifies an operation on or a test of the AC register .An operand from the memory is not needed therefore the other 12 bits are used to specify the operation to be executed.
An input-output instruction does not need a reference to memory and is recognized by operational code 111 with a 1 in the left most bit of the instruction the remaining 12 bits are used to specify the type of input output operation or test performed.
- Data transfers between the main memory and the processor registers - LDA, STA
- Program sequencing and control - BUN, BSA, ISZ
- Input and output - INP, OUT
The timing for all register in basic computer is controlled by a master clock generator.
Clock pulses – The clock pulses are applied to all flip-flops and registers in the system , including the flip-flops in the control unit . The clock pulses do not change the state of a register unless the register is unable by a control signal.
There are two types of control organisations :- Hardwired control – In hardwired organization, the control logic is implemented with gates , flip-flops , decoders , and other digital circuits. It has the advantage that it can be optimized to produce a fast mode of operation. 2. Microprogramme control– The control information is stored in the control memory . The control memory is programmed to initiate the required sequence of microperations.
TIMING AND CONTROL
TIMING AND CONTROL
Control unit of Basic Computer Instruction register (IR) 14 13 12 15 11 - 0 Other inputs 3 x 8 decoder 7 6 5 4 3 2 1 0 D 0 Combinational Control logic I D Control signals 7 T 15 T 0 15 14 . . . . 2 1 0 4 x 16 decoder Increment (INR) 4-bit sequence Clear (CLR) counter Clock (SC)
In basic computer each instruction cycle consist of following phases:- 1. Fetch an instruction from the memory. 2. Decode the instruction. 3. Read the effective address from the memory if the instruction has an indirect address. 4. Execute the instruction.
Fetch & decode ->Initially, the PC is loaded with the address of the first incrementer in the program.
The SC(sequence counter) is cleared to 0,providing a decoded time signal T0.After each clock pulse ,SC is incremented by1 so that the timing go through a sequenceT0,T1,T3 and so on . The microperations for fetch & decode phases are:- T0: AR<-PC T1: IR<-M[AR],PC<-PC+1 T2: D0…..,D7<-Decode IR(12-14),AR<-IR(0-11),I<-IR(15)
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1) T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1) T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15) T1 S2 Bus T0 S1 S0 Memory 7 unit Address Read AR 1 LD PC 2 INR IR 5 LD Clock Common bus
Register Reference Instructions are identified when - D7 = 1, I = 0 - Register Ref. Instr. is specified in b0 ~ b11 of IR - Execution starts with timing signal T3 r = D7 IT3 => Register Reference Instruction Bi = IR(i) , i=0,1,2,...,11 r: SC 0 CLA rB11: AC 0 CLE rB10: E 0 CMA rB9: AC AC’ CME rB8: E E’ CIR rB7: AC shr AC, AC(15) E, E AC(0) CIL rB6: AC shl AC, AC(0) E, E AC(15) INC rB5: AC AC + 1 SPA rB4: if (AC(15) = 0) then (PC PC+1) SNA rB3: if (AC(15) = 1) then (PC PC+1) SZA rB2: if (AC = 0) then (PC PC+1) SZE rB1: if (E = 0) then (PC PC+1) HLT rB0: S 0 (S is a start-stop flip-flop)