Ctp cdnlive2005 1329mohindru.pres


Published on

Published in: Technology, Business
  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

Ctp cdnlive2005 1329mohindru.pres

  1. 1. Comprehensive SoC Power Grid verification using VoltageStorm Navneet Mohindru, VoltageStorm Product Validation Lead Lalit Garg, VAVO Product Engineer
  2. 2. Agenda• Introduction• Static and Dynamic IR drop analysis using VoltageStorm• SoC Hierarchical Analysis Methodology• Results and Observations• Conclusions• Q&A 2
  3. 3. Introduction• Low power supply voltage causing IR drop problems in SoC designs• Increasing demand to handle analog blocks in SoC – Have their own dedicated supplies – Must account for block boundary voltages – IR drop/ground bounce from top-level power routing – Some analog blocks share digital power supplies• Integration with VoltageStorm – Base SoC power integrity product – Hierarchical, cell-based approach – Utilizes abstracted power grid views – Mix & match power grid views for complete solution 3
  4. 4. Static and Dynamic IR dropanalysis using VoltageStorm• VoltageStormsupports both static and dynamicIR drop analysis 4
  5. 5. Static IR drop analysis usingVoltageStorm• Static IR drop analysis verifies robustness of power rail by showing static IR drop, open circuits, missing vias and high current densities• StaticIR drop analysis is based upon average power calculated by powermeter• Average power calculation is based upon three methods – Full-chip VCD – Accura based switching probability propagation method – Mixture of Accura and VCD 5
  6. 6. Dynamic IR drop analysis usingVoltageStorm• Dynamic IR drop analysis is used for analyzing the effect of transient IR drop• Helpsin optimizing number of decoupling capacitors to reduce leakage in 90nm and sub-90nm designs• Based upon instance based dynamic current consumption calculated by powermeter• Powermeteruses two methods to calculate dynamic current consumption – Vector-based – Uses gate or transistor level simulation to generate dynamic power/current waveform – Most accurate solution if “right” vectors are provided by user – Vectorless – Uses timing window information to generate dynamic power/current waveform – Best approach to obtain full-chip transient information 6
  7. 7. SoC Hierarchical AnalysisMethodology• VoltageStorm uses power grid views for enabling hierarchical solution•A power grid is used to model power rail and power distribution information of each instance in design.• For SoC design, different type of power grids will include – standard cell views – digital blocks – IP/Memory blocks – Analog/Mixed Signal Blocks 7
  8. 8. Types of Power Grid Views• VoltageStorm uses four types of Static Power Grid Views power grid views for hierarchical Detailed Reduced Abstract Port static analysis – Detailed – Reduced – Abstract – Port Dynamic Power Grid Views• For hierarchical dynamic Detailed Dynamic Reduced Dynamic Port analysis, three additional types of power grid views are used – Detailed Dynamic – Reduced Dynamic – Port 8
  9. 9. Power Grid Views for StandardCells• For standard cells port views are sufficient. However for dynamic analysis detailed views are created for CRC modeling of standard cell.• CRC modeling – R on – Device C – Load C (Pin capacitance) Cell VDD Loading C from x out SPEF/DSPF device Ron x out device C device C Pin-cap 9
  10. 10. Power Grid Views forMemory/Hard IP• ForMemory and hard IP, detailed views are created for verifying that these blocks do not suffer from IR drop within the instance GDS• Two methods are used – Libgen detailed view creation. Vectors VST – Most common method – Transistor level VoltageStorm Flow LEF LibGen Detailed Dynamic PGV – Used for detailed dynamic PGV creation – Device recognition and spice netlist generation – RC extraction – Spice-like simulation on spice netlist for current tap generation – Analysis on power grid – Generate detailed/reduced power grid view from analysis results 10
  11. 11. Power Grid Views for DigitalBlocks• Forcreating power grid views of digital blocks, static or dynamic IR drop analysis is run at block level first. Here are the steps – Calculate instance based average static/dynamic current. – Run R or RC extraction on block level power grid. – Merge the static or dynamic current with the extracted power grid. – Run static/dynamic analysis. – Generate detailed/reduced power grid view for the block from the analysis results. 11
  12. 12. Power Grid Views for Analog/Mixed-Signal Blocks (VAVO)• Analog VoltageStorm (VAVO) accurately characterize power consumption and power distribution inside analog and mixed signal blocks – Power integrity verification – IR drop (power and ground rails) – Power rail Electromigration – Integrated with Virtuoso ADE environment – Flow supported by existing Cadence products – Assura LVS – Assura RCX – Spectre or UltraSim for simulation 12
  13. 13. VAVO FLOW DIAGRAM Testbench schematic Schematic Layout Assura LVS Assura RCX (RC extraction) Create simulation netlist from config view including Assura extracted cellview Assura extracted cellview Create Simulation files Run Spectre or UltraSim Run VAVO/VAEOCreate Power Grid View Display results in Assura extracted cellview 13
  14. 14. Simulation Details in VAVO V V V Top-levels of interconnect V V VDD M6 V V V V V V M5 M4 V V V V V V M1 V Voltage measures are V V automatically added to V V extracted netlist Analog Circuit 14
  15. 15. VAVO Plot and Report Examples 15
  16. 16. VoltageStormComprehensive SoC Power Grid Verification VoltageStorm PE Full ChipStatic & Dynamic Power Grid Views (static & dynamic) Encounter Platform Virtuoso PlatformVoltageStorm PE VoltageStorm DG VoltageStorm VST VoltageStorm VAVO(activity propagation, (vectorless & VCD, (dynamic, transistor) (dynamic, transistor) static, cell-based) dynamic, cell-based) CeltIC CeltIC UltraSim Spectre NDC NDC UltraSim Large Digital Large Digital Small Digital Mixed-Signal & Design Design Design Analog Design 16
  17. 17. Results and ObservationsStatic IR Drop top level run with libgen detailed view Static IR Drop top level run with VAVO detailed view of PLL of PLL 17
  18. 18. Results and Observations• The power grid views generated by VAVO for the analog block are more accurate because of the following reasons: – Device recognition is more accurate because Assura LVS is used to extract analog devices. – RCX is more accurate in extracting parasitics for non-manhattan geometry. – Tap current in VAVO is calculated from actual Spice-like simulation. 18
  19. 19. Conclusions• Here are conclusions from this methodology – VoltageStorm can analyze and characterize all types of blocks such as digital blocks, memories, hard IPs and analog/mixed signal blocks accurately at SoC level. – The hierarchical flow of VoltageStorm gives it infinite capacity since designer can create as many power grid views as required and feed them into top level run. 19