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Interfacing address
 

Interfacing address

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    Interfacing address Interfacing address Presentation Transcript

    • Danish ansari F.Y.Bsc-ITFIFTY FOUR
    • Interfacing:Interfacing means a device or program enabling a user to communicate with a computer, or for connecting two items of hardware or software.The interfacing process involves designing a circuit that will match the memory requirements with the microprocessor.
    • Memory interfacing Memory is an integral part of a microcomputer system. Memory has certain signal requirements to write into & read from its registers. Similarly the micro processor initiates a set of signals when it wants to read from & write into memory.
    • Memory structure & its requirements Read/Write memory is a group of registers to store binary information. It has 2048 registers & each register can store 8 bits indicated by 8 input & 8 output data lines. The chip has 11 address lines A10-A0, one chip select (cs), & two control lines:Read (rd) to enable the output buffer and Write (wr) to enable the input buffer.
    • Eprom: It is a group of 4096 registers. It has 12 address lines A11-A0, one chip select (cs), & one read control signal. This chip must be programmed before it can be used as a read-only memory.
    • Basic concepts in memoryinterfacing: The primary function of memory interfacing is that the microprocessor should be able to read from and write into a given register of a memory chip. The microprocessor should perform these operations: Be able to select the chip. Identify the register. Enable the appropriate buffer.
    • Address decoding The process of address decoding should result in identifying a register for a given address. It should be able to generate a unique pulse for a given address. The address lines (A11-A0) are connected to the memory chip, & the remaining four address lines (A15- A12) of the 8085 microprocessor must be decoded.
    •  It shows two methods of decoding these lines. One by using a NAND gate Other by using a 3-8 decoder. The output of the NAND goes active & selects the chip only when all address lines A15-A12 are at logic 1. The same result can be obtained by using 3-8 decoder , which is capable of decoding 8 different input addresses.
    •  In the decoder circuit, three input lines can have 8 different logic combinations from 000 to 111; each input combination can be identified by the corresponding output line if Enable lines are active. In this circuit enable lines are enabled by grounding. This address decoding scheme can be used to interface a 4K EPROM and a 2K R/W memory.
    • Address decoding & memoryaddresses The address range of the memory chip can be obtained by analyzing the possible logic levels on the 16 address lines. The logic levels on the address lines A15-A12 must be 0000 to assert the chip enable, & the address lines A11- A0 can assume any combinations from all 0s to all 1s. Therefore the memory address of the chip ranges from 0000H to 0FFFH.
    • Thank you