Microprocessor systems 8085
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  • 1. Microprocessor SystemsMicroprocessor Systems SESSION OF INTEL 8086SESSION OF INTEL 8086 By: Engr.Shafiullah Soomro safiullah123@gmail.com
  • 2. INTEL 8086 INTRODUCTIONINTEL 8086 INTRODUCTION  Intel 8086 (also called iAPX86) is a 16-bit microprocessorIntel 8086 (also called iAPX86) is a 16-bit microprocessor  it is designed by Intel between early 1976 and mid-1978it is designed by Intel between early 1976 and mid-1978  8086 gave rise to the x86 architecture of Intel's future8086 gave rise to the x86 architecture of Intel's future processorsprocessors  It is 40-Pins DIP packageIt is 40-Pins DIP package  It is manufactured using high performance metal-oxideIt is manufactured using high performance metal-oxide semiconductor (HMOS) technologysemiconductor (HMOS) technology  It has approximately 29,000 transistorsIt has approximately 29,000 transistors  8086 has a 16bit data bus. It can read or write data to a8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a timememory/port either 16bits or 8 bit at a time  8086 has a 20bit address bus which means, it can8086 has a 20bit address bus which means, it can address up to 2^20 = 1MB memory locationaddress up to 2^20 = 1MB memory location  Frequency range of 8086 is 6-10 MHzFrequency range of 8086 is 6-10 MHz
  • 3. PIN DIAGRAM OF 8086
  • 4. Pins Description of 8086Pins Description of 8086 ASSIGNMENT No.1 OUT OF 2 15 Sessionals = 10(5+5) for Class Test (best 2 out of 3) 5 for Assignment OPTIONS 1=> Each of 2.5 Marks (2 Assignments) 2=> One Best out of Two Assignments Last Submission Date??
  • 5. Architecture of INTEL 8086
  • 6. 1 MB Address Space of 80861 MB Address Space of 8086 The diagram shows the Memory Map of 8086 As 8086 has 20 Address lines, so it has ability to work with 2^20 = 1024 KB = 1 MB memory This 1 MB memory is divided as ROM, Video Display RAM and RAM as shown in figure The RAM is further divided into 4 Segments each of 64KB, discussed in next slide
  • 7. 1 MB Address Space of 80861 MB Address Space of 8086  8086 has 20-bit address bus, so it can address any of 2^20 or 1,048,576 bytes (1 MB) in memory  But 8086 use only four 64Kbytes segments in this 1 MB range as its working Memory  Those are Data Segment, Code Segment, Stack Segment and Extra Segment  1 MB is divided as, that starting address (base address) of each segment contains 0H in lower 4 bits  Four segment registers in BIU are used to hold upper 16-bits of the 20-bit base address of each segment  Those Segment registers are DS, CS, SS and ES Fig 2-9 page 30 of V.Hall
  • 8. Physical Addressing in 8086 ArchitecturePhysical Addressing in 8086 Architecture (1/4)(1/4) ADDITION is performed by Address Generator to Produce 20-bit physical address: • SI (Source Index) Register contains offset, it is added with DS (Data Segment) Register , that contains base address and hardwired Zero is included before addition • DI (Destination Index) Register contains offset, it is added with with ES (Extra Segment) Register that contains base address and hardwired Zero is included before addition • IP (Instruction Pointer) Register contains offset, it is added with CS (Code Segment) Register that contains base address and hardwired Zero is included before addition • SP (Stack Pointer) Register contains offset, it is added with with SS (Stack Segment) Register that contains base address and hardwired Zero is included before addition • Data area(s) may exist in stack. To access such data area in stack segment, BP register is used which contains the offset address. BP register is also used as a general purpose register.
  • 9. Physical Addressing in 8086 Architecture (2/4)Physical Addressing in 8086 Architecture (2/4)
  • 10. Physical Addressing in 8086 Architecture (3/4)Physical Addressing in 8086 Architecture (3/4)
  • 11. Physical Addressing in 8086 Architecture (4/4)Physical Addressing in 8086 Architecture (4/4)
  • 12. Advantages of Memory SegmentationAdvantages of Memory Segmentation  Allow the memory capacity to be 1MbAllow the memory capacity to be 1Mb even though the addresses associatedeven though the addresses associated with the individual instructions are only 16with the individual instructions are only 16 bits wide.bits wide.  Facilitate the use of separate memoryFacilitate the use of separate memory areas for the program, its data and theareas for the program, its data and the stack.stack.  Permit a program and/or its data to be putPermit a program and/or its data to be put into different areas of memory each timeinto different areas of memory each time the program is executed.the program is executed.  Multitasking becomes easy.Multitasking becomes easy.
  • 13. Architecture of INTEL 8086
  • 14. Description of 8086 ArchitectureDescription of 8086 Architecture TWO INDEPENDENT UNITS Intel 8086 Microprocessor’s architecture is divided into two independent units: 1. BIU (Bus Interface Unit) BIU has segment registers, instruction pointer, address generation and bus control logic block, instruction queue 2. EU (Execution Unit) EU has general purpose registers, ALU, control unit, instruction register, flag (or status) register
  • 15. Description of 8086 ArchitectureDescription of 8086 Architecture FUNCTIONS OF BIU & EU The main jobs performed by BIU are: • BIU is the 8086’s interface to the outside world, i.e., all External bus operations are done by BIU. • It does the job of instruction fetching, reading/writing of data/operands for memory and also the inputting/outputting of data for peripheral devices. • It does the job of filling the instruction queue. • Does the job of address generation. The main jobs performed by the execution unit are: • Decoding/execution of instructions. • It accepts instructions from the output end of instruction queue (residing in BIU) and data from the general purpose registers or memory. • It generates operand addresses when necessary, hands them over to BIU requesting it (BIU) to perform read or write cycle to memory or I/O devices. • EU tests the status of flags in the control register and updates them when executing instructions. • EU waits for instructions from the instruction queue, when it is empty. • EU has no connection to the system buses.
  • 16. FETCH & EXECUTE CYCLE IN 8086Although the 8086/88 still functions as a stored program computer, organization of the CPU into a separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what happens when the 8086 or 8088 is first started. 1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU. 2. Register IP is incremented by 1 to prepare for the next instruction fetch. 3. Once inside the BIU, the instruction is passed to the queue. This is a first-in, first-out storage register sometimes likened to a "pipeline". 4. Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution. 5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction. Description of 8086 ArchitectureDescription of 8086 Architecture
  • 17. Registers of 8086Registers of 8086 Description of 8086 ArchitectureDescription of 8086 Architecture
  • 18. Description of 8086 ArchitectureDescription of 8086 Architecture Address Generator: Its responsibility is to generate 20-bit physical address for memory, by adding base address with offset and zero hardwired. Instruction Stream Byte Queue: This queue is used to store instructions after fetching, it has ability to store 6 bytes, EU takes instruction from this queue for execution, it works as FIFO (First In First Out) fashion. Control System: It is responsible to decoding the instruction, controlling the overall functions & timing of Microprocessor. Segment Registers: Those are used to hold the base address of their relevant segments of memory. ES Register is used to hold base address of Extra Segment of memory CS Register is used to hold base address of Code Segment of memory SS Register is used to hold base address of Stack Segment of memory DS Register is used to hold base address of Data Segment of memory  
  • 19. Description of 8086 ArchitectureDescription of 8086 Architecture IP (Instruction Pointer) IP is used to hold the offset address of next instruction to be fetched from Code segment SP (Stack Pointer) SP is used to hold the offset of the top of stack, in stack segment BP (Base Pointer) Data Area may exists in stack segment, so BP is used to hold the base address of Data Area within Stack Segment SI (Source index) It is used to hold the offset of the next instruction to be fetched from Data Segment; it is also used in string operations DI (Destination Index) It is used to hold the offset of the next instruction to be fetched from Extra Segment; it is also used in string operations ALU (Arithmetic & Logic Unit) Arithmetic & logic unit is responsible for performing mathematical & logical operations
  • 20. Description of 8086 ArchitectureDescription of 8086 Architecture GERNAL PURPOSE REGISTERS Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation. Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Count register consists of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions. Data register consists of 2 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.  
  • 21. Description of 8086 ArchitectureDescription of 8086 Architecture FLAG REGISTER It is a 16-bit register, also called flag register or Program Status Word (PSW). Seven bits remain unused while the rest nine are used to indicate the conditions of flags. Out of nine flags, six are condition flags and three are control flags.
  • 22. Description of 8086 ArchitectureDescription of 8086 Architecture The control flags These can be set/reset by the programmer. TF (Trap), When TF (trap flag) is set (=1), the processor operates in single stepping mode—i.e., pausing after each instruction is executed. This mode is very useful during program development or program debugging. When an interrupt is recognized, TF flag is cleared.   IF (Interrupt) IF (interrupt flag) is set, the maskable interrupt INTR is enabled otherwise disabled (i.e., when IF = 0).   DF (Direction) flag DF (direction flag) is used in string (also known as block move) operations. If DF is set to 1 and MOVS instruction is executed, the contents of the index registers DI and SI are automatically decremented to access the string from the highest memory location down to the lowest memory location.
  • 23. Description of 8086 ArchitectureDescription of 8086 Architecture Condition flags   These are set/reset depending on the results of some arithmetic or logical operations during program execution.   OF (Overflow), OF is used only for signed arithmetic operation and is set if the result is too large to be fitted in the number of bits available to accommodate it.   SF (Sign), Set equal to high-order bit of result (0 is positive, 1 if negative)   ZF (Zero), ZF is set if the result of an arithmetic or logical operation is zero.   AF (Auxiliary Carry), AF is set if there is a carry out of bit 3 resulting from an addition operation or a borrow required from bit 4 into bit 3 during subtraction operation.   PF (Parity) PF is set if the lower 8-bits of the result of an operation contains an even number of 1’s   CF (Carry)] CF is set if there is a carry out of the MSB position resulting from an addition operation or if a borrow is needed out of the MSB position during subtraction.
  • 24. Addressing Modes of 8086 (1/2)Addressing Modes of 8086 (1/2) Implied - the data value/data address is implicitly associated with the instruction. Register - references the data in a register or in a register pair. Immediate - the data is provided in the instruction. Direct - the instruction operand specifies the memory address where data is located. Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers.
  • 25. Addressing Modes of 8086 (2/2)Addressing Modes of 8086 (2/2) Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.
  • 26. END OF 8086 SESSION Get Ready for 2nd Sessional Class Test !!!