2013 IEEE Projects @ s3technoloiges
Contact: 0452- 4373398, 9789339435
S.N.

IEEE 2013-2014 TITLES
VLSI

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1.

Pip...
2013 IEEE Projects @ s3technoloiges
Contact: 0452- 4373398, 9789339435
15. Effective and Efficient Approach for Power Redu...
2013 IEEE Projects @ s3technoloiges
Contact: 0452- 4373398, 9789339435
Programmable Duty Cycle
28. Energy-Efficient Digita...
2013 IEEE Projects @ s3technoloiges
Contact: 0452- 4373398, 9789339435
43. Low Latency and Energy Efficient Scalable Archi...
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2013 VLSI Project Titles In Madurai

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S3 Technologies Offered Industrial Training for .NET, web designing and PHP,
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Offer Final year project for all Disciplines and all domains.
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• IEEE 2013 based projects & Application – Client based projects ( Real time projects )
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Knowledge point:
S3 technologies,
43, North Masi street, ( Near Krishnan Kovil)
Simmakkal, Madurai
Phone: 0452-4373398, 9789339435
Visit: www.s3techindia.com
Mail: s3techmadurai@gmail.com

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2013 VLSI Project Titles In Madurai

  1. 1. 2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435 S.N. IEEE 2013-2014 TITLES VLSI Language 1. Pipelined Radix- 2. A Low-Complexity Turbo Decoder Architecture for EnergyEfficient Wireless Sensor Networks STBC-OFDM Downlink Baseband Receiver for Mobile WMAN Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip VHDL/verilog 5. Application Space Exploration of a Heterogeneous un-Time Configurable Digital Signal Processor VHDL/verilog 6. Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor VHDL/verilog 7. CORDIC Designs for Fixed Angle of Rotation VHDL/verilog 8. A Unified Graphics and Vision Processor With a 89 Pose Estimation Engine for Augmented Reality 9. A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits 3. 4. Feedforward FFT Architectures VHDL/verilog W/fps VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog 10. Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials 11. Architecture and Design Flow for a Highly Efficient Structured ASIC 12. Secure Dual-Core Cryptoprocessor for Pairings Over BarretoNaehrig Curves on FPGA Platform VHDL/verilog 13. Secure Dual-Core Cryptoprocessor for Pairings Over BarretoNaehrig Curves on FPGA Platform VHDL/verilog 14. A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology VHDL/verilog VHDL/verilog VHDL/verilog 43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai
  2. 2. 2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435 15. Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops 16. 135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder VHDL/verilog 17. VHDL/verilog Reconfigurable Accelerator for the Word-Matching Stage of BLASTN 18. Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems VHDL/verilog VHDL/verilog 19. MDC FFT/IFFT Processor With Variable Length for MIMOOFDM Systems VHDL/verilog 20. Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems VHDL/verilog 21. Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs VHDL/verilog 22. Design of Hardware Function Evaluators Using LowOverhead Nonuniform Segmentation With Address Remapping VHDL/verilog 23. Design of Hardware Function Evaluators Using LowOverhead Nonuniform Segmentation With Address Remapping VHDL/verilog 24. Architecture for Real-Time Nonparametric Probability Density Function Estimation VHDL/verilog 25. Combined Architecture/Algorithm Approach to Fast FPGA Routing VHDL/verilog 26. Asynchronous Fine-Grain Power-Gated Logic VHDL/verilog 27. VHDL/verilog All-Digital Fast-Locking Pulsewidth-Control Circuit With 43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai
  3. 3. 2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435 Programmable Duty Cycle 28. Energy-Efficient Digital Signal Processing via VoltageOverscaling-Based Residue Number System VHDL/verilog 29. Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design VHDL/verilog 30. Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications VHDL/verilog 31. Enhanced Secure Architecture for Joint Action Test Group Systems VHDL/verilog 32. Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications VHDL/verilog 33. An efficient FPGA implementation of the Advanced Encryption Standard algorithm 34. Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT 35. Separable Reversible Data Hiding in Encrypted Image VHDL/verilog 36. Low-Power Low-Cost Design of Primary Synchronization Signal Detection 37. A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores 38. An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy 39. A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor 40. Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure 41. Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-onChip 42. A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog 43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai
  4. 4. 2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435 43. Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph 44. A Low-Power Low-Cost Design of Primary Synchronization Signal Detection 45. Low-Power and Area-Efficient Carry Select Adder VHDL/verilog 46. Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain 47. Physical-Defect Modeling and Optimization for FaultInsertion Test 48. Reconfigurable Routers for Low Power and High Performance 49. A Reliable Routing Architecture and Algorithm for NoCs 50. Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays 51. Ultralow-Voltage Process-Variation-Tolerant SchmittTrigger-Based SRAM Design 52. Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog VHDL/verilog 43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai

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