3. PC System Architecture Where are the Bottlenecks? PC System Architecture Migration of System Memory Creating New Memory Sub-Architecture Utilize Upgraded PCIe link for New Storage Memory Sub-Architecture Most Memory Interfaces and System Interconnect Have Undergone Dramatic BW Upgrades Over the Years Bulk Storage Access BW Lags (Mechanical Latency)
17. HLNAND SSD vs. NAND SSD Read Throughput, Experimental Results HLNAND-based SSD, Media Rate NAND-based SSD, Media Rate Plots from Mobile Embedded Lab, University of Seoul, 2008
18. HLNAND SSD vs. SSD vs. HDD Estimates and Measured Performance Read Throughput
19. HLNAND SSD vs. NAND SSD Write Throughput, Experimental Results HLNAND-based SSD, Media Rate NAND-based SSD, Media Rate Plots from Mobile Embedded Lab, University of Seoul, 2008
20. HLNAND SSD vs. SSD vs. HDD Estimates and Measured Performance Write Throughput
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25. New Hierarchy for New User Experience Historical Storage Hierarchy New Storage Hierarchy
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Editor's Notes
August 2008 Flash Memory Summit Santa Clara, CA USA
- Loading and saving from and to the HDD/SSD
August 2008 Flash Memory Summit Santa Clara, CA USA
How many conventional flash devices per channel to saturate? Sata 1 Sata 2 Sata 3
Comparable number of interface blocks in controller Higher speed IO in HLNAND rings allows higher BW P to P connection facilitates higher IO rates per ring (channel) Lower pin count on hlnand controller -> dependent on number rings, not devices