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12 BIT SPI DAC

12 BIT SPI DAC

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  • 1. © 2005 Microchip Technology Inc. DS21953A-page 1MCP4821/MCP4822Features• 12-Bit Resolution• ±0.2 LSb DNL (typ.)• ±2 LSb INL (typ.)• Single or Dual Channel• Rail-to-Rail Output• SPI™ Interface with 20 MHz Clock Support• Simultaneous Latching of the Dual DACswith LDAC pin• Fast Settling Time of 4.5 µs• Selectable Unity or 2x Gain Output• 2.048V Internal Band Gap Voltage Reference• 50 ppm/°C VREF Temperature Coefficient• 2.7V to 5.5V Single-Supply Operation• Extended Temperature Range: -40°C to +125°CApplications• Set Point or Offset Trimming• Sensor Calibration• Precision Selectable Voltage Reference• Portable Instrumentation (Battery-Powered)• Calibration of Optical Communication DevicesBlock DiagramDescriptionThe Microchip Technology Inc. MCP482X devices are2.7V–5.5V, low-power, low DNL, 12-bit Digital-to-AnalogConverters (DACs) with internal band gap voltagereference, optional 2x-buffered output and SerialPeripheral Interface (SPI™).The MCP482X family of DACs provide high accuracyand low noise performance for industrial applicationswhere calibration or compensation of signals (such astemperature, pressure and humidity) are required.The MCP482X devices are available in the extendedtemperature range and PDIP, SOIC and MSOPpackages.The MCP482X devices utilize a resistive stringarchitecture, with its inherent advantages of low DNLerror, low ratio metric temperature coefficient and fastsettling time. These devices are specified over theextended temperature range. The MCP482X familyincludes double-buffered registers, allowing simulta-neous updates using the LDAC pin. These devices alsoincorporate a Power-On Reset (POR) circuit to ensurereliable power-up.Package TypesOp AmpsVDDAVSSCS SDI SCKInterface LogicInputRegister A Register BInputDACARegister RegisterDACBStringDACBStringDACAOutputLogicPower-onResetVOUTA VOUTBLDACSHDNOutputGainLogicGainLogic2.048VVREFMCP48218-Pin PDIP, SOIC, MSOP12348765CSSCKSDIVDDAVSSVOUTASHDNLDACMCP48228-Pin PDIP, SOIC, MSOP12348765CSSCKSDIVDDAVSSVOUTAVOUTBLDAC12-Bit DACs with Internal VREF and SPI™ Interface
  • 2. MCP4821/MCP4822DS21953A-page 2 © 2005 Microchip Technology Inc.1.0 ELECTRICALCHARACTERISTICSAbsolute Maximum Ratings †VDD............................................................................................................. 6.5VAll inputs and outputs ...................AVSS – 0.3V to VDD + 0.3VCurrent at Input Pins ....................................................±2 mACurrent at Supply Pins ...............................................±50 mACurrent at Output Pins ...............................................±25 mAStorage temperature .....................................-65°C to +150°CAmbient temp. with power applied ................-55°C to +125°CESD protection on all pins ...........≥ 4 kV (HBM), ≥ 400V (MM)Maximum Junction Temperature (TJ)..........................+150°C† Notice: Stresses above those listed under “MaximumRatings” may cause permanent damage to the device. This isa stress rating only and functional operation of the device atthose or any other conditions above those indicated in theoperational listings of this specification is not implied.Exposure to maximum rating conditions for extended periodsmay affect device reliability.5V AC/DC CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x,RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at +25°C.Parameters Sym Min Typ Max Units ConditionsPower RequirementsInput Voltage VDD 2.7 — 5.5Input Current - MCP4821Input Current - MCP4822IDD ——330415400750µA Digital inputs grounded, Outputunloaded, code = 0x000Hardware Shutdown Current ISHDN — 0.3 2 µASoftware Shutdown Current ISHDN_SW — 3.3 6 µAPower-on-Reset Threshold VPOR — 2.0 — VDC AccuracyResolution n 12 — — BitsINL Error INL -12 2 12 LSbDNL (Note 1) DNL -0.75 ±0.2 +0.75 LSb Device is monotonicOffset Error VOS -1 ±0.02 1 % of FSR Code = 0x000hOffset Error TemperatureCoefficientVOS/°C — 0.16 — ppm/°C -45°C to 25°C— -0.44 — ppm/°C +25°C to 85°CGain Error gE -2 -0.10 2 % of FSR Code 0xFFFh, not including offseterrorGain Error TemperatureCoefficientΔG/°C — -3 — ppm/°CInternal Voltage Reference (VREF)Nominal Reference Voltage VREF 2.008 2.048 2.088 V VOUTA when G = 1x andCode = 0xFFFhTemperature Coefficient(Note 1)ΔVREF/°C — 125 325 ppm/°C -40°C to 0°C— 0.25 0.65 LSb/°C -40°C to 0°C— 45 160 ppm/°C 0°C to +85°C— 0.09 0.32 LSb/°C 0°C to +85°COutput Noise (VREF Noise) ENREF(0.1-10 Hz)— 290 — µVp-p Code = 0xFFFh, G = 1Output Noise Density eNREF(1 kHz)— 1.2 — µV/√Hz Code = 0xFFFh, G = 1eNREF(10 kHz)— 1.0 — µV/√Hz Code = 0xFFFh, G = 11/f Corner Frequency fCORNER — 400 — HzNote 1: By design, not production tested.2: Too small to quantify.
  • 3. © 2005 Microchip Technology Inc. DS21953A-page 3MCP4821/MCP4822Output AmplifierOutput Swing VOUT — 0.010 toVDD – 0.040— Accuracy is better than 1 LSb forVOUT = 10 mV to (VDD – 40 mV)Phase Margin PM — 66 — °Slew Rate SR — 0.55 — V/µsShort Circuit Current ISC — 15 24 mASettling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value from1/4 to 3/4 full-scale rangeDynamic PerformanceDAC-to-DAC Crosstalk — <10 — nV-s Note 2Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry(0111...1111 to 1000...0000)Digital Feedthrough — <10 — nV-s Note 2Analog Crosstalk — <10 — nV-s Note 25V AC/DC CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x,RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at +25°C.Parameters Sym Min Typ Max Units ConditionsNote 1: By design, not production tested.2: Too small to quantify.3V AC/DC CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x,RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at 25°CParameters Sym Min Typ Max Units ConditionsPower RequirementsInput Voltage VDD 2.7 — 5.5Input Current - MCP4821Input Current - MCP4822IDD ——300415400750µA Digital inputs grounded, Outputunloaded, code = 0x000Hardware Shutdown Current ISHDN — 0.25 2 µASoftware Shutdown Current ISHDN_SW — 2 6 µAPower-On Reset threshold VPOR — 2.0 — VDC AccuracyResolution n 12 — — BitsINL Error INL -12 ±3 12 LSbDNL (Note 1) DNL -0.75 ±0.3 0.75 LSb Device is monotonicOffset Error VOS -1 ±0.02 1 % of FSR Code 0x000hOffset Error TemperatureCoefficientVOS/°C — 0.5 — ppm/°C -45°C to +25°C— -0.77 — ppm/°C +25°C to +85°CGain Error gE -2 -0.15 2 % of FSR Code 0xFFFh, not including off-set errorGain Error TemperatureCoefficientΔG/°C — -3 — ppm/°CNote 1: By design, not production tested.2: Too small to quantify.
  • 4. MCP4821/MCP4822DS21953A-page 4 © 2005 Microchip Technology Inc.Internal Voltage Reference (VREF)Nominal Reference Voltage VREF 2.008 2.048 2.088 V VOUTA when G = 1x andCode = 0xFFFhTemperature Coefficient(Note 1)ΔVREF/°C — 125 325 ppm/°C -40°C to 0°C— 0.25 0.65 LSb/°C -40°C to 0°C— 45 160 ppm/°C 0°C to +85°C— 0.09 0.32 LSb/°C 0°C to +85°COutput Noise (VREF Noise) ENREF(0.1-10 Hz)— 290 — µVp-p Code = 0xFFFh, G = 1Output Noise Density eNREF(1 kHz)— 1.2 — µV/√Hz Code = 0xFFFh, G = 1eNREF(10 kHz)— 1.0 — µV/√Hz Code = 0xFFFh, G = 11/f Corner Frequency fCORNER — 400 — HzOutput AmplifierOutput Swing VOUT — 0.010 toVDD – 0.040— Accuracy is better than 1 LSb forVOUT = 10 mV to (VDD – 40 mV)Phase Margin PM — 66 — °Slew Rate SR — 0.55 — V/µsShort Circuit Current ISC — 14 24 mASettling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value from1/4 to 3/4 full-scale rangeDynamic PerformanceDAC-to-DAC Crosstalk — <10 — nV-s Note 2Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry(0111...1111 to1000...0000)Digital Feedthrough — <10 — nV-s Note 2Analog Crosstalk — <10 — nV-s Note 23V AC/DC CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x,RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at 25°CParameters Sym Min Typ Max Units ConditionsNote 1: By design, not production tested.2: Too small to quantify.5V EXTENDED TEMPERATURE SPECIFICATIONSElectrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x,RL = 5 kΩ to GND, CL = 100 pF. Typical values at +125°C by characterization or simulation.Parameters Sym Min Typ Max Units ConditionsPower RequirementsInput Voltage VDD 2.7 — 5.5Input Current - MCP4821Input Current - MCP4822IDD ——350440— µA Digital inputs grounded, Outputunloaded, code = 0x000Hardware Shutdown Current ISHDN — 1.5 — µASoftware Shutdown Current ISHDN_SW — 5 — µAPower-On Reset threshold VPOR — 1.85 — VDC AccuracyResolution n 12 — — BitsINL Error INL — ±4 — LSbNote 1: By design, not production tested.2: Too small to quantify.
  • 5. © 2005 Microchip Technology Inc. DS21953A-page 5MCP4821/MCP4822DNL (Note 1) DNL — ±0.25 — LSb Device is monotonicOffset Error VOS — ±0.02 — % of FSR Code 0x000hOffset Error TemperatureCoefficientVOS/°C — -5 — ppm/°C +25°C to +125°CGain Error gE — -0.10 — % of FSR Code 0xFFFh, not including offseterrorGain Error TemperatureCoefficientΔG/°C — -3 — ppm/°CInternal Voltage Reference (VREF)Nominal Reference Voltage VREF — 2.048 — V VOUTA when G = 1x andCode = 0xFFFhTemperature Coefficient(Note 1)ΔVREF/°C — 125 — ppm/°C -40°C to 0°C— 0.25 — LSb/°C -40°C to 0°C— 45 — ppm/°C 0°C to +85°C— 0.09 — LSb/°C 0°C to +85°COutput Noise (VREF Noise) ENREF(0.1 - 10 Hz)— 290 — µVp-p Code = 0xFFFh, G = 1Output Noise Density eNREF(1 kHz)— 1.2 — µV/√Hz Code = 0xFFFh, G = 1eNREF(10 kHz)— 1.0 — µV/√Hz Code = 0xFFFh, G = 11/f Corner Frequency fCORNER — 400 — HzOutput AmplifierOutput Swing VOUT — 0.010 toVDD – 0.040— Accuracy is better than 1 LSb forVOUT = 10 mV to (VDD – 40 mV)Phase Margin PM — 66 — °Slew Rate SR — 0.55 — V/µsShort Circuit Current ISC — 17 — mASettling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value from1/4 to 3/4 full-scale rangeDynamic PerformanceDAC-to-DAC Crosstalk — <10 — nV-s Note 2Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry(0111...1111 to1000...0000)Digital Feedthrough — <10 — nV-s Note 2Analog Crosstalk — <10 — nV-s Note 25V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED)Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x,RL = 5 kΩ to GND, CL = 100 pF. Typical values at +125°C by characterization or simulation.Parameters Sym Min Typ Max Units ConditionsNote 1: By design, not production tested.2: Too small to quantify.
  • 6. MCP4821/MCP4822DS21953A-page 6 © 2005 Microchip Technology Inc.AC CHARACTERISTICS (SPI™ TIMING SPECIFICATIONS)FIGURE 1-1: SPI™ Input Timing.Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.Typical values are at +25°C.Parameters Sym Min Typ Max Units ConditionsSchmitt Trigger High-LevelInput Voltage(All digital input pins)VIH 0.7 VDD — — VSchmitt Trigger Low-LevelInput Voltage(All digital input pins)VIL — — 0.2 VDD VHysteresis of Schmitt TriggerInputsVHYS — 0.05 VDD —Input Leakage Current ILEAKAGE -1 — 1 μA SHDN = LDAC = CS = SDI =SCK + VREF = VDD or AVSSDigital Pin Capacitance(All inputs/outputs)CIN,COUT— 10 — pF VDD = 5.0V, TA = +25°C,fCLK = 1 MHz (Note 1)Clock Frequency FCLK — — 20 MHz TA = +25°C (Note 1)Clock High Time tHI 15 — — ns Note 1Clock Low Time tLO 15 — — ns Note 1CS Fall to First Rising CLKEdgetCSSR 40 — — ns Applies only when CS falls withCLK high. (Note 1)Data Input Setup Time tSU 15 — — ns Note 1Data Input Hold Time tHD 10 — — ns Note 1SCK Rise to CS Rise HoldTimetCHS 15 — — ns Note 1CS High Time tCSH 15 — — ns Note 1LDAC Pulse Width tLD 100 — — ns Note 1LDAC Setup Time tLS 40 — — ns Note 1SCK Idle Time before CS Fall tIDLE 40 — — ns Note 1Note 1: By design and characterization, not production tested.CSSCKSILDACtCSSRtHDtSUtLOtCSHtCHSLSb inMSb intIDLEMode 1,1Mode 0,0tHItLDtLS
  • 7. © 2005 Microchip Technology Inc. DS21953A-page 7MCP4821/MCP4822TEMPERATURE CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, AVSS = GND.Parameters Sym Min Typ Max Units ConditionsTemperature RangesSpecified Temperature Range TA -40 — +125 °COperating Temperature Range TA -40 — +125 °C Note 1Storage Temperature Range TA -65 — +150 °CThermal Package ResistancesThermal Resistance, 8L-PDIP θJA — 85 — °C/WThermal Resistance, 8L-SOIC θJA — 163 — °C/WThermal Resistance, 8L-MSOP θJA — 206 — °C/WNote 1: The MCP482X family of DACs operate over this extended temperature range, but with reducedperformance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of+150°C.
  • 8. MCP4821/MCP4822DS21953A-page 8 © 2005 Microchip Technology Inc.2.0 TYPICAL PERFORMANCE CURVESNote: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF.FIGURE 2-1: DNL vs. Code.FIGURE 2-2: DNL vs. Code and AmbientTemperature.FIGURE 2-3: Absolute DNL vs. AmbientTemperature.FIGURE 2-4: INL vs. Code and AmbientTemperature.FIGURE 2-5: Absolute INL vs. AmbientTemperature.FIGURE 2-6: INL vs. Code.Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.-0.3-0.2-0.100.10.20.30 1024 2048 3072 4096Code (Decimal)DNL(LSB)-0.2-0.100.10.20 1024 2048 3072 4096Code (Decimal)DNL(LSB)125C 85C 25C0.0750.07520.07540.07560.07580.0760.07620.07640.0766-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)AbsoluteDNL(LSB)Note: Single device graph for illustration of 64code effect.-5-4-3-2-10123450 1024 2048 3072 4096Code (Decimal)INL(LSB)125C 85 25Ambient Temperature00.511.522.5-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)AbsoluteINL(LSB)-6-4-2020 1024 2048 3072 4096Code (Decimal)INL(LSB)
  • 9. © 2005 Microchip Technology Inc. DS21953A-page 9MCP4821/MCP4822Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF.FIGURE 2-7: Full-Scale VOUTA w/G = 1(VREF) vs. Ambient Temperature and VDD.FIGURE 2-8: Full-Scale VOUTA w/G = 2(2VREF) vs.Ambient Temperature and VDD.FIGURE 2-9: Output Noise VoltageDensity (VREF Noise Density w/G = 1) vs.Frequency.FIGURE 2-10: Output Noise Voltage (VREFNoise Voltage w/G = 1) vs. Bandwidth.2.0402.0412.0422.0432.0442.0452.0462.0472.0482.0492.050-40 -20 0 20 40 60 80 100 120Ambient Temperature (°C)FullScaleVOUT(V)VDD: 4VVDD: 3VVDD: 2.7V4.0764.0804.0844.0884.0924.0964.100-40 -20 0 20 40 60 80 100 120Ambient Temperature (°C)FullScaleVOUT(V)VDD: 5.5VVDD: 5V1.E-071.E-061.E-051.E-041E-1 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5Frequency (Hz)OutputNoiseVoltageDensity(μV/Hz)0.1 1 10 100 1k 10k 100k1001010.11.E-051.E-041.E-031.E-021E+2 1E+3 1E+4 1E+5 1E+6Bandwidth (Hz)OutputNoiseVoltage(mV)100 1k 10k 100k 1MEni (in VRMS)10.01.000.100.01Eni (in VP-P)Maximum Measurement Time = 10s
  • 10. MCP4821/MCP4822DS21953A-page 10 © 2005 Microchip Technology Inc.Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF.FIGURE 2-11: MCP4821 IDD vs. AmbientTemperature and VDD.FIGURE 2-12: MCP4821 IDD Histogram(VDD = 2.7V).FIGURE 2-13: MCP4821 IDD Histogram(VDD = 5.0V).FIGURE 2-14: MCP4822 IDD vs. AmbientTemperature and VDD.FIGURE 2-15: MCP4822 IDD Histogram(VDD = 2.7V).FIGURE 2-16: MCP4822 IDD Histogram(VDD = 5.0V).180200220240260280300320340-40 -20 0 20 40 60 80 100 120Ambient Temperature (°C)IDD(μA)VDD5.5V4.0V5.0V3.0V2.7V02468101214161820265270275280285290295300305310315320>320IDD (μA)Occurrence024681012141618285290295300305310315320325330335340345350>350IDD (μA)Occurrence300350400450500550600-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)IDD(μA)VDD5.5V4.0V5.0V3.0V2.7V0510152025380385390395400405410415420425430435440IDD (μA)Occurrence0246810121416182022385390395400405410415420425430435IDD (μA)Occurrence
  • 11. © 2005 Microchip Technology Inc. DS21953A-page 11MCP4821/MCP4822Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF.FIGURE 2-17: Hardware Shutdown Currentvs. Ambient Temperature and VDD.FIGURE 2-18: Software Shutdown Currentvs. Ambient Temperature and VDD.FIGURE 2-19: Offset Error vs. AmbientTemperature and VDD.FIGURE 2-20: Gain Error vs. AmbientTemperature and VDD.FIGURE 2-21: VIN High Threshold vs.Ambient Temperature and VDD.FIGURE 2-22: VIN Low Threshold vs.Ambient Temperature and VDD.00.10.20.30.40.50.60.7-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)ISHDN(μA)VDD5.5V4.0V5.0V3.0V2.7V11.522.533.54-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)ISHDN_SW(μA)VDD5.5V4.0V5.0V3.0V2.7V-0.03-0.010.010.030.050.070.090.11-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)OffsetError(%)VDD5.5V4.0V5.0V3.0V2.7V-0.5-0.45-0.4-0.35-0.3-0.25-0.2-0.15-0.1-0.05-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)GainError(%)VDD5.5V4.0V5.0V3.0V2.7V11.522.533.54-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)VINHiThreshold(V)VDD5.5V4.0V5.0V3.0V2.7V0.80.911.11.21.31.41.51.6-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)VINLowThreshold(V)VDD5.5V4.0V5.0V3.0V2.7V
  • 12. MCP4821/MCP4822DS21953A-page 12 © 2005 Microchip Technology Inc.Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF.FIGURE 2-23: Input Hysteresis vs. AmbientTemperature and VDD.FIGURE 2-24: VOUT High Limit vs. AmbientTemperature and VDD.FIGURE 2-25: VOUT Low Limit vs. AmbientTemperature and VDD.FIGURE 2-26: IOUT High Short vs. AmbientTemperature and VDD.FIGURE 2-27: IOUT vs. VOUT. Gain = 2.00.250.50.7511.251.51.7522.252.5-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)VIN_SPIHysteresis(V)VDD5.5V4.0V5.0V3.0V2.7V0.0150.0170.0190.0210.0230.0250.0270.0290.0310.0330.035-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)VOUT_HILimit(VDD-Y)(V)VDD4.0V3.0V2.7V0.00100.00120.00140.00160.00180.00200.00220.00240.00260.0028-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)VOUT_LOWLimit(Y-AVSS)(V)VDD5.5V4.0V5.0V3.0V2.7V10111213141516-40 -20 0 20 40 60 80 100 120Ambient Temperature (ºC)IOUT_HI_SHORTED(mA)VDD5.5V4.0V5.0V3.0V2.7V0.01.02.03.04.05.06.00 2 4 6 8 10 12 14 16IOUT (mA)VOUT(V)VREF = 4.096VOutput Shorted to VSSOutput Shorted to VDD
  • 13. © 2005 Microchip Technology Inc. DS21953A-page 13MCP4821/MCP4822Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF.FIGURE 2-28: VOUT Rise Time 100%.FIGURE 2-29: VOUT Fall Time.FIGURE 2-30: VOUT Rise Time 50%.FIGURE 2-31: VOUT Rise Time 25% - 75%.FIGURE 2-32: VOUT Rise Time ExitShutdown.FIGURE 2-33: PSRR vs. Frequency.VOUTSCKLDACTime (1 µs/div)VOUTSCKLDACTime (1 µs/div)VOUTSCKLDACTime (1 µs/div)Time (1 µs/div)VOUTLDACTime (1 µs/div)VOUTSCKLDACRippleRejection(dB)Frequency (Hz)
  • 14. MCP4821/MCP4822DS21953A-page 14 © 2005 Microchip Technology Inc.3.0 PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 3-1.TABLE 3-1: PIN FUNCTION TABLE3.1 Positive Power Supply Input (VDD)VDD is the positive power supply input. The input powersupply is relative to AVSS and can range from 2.7V to5.5V. A decoupling capacitor on VDD is recommendedto achieve maximum performance.3.2 Chip Select (CS)CS is the chip select input, which requires an active-lowsignal to enable serial clock and data functions.3.3 Serial Clock Input (SCK)SCK is the SPI compatible serial clock input.3.4 Serial Data Input (SDI)SDI is the SPI compatible serial data input.3.5 Latch DAC Input (LDAC)LDAC (the latch DAC synchronization input) transfersthe input latch registers to the DAC registers (outputlatches) when low. Can also be tied low if transfer onthe rising edge of CS is desired.3.6 Hardware Shutdown Input (SHDN)SHDN is the hardware shutdown input that requires anactive-low input signal to configure the DACs in theirlow-power Standby mode.3.7 DACx Outputs (VOUTA, VOUTB)VOUTA and VOUTB are DAC outputs. The DAC outputamplifier drives these pins with a range of AVSS to VDD.3.8 Analog Ground (AVSS)AVSS is the analog ground pin.MCP4821Pin No.MCP4822Pin No.Symbol Function1 1 VDD Positive Power Supply Input (2.7V to 5.5V)2 2 CS Chip Select Input3 3 SCK Serial Clock Input4 4 SDI Serial Data Input5 5 LDAC Synchronization input used to transfer DAC settings from seriallatches to output latches6 — SHDN Hardware Shutdown Input— 6 VOUTB DACB Output7 7 AVSS Analog Ground8 8 VOUTA DACA Output
  • 15. © 2005 Microchip Technology Inc. DS21953A-page 15MCP4821/MCP48224.0 GENERAL OVERVIEWThe MCP482X devices are voltage-output string DACs.These devices include rail-to-rail output amplifiers,internal voltage reference, shutdown and reset-man-agement circuitry. Serial communication conforms tothe SPI protocol. The MCP482X devices operate from2.7V to 5.5V supplies.The coding of these devices is straight binary, with theideal output voltage given by Equation 4-1, where G isthe selected gain (1x or 2x), DN represents the digitalinput value and n represents the number of bits ofresolution (n = 12).EQUATION 4-1: LSb SIZE1 LSb is the ideal voltage difference between twosuccessive codes. Table 4-1 illustrates how to calculateLSb.4.0.1 INL ACCURACYINL error for these devices is the maximum deviationbetween an actual code transition point and its corre-sponding ideal transition point once offset and gainerrors have been removed. These endpoints are from0x000 to 0xFFF. Refer to Figure 4-1.Positive INL represents transition(s) later than ideal.Negative INL represents transition(s) earlier than ideal.FIGURE 4-1: INL Accuracy.4.0.2 DNL ACCURACYDNL error is the measure of variations in code widthsfrom the ideal code width. A DNL error of zero wouldimply that every code is exactly 1 LSb wide.FIGURE 4-2: DNL Accuracy.4.0.3 OFFSET ERROROffset error is the deviation from zero voltage outputwhen the digital input code is zero.4.0.4 GAIN ERRORGain error is the deviation from the ideal output,VREF – 1 LSb, excluding the effects of offset error.TABLE 4-1: LSb SIZESDevice Gain LSb SizeMCP482X 1x 2.048V/4096MCP482X 2x 4.096V/4096VOUT2.048V G DN⋅ ⋅2n--------------------------------------=111110101100011010001000DigitalInputCodeActualTransferFunctionINL < 0Ideal TransferFunctionINL < 0DAC Output111110101100011010001000DigitalInputCodeActualTransferFunctionIdeal TransferFunctionNarrow Code < 1 LSbDAC OutputWide Code > 1 LSb
  • 16. MCP4821/MCP4822DS21953A-page 16 © 2005 Microchip Technology Inc.4.1 Circuit Descriptions4.1.1 OUTPUT AMPLIFIERSThe DACs’ outputs are buffered with a low-power,precision CMOS amplifier. This amplifier provides lowoffset voltage and low noise. The output stage enablesthe device to operate with output voltages close to thepower supply rails. Refer to Section 1.0 “ElectricalCharacteristics” for range and load conditions.In addition to resistive load-driving capability, the ampli-fier will also drive high capacitive loads without oscilla-tion. The amplifiers’ strong outputs allow VOUT to beused as a programmable voltage reference in asystem.4.1.1.1 Programmable Gain BlockThe rail-to-rail output amplifier has configurable gain,allowing optimal full-scale outputs for differing voltagereference inputs. The output amplifier gain has twoselections, a gain of 1 V/V (GA = 1) or a gain of 2 V/V(GA = 0).The output range is ideally 0.000V to 4095/4096 *2.048V when G = 1, and 0.000 to 4095/4096 * 4.096Vwhen G = 2. The default value for this bit is a gain of 2,yielding an ideal full-scale output of 0.000V to 4.096Vdue to the internal 2.048V VREF. Note that the near rail-to-rail CMOS output buffer’s ability to approach AVSSand VDD establish practical range limitations. Theoutput swing specification in Section 1.0 “ElectricalCharacteristics” defines the range for a given loadcondition.4.1.2 VOLTAGE REFERENCEThe MCP482X devices utilize internal 2.048V voltagereference. The voltage reference has low temperaturecoefficient and low noise characteristics. Refer toSection 1.0 “Electrical Characteristics” for thevoltage reference specifications.4.1.3 POWER-ON RESET CIRCUITThe Power-On Reset (POR) circuit ensures that theDACs power-up with SHDN = 0 (high-impedance). Thedevices will continue to have a high-impedance outputuntil a valid Write command is performed to either ofthe DAC registers and the LDAC pin meets the inputlow threshold.If the power supply voltage is less than the PORthreshold (VPOR = 2.0V, typical), the DACs will be heldin their reset state. They will remain in that state untilVDD > VPOR and a subsequent Write command isreceived.Figure 4-3 shows a typical power supply transientpulse and the duration required to cause a reset tooccur, as well as the relationship between the durationand trip voltage. A 0.1 µF decoupling capacitor,mounted as close as possible to the VDD pin, providesadditional transient immunity.FIGURE 4-3: Typical Transient Response.4.1.4 SHUTDOWN MODEShutdown mode can be entered by using either hard-ware or software commands. The hardware pin(SHDN) is only available on the MCP4821. DuringShutdown mode, the supply current is isolated frommost of the internal circuitry. The serial interfaceremains active, thus allowing a Write command tobring the device out of Shutdown mode. When the out-put amplifiers are shut down, the feedback resistance(typically 500 kΩ) produces a high-impedance path toAVSS. The device will remain in Shutdown mode untilthe SHDN pin is brought high and a write commandwith SD = 1 is latched into the device. When a DAC ischanged from Shutdown to Active mode, the outputsettling time takes < 10 µs, but greater than thestandard Active mode settling time (4.5 µs).Transients above the curvewill cause a resetTransients below the curvewill NOT cause a reset5VTimeSupplyVoltagesTransient DurationVPORVDD - VPORTA = +25°CTransientDuration(µs)10864201 2 3 4 5VDD – VPOR (V)
  • 17. © 2005 Microchip Technology Inc. DS21953A-page 17MCP4821/MCP48225.0 SERIAL INTERFACE5.1 OverviewThe MCP482X family is designed to interface directlywith the SPI port, available on many microcontrollers,and supports Mode 0,0 and Mode 1,1. Commands anddata are sent to the device via the SDI pin, with databeing clocked-in on the rising edge of SCK. Thecommunications are unidirectional and, thus, datacannot be read out of the MCP482X devices. The CSpin must be held low for the duration of a write com-mand. The write command consists of 16 bits and isused to configure the DAC’s control and data latches.Register 5-1 details the input registers used toconfigure and load the DACA and DACB registers.Refer to Figure 1-1 and the AC ElectricalCharacteristics tables for detailed input and output tim-ing specifications for both Mode 0,0 and Mode 1,1operation.5.2 Write CommandThe write command is initiated by driving the CS pinlow, followed by clocking the four configuration bits andthe 12 data bits into the SDI pin on the rising edge ofSCK. The CS pin is then raised, causing the data to belatched into the selected DAC’s input registers. TheMCP482X devices utilize a double-buffered latch struc-ture to allow both DACA’s and DACB’s outputs to besynchronized with the LDAC pin, if desired. Upon theLDAC pin achieving a low state, the values held in theDAC’s input registers are transferred into the DACs’output registers. The outputs will transition to the valueand held in the DACX register.All writes to the MCP482X devices are 16-bit words.Any clocks past 16 will be ignored. The most signifi-cant four bits are configuration bits. The remaining 12bits are data bits. No data can be transferred into thedevice with CS high. This transfer will only occur if 16clocks have been transferred into the device. If therising edge of CS occurs prior, shifting of data into theinput registers will be aborted.REGISTER 5-1: WRITE COMMAND REGISTERbit 15 A/B: DACA or DACB Select bit1 = Write to DACB0 = Write to DACAbit 14 — Don’t Carebit 13 GA: Output Gain Select bit1 = 1x (VOUT = VREF * D/4096)0 = 2x (VOUT = 2 * VREF * D/4096)bit 12 SHDN: Output Power-down Control bit1 = Output Power-down Control bit0 = Output buffer disabled, Output is high-impedancebit 11-0 D11:D0: DAC Data bits12-bit number “D” which sets the output value. Contains a value between 0 and 4095.Upper Half:W-x W-x W-x W-0 W-x W-x W-x W-xA/B — GA SHDN D11 D10 D9 D8bit 15 bit 8Lower Half:W-x W-x W-x W-x W-x W-x W-x W-xD7 D6 D5 D4 D3 D2 D1 D0bit 7 bit 0LegendR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
  • 18. MCP4821/MCP4822DS21953A-page 18 © 2005 Microchip Technology Inc.FIGURE 5-1: Write Command.SDISCKCS0 21A/B — GA SHDN D11 D10config bits 12 data bitsLDAC3 4D95 6 7D8 D7 D68 9 10 12D5 D4 D3 D2 D1 D011 13 14 15VOUT(Mode 1,1)(Mode 0,0)
  • 19. © 2005 Microchip Technology Inc. DS21953A-page 19MCP4821/MCP48226.0 TYPICAL APPLICATIONSThe MCP482X devices are general purpose DACsintended to be used in applications where a precision,low-power DAC with moderate bandwidth and internalvoltage reference is required.Applications generally suited for the MCP482X devicesinclude:• Set Point or Offset Trimming• Sensor Calibration• Precision Selectable Voltage Reference• Portable Instrumentation (Battery-Powered)• Calibration of Optical Communication Devices6.1 Digital InterfaceThe MCP482X devices utilize a 3-wire synchronousserial protocol to transfer the DACs’ setup and outputvalues from the digital source. The serial protocol canbe interfaced to SPI™ or Microwire peripherals com-mon on many microcontroller units (MCUs), includingMicrochip’s PICmicro®MCUs and dsPIC®DSC familyof MCUs. In addition to the three serial connections(CS, SCK and SDI), the LDAC signal synchronizeswhen the serial settings are latched into the DAC’soutput from the serial input latch. Figure 6-1 illustratesthe required connections. Note that LDAC is active-low.If desired, this input can be tied low to reduce therequired connections from 4 to 3. Write commands willbe latched directly into the output latch when a valid 16clock transmission has been received and CS hasbeen raised.6.2 Power Supply ConsiderationsThe typical application will require a bypass capacitorin order to filter high-frequency noise. The noise can beinduced onto the power supplys traces or as a result ofchanges on the DACs output. The bypass capacitorhelps to minimize the effect of these noise sources onsignal integrity. Figure 6-1 illustrates an appropriatebypass strategy.In this example, the recommended bypass capacitorvalue is 0.1 µF. This capacitor should be placed asclose to the device power pin (VDD) as possible (within4 mm).The power source supplying these devices should beas clean as possible. If the application circuit has sep-arate digital and analog power supplies, AVDD andAVSS should reside on the analog plane.6.3 Output Noise ConsiderationsThe voltage noise density (in µV/√Hz) is illustrated inFigure 2-9. This noise appears at VOUTX, and is prima-rily a result of the internal reference voltage. Its 1/fcorner (fCORNER) is approximately 400 Hz.Figure 2-10 illustrates the voltage noise (in mVRMS ormVP-P). A small bypass capacitor on VOUTX is aneffective method to produce a single-pole Low-PassFilter (LPF) that will reduce this noise. For instance, abypass capacitor sized to produce a 1 kHz LPF wouldresult in an ENREF of about 100 µVRMS. This would benecessary when trying to achieve the low DNLperformance (at G = 1) that the MCP482X devices arecapable of. The tested range for stability is .001µF thru4.7 µF.FIGURE 6-1: Typical ConnectionDiagram.6.4 Layout ConsiderationsInductively-coupled AC transients and digital switchingnoise can degrade the output signal integrity,potentially masking the MCP482X family’sperformance. Careful board layout will minimize theseeffects and increase the Signal-to-Noise Ratio (SNR).Bench testing has shown that a multi-layer boardutilizing a low-inductance ground plane, isolated inputs,isolated outputs and proper decoupling are critical toachieving the performance that the MCP482X devicesare capable of providing. Particularly harshenvironments may require shielding of critical signals.Breadboards and wire-wrapped boards are notrecommended if low noise is desired.MCP482XVDDVDD VDDAVSSAVSS AVSSVOUTAVOUTBMCP482X0.1 µFPICmicro®Microcontroller0.1 µF 0.1 µFVOUTAVOUTBSDISDICS1SDOSCKLDACCS01 µF1 µF
  • 20. MCP4821/MCP4822DS21953A-page 20 © 2005 Microchip Technology Inc.6.5 Single-Supply OperationThe MCP482X devices are Rail-to-Rail (R-R) input andoutput DACs designed to operate with a VDD range of2.7V to 5.5V. Its output amplifier is robust enough todrive common, small-signal loads directly, thus eliminat-ing the cost and size of an external buffer for mostapplications.6.5.1 DC SET POINT OR CALIBRATIONA common application for a DAC with the MCP482Xfamily’s performance is a digitally-controlled set pointand/or calibration of variable parameters, such as sen-sor offset or slope. 12-bit resolution provides 4096 out-put steps. If G = 1 is selected, then the internal 2.048VREF would produce 500 µV of resolution. If G = 2 isselected, the internal 2.048 VREF would produce 1 mVof resolution.6.5.1.1 Decreasing The Output Step SizeIf the application is calibrating the threshold of a diode,transistor or resistor tied to AVSS, a threshold range of0.8V may be desired to provide 200 µV resolution. Twocommon methods to achieve a 0.8V range is to eitherreduce VREF to 0.82V (would require MCP492X deviceand external voltage reference) or use a voltage divideron the DAC’s output. Typically, when using a low-voltage VREF, the noise floor causes SNR error that isintolerable. The voltage divider method provides someadvantages when VREF needs to be very low or whenthe desired output voltage is not available. Using tworesistors to scale the output range down to the precisedesired level is a simple, low-cost method to achievevery small step sizes. Example 6-1 illustrates thisconcept. Note that the bypass capacitor on the outputof the voltage divider plays a critical function inattenuating the output noise of the DAC and theinduced noise from the environment.The MCP482X family’s low ±0.75 (max.) DNLperformance is critical to meeting calibration accuracyin production.EXAMPLE 6-1: Set Point or Threshold Calibration.MCP482XVDDSPI™3VTRIPR1R20.1 uFComparatorG = Gain select (1x or 2x)D = Digital value of DAC (0 – 4096)VOUT 2.048 GD212---------⋅=VCC+VCC–VOUTVtrip VOUTR2R1 R2+--------------------⎝ ⎠⎜ ⎟⎛ ⎞=VDDRSENSE
  • 21. © 2005 Microchip Technology Inc. DS21953A-page 21MCP4821/MCP48226.5.1.2 Building a “Window” DACWhen calibrating a set point or threshold of a sensor,rarely does the sensor utilize the entire output range ofthe DAC. If the LSb size is adequate to meet the appli-cation’s accuracy needs, the resolution is sacrificedwithout consequences. If greater accuracy is needed,then the output range will need to be reduced toincrease the resolution around the desired threshold. Ifthe threshold is not near VREF, 2VREF or AVSS, thencreating a “window” around the threshold has severaladvantages. One simple method to create this“window” is to use a voltage divider network with a pull-up and pull-down resistor. Example 6-2 andExample 6-4 illustrates this concept.The MCP482X family’s low ±0.75 (max.) DNLperformance is critical to meet calibration accuracy inproduction.EXAMPLE 6-2: Single-Supply “Window” DAC.MCP482XVDDSPI™3VTRIPR1R2 0.1 µFComparatorR3VCC-G = Gain select (1x or 2x)D = Digital value of DAC (0 – 4096)VCC+VCC+VCC-VOUTVOUT 2.048 GD212-------⋅=R23R2R3R2 R3+------------------=V23VCC+R2( ) VCC-R3( )+R2 R3+------------------------------------------------------=VtripVOUTR23 V23R1+R2 R23+--------------------------------------------=R1R23V23VOUT VOTheveninEquivalentRSENSE
  • 22. MCP4821/MCP4822DS21953A-page 22 © 2005 Microchip Technology Inc.6.6 Bipolar OperationBipolar operation is achievable using the MCP482Xdevices by using an external operational amplifier (opamp). This configuration is desirable due to the widevariety and availability of op amps. This allows a gen-eral purpose DAC, with its cost and availability advan-tages, to meet almost any desired output voltagerange, power and noise performance.Example 6-3 illustrates a simple bipolar voltage sourceconfiguration. R1 and R2 allow the gain to be selected,while R3 and R4 shift the DACs output to a selectedoffset. Note that R4 can be tied to VDD, instead of AVSS,if a higher offset is desired. Note that a pull-up to VDDcould be used, instead of R4 or in addition to R4, if ahigher offset is desired.EXAMPLE 6-3: Digitally-Controlled Bipolar Voltage Source.6.6.1 DESIGN A BIPOLAR DAC USINGEXAMPLE 6-3An output step magnitude of 1 mV, with an output rangeof ±2.05V, is desired for a particular application.1. Calculate the range: +2.05V – (-2.05V) = 4.1V.2. Calculate the resolution needed:4.1V/1 mV = 4100Since 212 = 4096, 12-bit resolution is desired.3. The amplifier gain (R2/R1), multiplied by full-scale VOUT (4.096V), must be equal to thedesired minimum output to achieve bipolaroperation. Since any gain can be realized bychoosing resistor values (R1+R2), the VREFvalue must be selected first. If a VREF of 4.096Vis used (G=2), solve for the amplifier’s gain bysetting the DAC to 0, knowing that the outputneeds to be -2.05V. The equation can besimplified to:4. Next, solve for R3 and R4 by setting the DAC to4096, knowing that the output needs to be+2.05V.MCP482XVDDVDDSPI™3VOUTR3R4R2R1VIN+G = Gain select (1x or 2x)D = Digital value of DAC (0 – 4096)0.1 µFVCC+VCC–VOUT 2.048 GD212-------⋅=VIN+VOUTR4R3 R4+--------------------=VOVO VIN+ 1R2R1------+⎝ ⎠⎛ ⎞ VDDR2R1------⎝ ⎠⎛ ⎞–=R2–R1---------2.05–4.096V-----------------=If R1 = 20 kΩ and R2 = 10 kΩ, the gain will be 0.5R2R1------12---=R4R3 R4+( )-----------------------2.05V 0.5 4.096V⋅( )+1.5 4.096V⋅-------------------------------------------------------23---= =If R4 = 20 kΩ, then R3 = 10 kΩ
  • 23. © 2005 Microchip Technology Inc. DS21953A-page 23MCP4821/MCP48226.7 Selectable Gain and Offset BipolarVoltage Output Using A Dual DACIn some applications, precision digital control of theoutput range is desirable. Example 6-4 illustrates howto use the MCP482X family to achieve this in a bipolaror single-supply application.This circuit is typically used for linearizing a sensorwhose slope and offset varies.The equation to design a bipolar “window” DAC wouldbe utilized if R3, R4 and R5 are populated.EXAMPLE 6-4: Bipolar Voltage Source with Selectable Gain and Offset.MCP482XVDDR3R4R2VOMCP482XVDDR1DACA (Gain Adjust)DACB (Offset Adjust)SPI™3R5VCC+TheveninBipolar “Window” DAC using R4 and R5G = Gain select (1x or 2x)D = Digital value of DAC (0 – 4096)0.1 µFVCC–AVSS = GNDVCC+VCC–VOUTB 2.048V GB⋅( )DB212-------=VOUTAVOUTBVOUTA 2.048V GA⋅( )DA212-------=VIN+VOUTBR4 VCC-R3+R3 R4+------------------------------------------------=VO VIN+ 1R2R1------+⎝ ⎠⎛ ⎞ VOUTAR2R1------⎝ ⎠⎛ ⎞–=Equivalent V45VCC+R4 VCC-R5+R4 R5+--------------------------------------------= R45R4R5R4 R5+------------------=VIN+VOUTBR45 V45R3+R3 R45+-----------------------------------------------= VO VIN+ 1R2R1------+⎝ ⎠⎛ ⎞ VOUTAR2R1------⎝ ⎠⎛ ⎞–=Offset Adjust Gain AdjustOffset Adjust Gain Adjust
  • 24. MCP4821/MCP4822DS21953A-page 24 © 2005 Microchip Technology Inc.6.8 Designing A Double-PrecisionDAC Using A Dual DACExample 6-5 illustrates how to design a single-supplyvoltage output capable of up to 24-bit resolution from adual 12-bit DAC. This design is simply a voltage dividerwith a buffered output.As an example, if a similar application to the onedeveloped in Section 6.6.1 “Design a Bipolar DACUsing Example 6-3” required a resolution of 1 µVinstead of 1 mV, and a range of 0V to 4.1V, then 12-bitresolution would not be adequate.1. Calculate the resolution needed:4.1V/1 µV = 4.1e06. Since 222= 4.2e06, 22-bitresolution is desired. Since DNL = ±0.75 LSb,this design can be attempted with the MCP482Xfamily.2. Since DACB‘s VOUTB has a resolution of 1 mV,its output only needs to be “pulled” 1/1000 tomeet the 1 µV target. Dividing VOUTA by 1000would allow the application to compensate forDACB‘s DNL error.3. If R2 is 100Ω, then R1 needs to be 100 kΩ.4. The resulting transfer function is shown in theequation of Example 6-5.EXAMPLE 6-5: Simple, Double-Precision DAC.MCP482XVDDR2VOMCP482XVDDR1DACA (Fine Adjust)DACB (Course Adjust)SPI™3R1 >> R2VOVOUTAR2 VOUTBR1+R1 R2+-----------------------------------------------------=G = Gain select (1x or 2x)D = Digital value of DAC (0 – 4096)0.1 µFVCC+VCC–VOUTA 2.048V GADA212-------⋅= VOUTB 2.048V GBDB212-------⋅=VOUTAVOUTB
  • 25. © 2005 Microchip Technology Inc. DS21953A-page 25MCP4821/MCP48226.9 Building A Programmable CurrentSourceExample 6-6 illustrates a variation on a voltage followerdesign where a sense resistor is used to convert theDAC’s voltage output into a digitally-selectable currentsource.Adding the resistor network from Example 6-2 wouldbe advantageous in this application. The smallerRSENSE is, the less power dissipated across it.However, this also reduces the resolution that thecurrent can be controlled with. The voltage divider, or“window”, DAC configuration would allow the range tobe reduced, thus increasing resolution around therange of interest. When working with very small sensorvoltages, plan on eliminating the amplifiers offset errorby storing the DACs setting under known sensorconditions.EXAMPLE 6-6: Digitally-Controlled CurrentSource.MCP482XRsenseIbLoadILVDDSPI™3VCC+VCC–VOUTG = Gain select (1x or 2x)D = Digital value of DAC (0 – 4096)ILVOUTRsense---------------ββ 1+------------×=VOUT 2.048V GD212-------⋅=IbILβ----=
  • 26. MCP4821/MCP4822DS21953A-page 26 © 2005 Microchip Technology Inc.7.0 DEVELOPMENT SUPPORT7.1 Evaluation & DemonstrationBoardsThe Mixed Signal PICtail™Demo Board supports theMCP482X family of devices. Refer towww.microchip.com for further information on thisproduct’s capabilities and availability.7.2 Application NotesApplication notes illustrating the performance andimplementation of the MCP482X family are planned butare currently not released. Refer towww.microchip.com for further information.
  • 27. © 2005 Microchip Technology Inc. DS21953A-page 27MCP4821/MCP48228.0 PACKAGING INFORMATION8.1 Package Marking InformationXXXXXXXXXXXXXNNNYYWW8-Lead PDIP (300 mil) Example:8-Lead SOIC (150 mil) Example:XXXXXXXXXXXXYYWWNNNMCP4821E/P ^ 2560524MCP4821ESN^^ 05242568-Lead MSOP Example:XXXXXXYWWNNN4821E524256Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability codePb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )can be found on the outer packaging for this package.Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.3e3e3e3e
  • 28. MCP4821/MCP4822DS21953A-page 28 © 2005 Microchip Technology Inc.8-Lead Plastic Micro Small Outline Package (MS) (MSOP)DAA1Lc(F)αA2E1EpBn 12φβ5°5° --Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not.037 REFFFootprint (Reference)exceed .010" (0.254mm) per side.Notes:Drawing No. C04-111*Controlling ParameterMold Draft Angle TopMold Draft Angle BottomFoot AngleLead WidthLead ThicknessβαcBφ.003.009.006.012Dimension LimitsOverall HeightMolded Package ThicknessMolded Package WidthOverall LengthFoot LengthStandoffOverall WidthNumber of PinsPitchALE1DA1EA2.016 .024.118 BSC.118 BSC.000.030.193 TYP..033MINpnUnits.026 BSCNOM8INCHES0.95 REF--.009.0160.080.220°0.230.408°MILLIMETERS*0.65 BSC0.853.00 BSC3.00 BSC0.604.90 BSC.043.031.037.0060.400.000.75MINMAX NOM1.100.800.150.95MAX8- --15°5° -15°5° -JEDEC Equivalent: MO-1870° - 8°5°5° --15°15°--- -
  • 29. © 2005 Microchip Technology Inc. DS21953A-page 29MCP4821/MCP48228-Lead Plastic Dual In-line (P) – 300 mil (PDIP)B1BA1ALA2pαEeBβcE1nD12Units INCHES* MILLIMETERSDimension Limits MIN NOM MAX MIN NOM MAXNumber of Pins n 8 8Pitch p .100 2.54Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68Base to Seating Plane A1 .015 0.38Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60Overall Length D .360 .373 .385 9.14 9.46 9.78Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43Lead Thickness c .008 .012 .015 0.20 0.29 0.38Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78Lower Lead Width B .014 .018 .022 0.36 0.46 0.56Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92Mold Draft Angle Top α 5 10 15 5 10 15Mold Draft Angle Bottom β 5 10 15 5 10 15* Controlling ParameterNotes:Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceedJEDEC Equivalent: MS-001Drawing No. C04-018.010” (0.254mm) per side.§ Significant Characteristic
  • 30. MCP4821/MCP4822DS21953A-page 30 © 2005 Microchip Technology Inc.8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)Foot Angle φ 0 4 8 0 4 81512015120βMold Draft Angle Bottom1512015120αMold Draft Angle Top0.510.420.33.020.017.013BLead Width0.250.230.20.010.009.008cLead Thickness0.760.620.48.030.025.019LFoot Length0.510.380.25.020.015.010hChamfer Distance5.004.904.80.197.193.189DOverall Length3.993.913.71.157.154.146E1Molded Package Width6.206.025.79.244.237.228EOverall Width0.250.180.10.010.007.004A1Standoff §1.551.421.32.061.056.052A2Molded Package Thickness1.751.551.35.069.061.053AOverall Height1.27.050pPitch88nNumber of PinsMAXNOMMINMAXNOMMINDimension LimitsMILLIMETERSINCHES*Units21DnpBEE1hLβc45°φA2αAA1* Controlling ParameterNotes:Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.010” (0.254mm) per side.JEDEC Equivalent: MS-012Drawing No. C04-057§ Significant Characteristic
  • 31. © 2005 Microchip Technology Inc. DS21953A-page 31MCP4821/4822APPENDIX A: REVISION HISTORYRevision A (June 2005)• Original Release of this Document.
  • 32. MCP4821/4822DS21953A-page 32 © 2005 Microchip Technology Inc.NOTES:
  • 33. © 2005 Microchip Technology Inc. DS21953A-page 33MCP4821/4822PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.Device: MCP4821: 12-Bit DAC with SPI™ InterfaceMCP4821T: 12-Bit DAC with SPI Interface(Tape and Reel) (SOIC, MSOP)MCP4822: 12-Bit DAC with SPI InterfaceMCP4822T: 12-Bit DAC with SPI Interface(Tape and Reel) (SOIC, MSOP)Temperature Range: E = -40°C to +125°CPackage: MS = Plastic MSOP, 8-leadP = Plastic DIP (300 mil Body), 8-leadSN = Plastic SOIC, (150 mil Body), 8-leadPART NO. X /XXPackageTemperatureRangeDeviceExamples:a) MCP4821T-E/SN: Tape and ReelExtended Temperature,8LD SOIC package.b) MCP4821T-E/MS: Tape and ReelExtended Temperature,8LD MSOP package.c) MCP4821-E/SN: Extended Temperature,8LD SOIC package.d) MCP4821-E/MS: Extended Temperature,8LD MSOP package.e) MCP4821-E/P: Extended Temperature,8LD PDIP package.a) MCP4822T-E/SN: Tape and ReelExtended Temperature,8LD SOIC package.b) MCP4822-E/P: Extended Temperature,8LD PDIP package.c) MCP4822-E/SN: Extended Temperature,8LD SOIC package.
  • 34. MCP4821/4822DS21953A-page 34 © 2005 Microchip Technology Inc.NOTES:
  • 35. © 2005 Microchip Technology Inc. DS21953A-page 35Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS OR WAR-RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,WRITTEN OR ORAL, STATUTORY OR OTHERWISE,RELATED TO THE INFORMATION, INCLUDING BUT NOTLIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,MERCHANTABILITY OR FITNESS FOR PURPOSE.Microchip disclaims all liability arising from this information andits use. Use of Microchip’s products as critical components inlife support systems is not authorized except with expresswritten approval by Microchip. No licenses are conveyed,implicitly or otherwise, under any Microchip intellectual propertyrights.TrademarksThe Microchip name and logo, the Microchip logo, Accuron,dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,PICSTART, PRO MATE, PowerSmart, rfPIC, andSmartShunt are registered trademarks of MicrochipTechnology Incorporated in the U.S.A. and other countries.AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,PICMASTER, SEEVAL, SmartSensor and The EmbeddedControl Solutions Company are registered trademarks ofMicrochip Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, dsPICDEM,dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,FanSense, FlexROM, fuzzyLAB, In-Circuit SerialProgramming, ICSP, ICEPIC, Linear Active Thermistor,MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,Smart Serial, SmartTel, Total Endurance and WiperLock aretrademarks of Microchip Technology Incorporated in theU.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporatedin the U.S.A.All other trademarks mentioned herein are property of theirrespective companies.© 2005, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.Printed on recycled paper.Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Microchip received ISO/TS-16949:2002 quality system certification forits worldwide headquarters, design and wafer fabrication facilities inChandler and Tempe, Arizona and Mountain View, California inOctober 2003. The Company’s quality system processes andprocedures are for its PICmicro®8-bit MCUs, KEELOQ®code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the designand manufacture of development systems is ISO 9001:2000 certified.
  • 36. DS21953A-page 36 © 2005 Microchip Technology Inc.AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support:http://support.microchip.comWeb Address:www.microchip.comAtlantaAlpharetta, GATel: 770-640-0034Fax: 770-640-0307BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitFarmington Hills, MITel: 248-538-2250Fax: 248-538-2260KokomoKokomo, INTel: 765-864-8360Fax: 765-864-8387Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608San JoseMountain View, CATel: 650-215-1444Fax: 650-961-0286TorontoMississauga, Ontario,CanadaTel: 905-673-0699Fax: 905-673-6509ASIA/PACIFICAustralia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8528-2100Fax: 86-10-8528-2104China - ChengduTel: 86-28-8676-6200Fax: 86-28-8676-6599China - FuzhouTel: 86-591-8750-3506Fax: 86-591-8750-3521China - Hong Kong SARTel: 852-2401-1200Fax: 852-2401-3431China - ShanghaiTel: 86-21-5407-5533Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660Fax: 86-755-8203-1760China - ShundeTel: 86-757-2839-5507Fax: 86-757-2839-5571China - QingdaoTel: 86-532-502-7355Fax: 86-532-502-7205ASIA/PACIFICIndia - BangaloreTel: 91-80-2229-0061Fax: 91-80-2229-0062India - New DelhiTel: 91-11-5160-8631Fax: 91-11-5160-8632Japan - KanagawaTel: 81-45-471- 6166Fax: 81-45-471-6122Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or82-2-558-5934Malaysia - PenangTel:011-604-646-8870Fax:011-604-646-5086Philippines - ManilaTel: 011-632-634-9065Fax: 011-632-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - KaohsiungTel: 886-7-536-4818Fax: 886-7-536-4803Taiwan - TaipeiTel: 886-2-2500-6610Fax: 886-2-2508-0102Taiwan - HsinchuTel: 886-3-572-9526Fax: 886-3-572-6459EUROPEAustria - WeisTel: 43-7242-2244-399Fax: 43-7242-2244-393Denmark - BallerupTel: 45-4450-2828Fax: 45-4485-2829France - MassyTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - IsmaningTel: 49-89-627-144-0Fax: 49-89-627-144-44Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340England - BerkshireTel: 44-118-921-5869Fax: 44-118-921-5820WORLDWIDE SALES AND SERVICE04/20/05