Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC


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Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC

  1. 1. Presented By Guided By RAVITESH BAJPAI Prof. SHIVENDRA SINGH 0111EC07MT09 ASSISTANT PROFESSER Department of Electronics and Communication Engineering Technocrats Institute of Technology Bhopal M.P4/3/2013 1
  3. 3. To design and implement an AMBA based advanced DMA controller which can support hardware triggers, linking operation and channel chaining transfer.  provide three dimensions transmission. which can perform data block moving, data sorting and subframe extraction of various data structures. which can completes data transfer of different width of read and write. which can decrease the power consumption. Which can achieves AHB bus and APB bus to run in parallel. Which could adopt buffer and non-buffer data transfer mode according to the speed of equipments.4/3/2013 3
  5. 5. What is SoC ? System-on-Chip Chip + Software + Integration =Soc The SoC chip includes: -Embedded processo - ASIC Logics and analog circuitry - Embedded memory4/3/2013 5
  6. 6. What is a DMAStands for "Direct MemoryAccess.“ DMA is a method oftransferring data from thecomputers RAM to another partof the computer withoutprocessing it using the CPUAllows data to be sent directlyfrom an attached device (suchas a disk drive) tothememory on thecomputers motherboard. 4/3/2013 6
  7. 7. What is AMBA(AMBA) =The Advanced MicrocontrollerBus Architecture specification defines anonchip communications standard fordesigning high-performance embeddedmicrocontrollers.Three distinct buses are defined withinthe AMBA specification:• the Advanced High-performance Bus (AHB)• the Advanced System Bus (ASB)• the Advanced Peripheral Bus (APB) 4/3/2013 7
  8. 8. AMBA AHB AMBA ASB AMBA APB * High performance * High Performance * Low power * Pipelined operation * Pipelined operation * Latched address and control * Multiple bus masters * Multiple bus masters * Simple interface * Burst transfers * Suitable for many peripherals * Split transactions4/3/2013 8
  9. 9. AMBA AHB system design• A bus master is • A bus slave able to responds to initiate a read or read and write write operation operations within a by given providing AHB AHB address- an address space range and control master slave informatio n AHB AHB arbiter decoder• The bus • -The AHB arbiter decoder is used ensures that to decode only one bus address of master at a each transfer time is and provide a allowed to select signal for the slave initiate data transfers. 4/3/2013 9
  10. 10. Timing Diagram of AMBA AHBBasic transfer Transfer type4/3/2013 10
  11. 11. Block Diagram of AMBA APBAPB bridge APB slave4/3/2013 11
  12. 12. Timing Diagram of AMBA APBWrite transfer Read transfer4/3/2013 12
  13. 13. Interfacing APB to AHBRead transfers Write transfers4/3/2013 13
  14. 14. Direct Memory Access controller (DMAC) is an important component of SoC architecture and Direct Memory Access (DMA) is an important technique to increase data transfer rate and MPU (microprocessor unit) efficiency in SoC system. There are a few of on-chip bus standards, but AMBA Rev 2.0[4] (Advance Microcontroller Bus Architecture) has become popular industry-standard on-chip bus architecture. The design of DMAC is compliance to the AMBA specification for easy integration into SoC.4/3/2013 14
  15. 15. The connectivity of proposed DMAC architecture -Uses external memory & memory interface can be used -APB bridge & System Arbiter will use APB - DMAC contains AHB slave APB master & APB master4/3/2013 15
  16. 16. A. Functional Overview B. Dual-Clock Domain Design C. Multi-channel Design and Arbitration Mechanism D. Parameter Sets E. AHB and APB Operation and Parallelism F. Asymmetric Asynchronous FIFO Design G. Interrupt and Error System Design4/3/2013 16
  17. 17. A. Functional Overview ARB Master APB Master MPU module module programs asserts bus asserts bus the request request parameter signal to get signal to set access to gain the the ARB control of APB after arbitration with APB Parameter Request and Bridge sets module Respond transfer module parameters accepts the to AHB request of Interrupt Master data and error module and transfer module APB Master asserts interrupt signal or Selected error signal request When data Requests finds its transfer enter correspondi completes arbiter ng or error module. parameter occurs set in parameter sets module4/3/2013 17
  18. 18. B. Dual-Clock Domain Design Advantage of using reduced APB clockfrequency - Decrease power consumption - Reduce area design Use of Pulse synchronous circuit - To decrease metastability to an acceptable level Working of Pulse synchronous circuit - To synchronized Pulse control signal transmission between AHB Master and APB Master, or between interrupt and Error module and APB Master module 4/3/2013 18
  19. 19. C. Multi-channel Design and Arbitration Mechanism Multi-channel Design Arbitration Mechanism ensures the allow chaining of only one channel has several transfers access to the bus by through one transfer observing which occurrence. channel has the greatest weight. The channel chaining capability for the The greatest weighted DMAC allows the channel will get completion of a access to the bus,In DMAC channel hardware channel transfer to trigger priority another DMAC channel transfer.4/3/2013 19
  20. 20. D. Parameter Sets Each parameter set is organized into eight words (32bit), and for contiguous data transfer, configure four words, the remaining words use default values Each parameter set includes source address,destination address, offset address index (SRCARY,DSTARY, SRCFRM, DSTFRM), data width, burst size(ACNT, BCNT, CCNT control information, such as address mode, transfer type, data flow control, link address, chaining transfer control, interrupt and error masking.4/3/2013 20
  21. 21. E. AHB and APB Operation and Parallelism AHB slave-to- AHB AHB Master APB Master slave module module APB AHB periphera Four slave-to- Between ARB Between ARB l-to-APB Transfer APB slave and APB slave and APB periphera type periphera peripheral peripheral l l Between Between FIFO APB and ARB slave. FIFO and APB periphera peripheral l-to-AHB salve4/3/2013 21
  22. 22. Data transfer in all four modesData transfer in AHB slave-to-AHB slave Data transfer in ARB slave-to-APB& APB peripheral-to-APB peripheral peripheral APB peripheral-to-ARB slave  DMAC reads data from AHB  If the APB peripheral is slow slave for one burst, writing into equipment, user adopt FIFO FIFO, and asserts request bus buffer by set transfer mode signal for write operation to register in parameter set, and meet the requirements of real- the process is like AHB time. slave-to-AHB slave.  When one burst data is read  ARB read operation is in parallel completely and DMAC occupies with APB write bus again, DMAC writes data to operation, forming a two-stage ARB slave. pipeline, thus transfer speed is  Transfer operations carry out in increased greatly order, until task terminates.4/3/2013 22
  23. 23. F. Asymmetric Asynchronous FIFO Design • To reading & writing data width of different WHY USED size • for AHB slave to-APB peripheral WHERE USED • for APB peripheral- to AHB slave. • data buffer in one clock domain. HOW IT • In write port, can write and read data WORKS • In read port, we only read data.4/3/2013 23
  24. 24. Block Description DualRAM • It is a 128*32bit asynchronous dual-port module SRAM • Write alignment saves data when, write data width < read data width fifo_align module • Read alignment saves data when, write data width > read data width • controls reading or writing fifo_control dual-ram module • Generates write full signal and read empty signal4/3/2013 24
  25. 25. G. Interrupt and Error System Design ERROR IN ERROR IN LINKFOR INTERRUPT DESIGN PARAMETER SETDMAC will generate interrupt SET signal to MPU The data transfer Data transfer request is corresponding to abandoned. link parameter set isData transfer terminates and abandoned. describe which channel request is complete. DMAC will generate error signal to MPU and describe which DMAC will generate channel is error and error signal to MPU finish the next and describe whichFinish the next channel data channel data link parameter set is transfer error. transfer immediately. immediately.4/3/2013 25
  26. 26. The DMA is designed in Verilog language and successfully synthesized into the gate-level circuit. The delay of critical path is 2.45ns, that is, the maximum frequency is 408 MRZ.4/3/2013 26
  27. 27. Performance Comparision No. of Cycles inthis DMA taken in AN2548 PL081 DMA PDMA PDMAbuffer mode are DMA (buffer) (non-buffer)just half toAN2548 butgreater than thanPL081 AHB to AHB 1920 989 989 - For non –buffer mode this AHB to APB 3072 1320 1564 1012DMA uses onethird of tatal APB to AHB 3072 1320 1564 1012cycles of AN2548& also less than APB to APB 3840 1728 1883 -PL081. 4/3/2013 27
  28. 28. • AN2548 • PL081 DMA • PROPOSED DMA DMA - No busrt mode - No busrt -Busrt mode mode -No parallel - Parallel operation -No parallel operation operation -Function of -Function of APB bridge -Function of APB bridge APB bridge -No non-buffer -No non-buffer mode -No non-buffer mode mode - Less high - High transfer transfer rates - High transfer rates rates4/3/2013 28
  29. 29. DMA controls directly data,address and control signals on APB It achieves AHB operation and APB operation run in parallel. Data transfer mode can be buffer and non-buffer mode according to practical application by setting control register.4/3/2013 29
  30. 30. Metastability could never been avoided in anytime when transmitting signals between asynchronous clock domains.4/3/2013 30
  31. 31. Number of hardware & software channels can also Software channels can also be implemented. be increased upto two decimals. Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC Can also work upon other than 0.18 µm library Other addressing modes are also possible technology of SMIC.4/3/2013 31
  32. 32. In the design and implementation of an AMBA based advanced DMA controller .The DMAC has 6 channels which support hardware triggers, linking operation and channel chaining transfer to improve the real-time processing capability and provides three dimensions transmission so as to perform data block moving, data sorting and subframe extraction of various data structures. Channel arbitration mechanism adopts hardware priority so that meet the different requirements of fairness and the priority in different systems and the DMAC supports incrementing and wrapping address modes and completes data transfer which the data width of read and write is different by asymmetric asynchronous FIFO. Moreover the DMAC adopts dual-clock domain design so as to decrease the power consumption.Furthermore the DMAC has the function of APB Bridge, and it can control address, data and control signals independently and achieve ARB bus and APB bus to run in parallel. And the DMAC could adopt buffer and non-buffer data transfer mode according to the speed of equipments. Non-buffer mode can enhance the data transfer rate significantly.4/3/2013 32
  33. 33. The performance of our DMAC is better. Each data transfer rate is increased by about 50%. Between ARB slave and APB peripheral, this DMA adopts non-buffer mode to transfer data, and the rate is increased by 67%.If this DMA uses buffer mode, the performance of PL081 is better than this. But the time spent more than PL081 is used in signals synchronization. This DMA adopts dual-clock domain design, and PL081 only has one clock RCLK. When this DMAC uses non-buffer, even though signal synchronization will occupy much time, the performance of this DMA is better than PL081, and the data transfer rate is increased by 23.3%.And this DMA has more features than PL081.4/3/2013 33
  34. 34. Transfer from AHB slave_to AHB master4/3/2013 34
  35. 35. Transfer from APB Master4/3/2013 35
  36. 36. Transfer from APB to AHB4/3/2013 36
  37. 37. Transfer from AHB to APB4/3/2013 37
  38. 38. Experimental results show that the DMAC has the advantage of high speed transfer rate and is much suitable to various application fields, such as multimedia processing.4/3/2013 38
  39. 39. [1] Guoliang Ma; Hu He ,Design And Implementation Of An Advanced Dma controller On Amba-Based SoC, ASIC, 2009. ASICON 09. IEEE 8th International Conference on Digital Object, Page(s): 419 – 422 [2] Hessel, S.; Szczesny, D.; Bruns, F.; Bilgic, A.; Hausner, J.Vehicular, Architectural Analysis of a Smart DMA Controller for Protocol Stack Acceleration in LTE Terminals,Technology Conference Fall (VTC 2010-Fall), 2010 IEEE 72nd Digital Object, Page(s): 1 – 5. [3] Jaehoon Song; Piljae Min; Hyunbean Yi; Design of Test Access Mechanism for AMBA- Based System-on-a-Chip,Sungju ParkVLSI Test Symposium, 2007. 25th IEEE , Page(s): 375 – 380 [4] Hang Yuan; Hongyi Chen; An improved DMA controller for high speed data transfer in MPU based SOC, Guoqiang Bai Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on Digital Object, Page(s): 1372 - 1375 vol.2.4/3/2013 39
  40. 40. [5] Lufeng Qiao; Design of DMA controller for multichannel PCI bus frame engine and data link manager,Zhigong Wang Communications, Circuits and Systems and West SinoExpositions, IEEE 2002 International Conference on Digital Object,Page(s): 1481 - 1485 vol.2. [6] Szczesny, D.; Hessel, S.; Traboulsi, S.; Optimizing the Processing Performance of a Smart DMA Controller for LTE Terminals,Bilgic, A. Embedded and Real-Time Computing Systems and Applications (RTCSA), 2010 IEEE 16th International Conference on Digital Object,Page(s):309-315 [7] Chia-Hao Yu; Chung-Kai Liu; Chih-Heng Kang; Tsun-Hsien Wang; Chih-Chien Shen; An Efficient DMA Controller for Multimedia Application in MPU Based SOC, Shau-Yin Tseng,Multimedia and Expo, 2007 IEEE International Conference on, Page(s): 80 – 83 [8] Prokin; DMA transfer method for wide-range speed and frequency measurement, M.Instrumentation and Measurement, IEEE Transactions on Volume: 42 , Issue: 4 , Page(s): 842 – 846 .4/3/2013 40
  41. 41. [9] Osborne, S.; Erdogan, A.T.; Arslan, T.; Bus encoding architecture for low-power implementation ofan AMBA-based SoC platform, Robinson, D.Computers and Digital Techniques, IEEE Proceedings - Volume: 149 , Issue: 4 , Page(s): 152 – 156[10] Pockrandt, M.; Herber, P.; Model checking a SystemC/TLM design of the AMBAAHB protocol, Glesner, S. Embedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEESymposium on, Page(s): 66 – 75[11] Osborne, S.; Erdogan, A.T.; Arslan, T.; Bus encoding architecture for low-power implementation ofan AMBA-based SoC platform,Robinson, D.Computers and Digital Techniques, IEEE Proceedings -Volume: 149 , Issue: 4 , Page(s): 152 - 156[12] Yi-Ting Lin; Chien-Chou Wang; AMBA AHB bus potocol checker with efficient debuggingmechanismIng-Jer Huang Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposiumon , Page(s): 928 – 93 4/3/2013 41
  42. 42. [13] Dubois, M.; Savaria, Y.; A generic AHB bus for implementing high-speed locally synchronousislands,Bois, G.SoutheastCon, 2005. Proceedings. IEEE , Page(s): 11 – 16[14] Toal, C.; Sezer, S.; A pipelined SoPC architecture for 2.5 Gbps network processing,Xing YuField-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEESymposium on , Page(s): 271 – 272[15] Sezer, S.; Toal, C.; A pipelined SoPC architecture for data link layer protocol processing,Xing YuSOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] , Page(s): 277 – 278[16] Toal, C.; A 32-bit SoPC implementation of a P5,Sezer, S.Computers and Communication, 2003.(ISCC 2003). Proceedings. Eighth IEEE International Symposium on , Page(s): 504 - 507 vol.1[17] AN2548 Application note.[18] AMBA Specification (rev2.1)[19] TMS320DM643x DMP EDMA3 Users Guide. SPRU987, January 2007.4/3/2013 42
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