Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our User Agreement and Privacy Policy.

Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our Privacy Policy and User Agreement for details.

Like this presentation? Why not share!

1,919 views

Published on

No Downloads

Total views

1,919

On SlideShare

0

From Embeds

0

Number of Embeds

17

Shares

0

Downloads

62

Comments

0

Likes

1

No embeds

No notes for slide

- 1. CSL718 : Pipelined Processors Pipeline Hazards Handling Structural Hazards 19th Jan, 2009 Anshul Kumar, CSE IITD
- 2. Types of Pipelines • Degree of overlap – Serial, Overlapped, Pipelined, Super-pipelined • Depth – Shallow, Deep • Structure – Linear, Non - linear • Scheduling of operations – Static, Dynamic slide 2 Anshul Kumar, CSE IITD
- 3. Degree of overlap Depth Serial Shallow Overlapped Deep Pipelined slide 3 Anshul Kumar, CSE IITD
- 4. Pipeline Structure Linear A B C Pipeline Non-linear A B C Pipeline Sequence: A, B, C, B, C, A, C, A slide 4 Anshul Kumar, CSE IITD
- 5. Scheduling/timing alternatives • Decisions : Static / Dynamic – order in which instructions enter the pipeline – sequence of stages through which different instructions pass – detection of hazards and introduction of stall cycles • Static – if one instruction stalls, all subsequent instructions are delayed • Dynamic – higher throughput is achieved slide 5 Anshul Kumar, CSE IITD
- 6. Dynamic Scheduling • type 1 : beginnings (decode) and endings (put away) in order • type 2 : only beginnings in order • type 3 : no order restrictions except dependencies • type 1 extended : beginnings in order, references that effect memory state are in order [note that a memory reference may lead to page fault] slide 6 Anshul Kumar, CSE IITD
- 7. Pipelining and CPI Type CPI Serial 5–6 Overlapped 3 Pipelined (static) 1.5 – 2 Pipelined (dynamic) 1.2 – 1.5 Multiple instruction issue < 1.0 slide 7 Anshul Kumar, CSE IITD
- 8. Hazards in Pipelining • Data dependencies => Data hazards – RAW (read after write) – WAR (write after read) – WAW (write after write) • Resource conflicts => Structural hazards – use of same resource in different stages • Procedural dependencies => Control hazards – conditional and unconditional branches, calls/returns slide 8 Anshul Kumar, CSE IITD
- 9. Handling hazards • Data hazards – detect instructions with data dependence – introduce nop instructions (bubbles) in the pipeline – more complex: data forwarding • Control hazards – detect branch instructions – flush inline instructions if branching occurs – more complex: branch prediction slide 9 Anshul Kumar, CSE IITD
- 10. Data Hazards read/write previous instr read/write current instr delay = 3 slide 10 Anshul Kumar, CSE IITD
- 11. Handling Data Hazards EX W previous instr Data Forwarding 1 R EX current instr W previous Instruction instr Reordering 2 R current instr slide 11 Anshul Kumar, CSE IITD
- 12. Are there software solutions? • Separate dependent instructions by reordering code • Insert nop instructions in worst case • Treat branches as delayed branches and insert suitable instructions in delay slots slide 12 Anshul Kumar, CSE IITD
- 13. Control Hazards cond eval target addr gen branch instr next inline instr delay = 2 target instr delay = 5 • the order of cond eval and target addr gen may be different • cond eval may be done in previous instruction slide 13 Anshul Kumar, CSE IITD
- 14. Structural Hazards Caused by Resource Conflicts • Use of a hardware resource in ABAC more than one cycle ABAC ABAC • Different sequences of ABCD resource usage by different ACBD instructions FDXX • Non-pipelined multi-cycle resources FDXX slide 14 Anshul Kumar, CSE IITD
- 15. Structural hazards • Structural hazards can possibly be removed by design – separate instruction and data memories – adders for PC increment and offset addition to PC separate from main ALU – each instruction uses ALU at most in one cycle – one instruction can read from RF while other can write into it in the same cycle slide 15 Anshul Kumar, CSE IITD
- 16. Analysis of Structural Hazards Non-linear A B C Pipeline 1 2 3 4 5 6 7 8 Reservation Table A X X X for X B X X C X X X slide 16 Anshul Kumar, CSE IITD
- 17. Analysis of Structural Hazards Multi-functional A B C Pipeline 12 3 4 5 6 7 8 Reservation Table A Y X X X Y for X YX B X for Y C YX YXYX slide 17 Anshul Kumar, CSE IITD
- 18. Collisions with Initiation Interval =2 1 2 3 4 5 6 7 8 9 10 11 A1 2 3 1 4 1,2 5 2,3 6 1 1,2 2,3 3,4 4,5 B 1 1,2 1-3 2-4 C slide 18 Anshul Kumar, CSE IITD
- 19. Collisions with Initiation Interval =5 1 2 3 4 5 6 7 8 9 10 11 A1 1,2 1 2,3 1 1 2 2 B 1 1 1 2 2 C slide 19 Anshul Kumar, CSE IITD
- 20. Latency Sequences and Cycles 1, 8, 1, 8, …. (1, 8) avg = 4.5 3, 3, 3, 3, …. (3) avg = 3 6, 6, 6, 6, …. (6) avg = 6 Minimum Average Latency (MAL) ? slide 20 Anshul Kumar, CSE IITD
- 21. Collision Free Scheduling Starting with the current state, in which cycles the next instance of X can be scheduled ? m …. 21 Cycle no. (future) 1011010 Collision vector for X 1 : collision 0 : no collision slide 21 Anshul Kumar, CSE IITD
- 22. Computing collision vector 7 6 5 4 3 2 1 1 0 1 1 0 1 0 0 1 2 3 4 5 6 7 8 9 10 11 A1 1 1 2 2 2 B 1 1 2 2 C 1 1 1 2 2 2 slide 22 Anshul Kumar, CSE IITD
- 23. State Transitions 1011010 1011010 clock cycle 0101101 clock cycle In short: 0010110 3 clock cycle 0001011 schedule X 1011011 1011011 slide 23 Anshul Kumar, CSE IITD
- 24. Collision Free Scheduling for X m …. 21 Collision vector for X 1011010 1 : collision 0 : no collision 8+ 1011010 8+ 3 1 6 8+ 1011011 1111111 6 3 slide 24 Anshul Kumar, CSE IITD
- 25. Collision Free Scheduling for Y m….2 1 Collision vector for Y 1010 1 : collision 0 : no collision 5+ 1010 5+ 1 3 5+ 1011 1111 3 slide 25 Anshul Kumar, CSE IITD
- 26. Latency Cycles from State Diagram Latency Cycles (1, 8) (1, 8, 6, 8) (3) (6) (3, 8) (3, 6, 3) Simple Latency Cycles (no figure repeats) (1, 8) (3) (6) (3, 8) (6, 8) Greedy Latency Cycles (1, 8) (3) - from different starting states slide 26 Anshul Kumar, CSE IITD
- 27. Minimum Average Latency (MAL) MAL > max no. of check marks in any row MAL < avg latency of any greedy cycle avg latency of any greedy cycle < no. of 1’s in initial collision vector + 1 slide 27 Anshul Kumar, CSE IITD
- 28. Upper Bound on MAL • Consider a greedy cycle (k1,k2,..,kn) • Let p = no. of 1’s in initial collision vector ⇒ k1 < p + 1 k2 < 2 p - k1 + 2 {k1-1 1’s removed, p 1’s added} k3 < 3 p - k1 - k2 + 3 …. kn < n p - k1 - k2 … - kn-1 + n ⇒ k1 + k2 … + kn < n p + n ⇒ MAL < p + 1 slide 28 Anshul Kumar, CSE IITD
- 29. Reference (Structural Hazards) 1. K. Hwang, quot;Advanced Computer Architecture : Parallelism, Scalability, Programmabilityquot;, McGraw Hill, 1993. slide 29 Anshul Kumar, CSE IITD

No public clipboards found for this slide

×
### Save the most important slides with Clipping

Clipping is a handy way to collect and organize the most important slides from a presentation. You can keep your great finds in clipboards organized around topics.

Be the first to comment