Lec Feb05 2009

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Lec Feb05 2009

  1. 1. CSL718 : Superscalar Processors Renaming and Reordering 5th Feb, 2009 Anshul Kumar, CSE IITD
  2. 2. Why Renaming and Reordering? • Register Renaming – Removes false dependencies (WAR and WAW) • Reordering Buffer (ROB) – Ensures sequential consistency of interrupts (precise vs imprecise interrupts) – Facilitates speculative execution slide 2 Anshul Kumar, CSE IITD
  3. 3. RAW, WAR and WAW (in Static Pipeline) (in Static Pipeline) IF D RF EX WB RAW IF D RF EX WB IF D RF EX WB WAR IF D RF EX WB IF D RF EX EX EX WB WAW IF D RF EX WB slide 3 Anshul Kumar, CSE IITD
  4. 4. RAW, WAR and WAW (in Superscalar) (in Superscalar) b←1 write IF IS DP EX WB RAW b←0 read IF IS DP EX WB WAW WAR write IF IS DP EX WB b←1 scoreboard bit set by write, cleared by read what happens when there are multiple reads for a write? slide 4 Anshul Kumar, CSE IITD
  5. 5. Implementation using scoreboard bit Implementation using scoreboard bit in order issue, scoreboard bit set by write, cleared at issue time b←0 b←1 write IF IS DP EX WB RAW read IF IS DP EX WB WAR read IF IS DP EX WB WAR WAW write IF IS DP EX WB b←0 issue only if there are no pending reads slide 5 Anshul Kumar, CSE IITD
  6. 6. CDC 6600 like Implementation CDC 6600 like b←φ b ← FU1 write IF IS DP EX WB RAW read IF IS DP EX WB WAW WAR write IF IS DP EX WB b ← FU2 slide 6 Anshul Kumar, CSE IITD
  7. 7. IBM 360 like Implementation IBM 360 like Implementation b ← FU1 b←φ write IF IS DP EX WB RAW read IF IS DP EX WB WAW WAR write IF IS DP EX WB b ← FU2 slide 7 Anshul Kumar, CSE IITD
  8. 8. Use of Renaming Use of Renaming write IF IS DP EX WB RAW read IF IS DP EX WB WAW WAR write IF IS DP EX WB slide 8 Anshul Kumar, CSE IITD
  9. 9. Register renaming write R5 write R5 RAW RAW read R5 read R5 WAR write R8 write R5 RAW RAW read R8 read R5 slide 9 Anshul Kumar, CSE IITD
  10. 10. Who does renaming? • Compiler – Done statically – Limited by registers visible to compiler • Hardware – Done dynamically – Limited by registers available to hardware slide 10 Anshul Kumar, CSE IITD
  11. 11. Types of renaming buffers • Separate renaming register file and architectural register file • Combined renaming and architectural register file • Renaming combined with reordering • Renaming combined with reservation stations and reordering slide 11 Anshul Kumar, CSE IITD
  12. 12. How renaming works? (in context of combined reg file) (in context of combined reg file) register address from instruction mapping physical register file (larger than architectural register file) slide 12 Anshul Kumar, CSE IITD
  13. 13. Types of mapping Indexed Associative • Inexpensive • Expensive • Two steps required • Single step associative access – Look up index – Read value slide 13 Anshul Kumar, CSE IITD
  14. 14. Renaming with indexed access entry index value value valid valid register number mapping table physical register file slide 14 Anshul Kumar, CSE IITD
  15. 15. Renaming with associative access match register number entry reg value value latest valid num valid physical register file (associative) slide 15 Anshul Kumar, CSE IITD
  16. 16. Handling interrupts these can “commit” status of instruction execution at the time of interrupt completed under execution not started program order slide 16 Anshul Kumar, CSE IITD
  17. 17. Speculative execution predicted branch speculative don’t commit till correctness of prediction is determined execution slide 17 Anshul Kumar, CSE IITD
  18. 18. Reordering instruction enter i i x x i: issued x: in execution f: finished x f x f instructions commit/retire slide 18 Anshul Kumar, CSE IITD
  19. 19. Using ROB with RF Register to reservation from FUs File stations/FUs Register from FUs ROB File to reservation stations/FUs slide 19 Anshul Kumar, CSE IITD
  20. 20. Future file and history file Register use in case of ROB File interrupts from FUs to reservation Future stations/FUs File update in case displaced of interrupts values History File Future to reservation from FUs File stations/FUs slide 20 Anshul Kumar, CSE IITD
  21. 21. Combining renaming and reordering Combining renaming and reordering • Use physical register file as ROB as well • Maintain status about committed and uncommitted values slide 21 Anshul Kumar, CSE IITD
  22. 22. How much to speculate? • Handle exceptions in speculated instructions? – handle only low cost exception events such as first level cache miss – wait if expensive exceptional event occurs such as second level cache miss or TLB miss • Speculating through multiple branches – needed when branches are frequent or clustered – even handling multiple branches in a cycle may be required slide 22 Anshul Kumar, CSE IITD

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