UART Implementation on FPGA using VHDL .
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UART Implementation on FPGA using VHDL .

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UART is a serial communication interface. In this project a serial communication is established between the transmitter and receiver. Data is transferred to the receiver serially with the help of rs-232. J-TAG wire is connected to the CPU and the FPGA kit to transmit control signal (instruction) to the FPGA. Whereas the data is transmitted by the RS-232.We programmed the transmitter, receiver, baud generator and interface the LCD in the XILINX ISE 9.2i . The transmitted data will be shown on the LCD. Also, the led will glow according to the ASCII value of the transmitted data.
The transmitter serialize the parallel data and add stop bit, start bit & parity bit to the data and the data is transmitted to the receiver. The receiver receives the data serially and then convert the received data into parallel. The Data is transmitted through flash magic Software, which is received and then displayed on the LCD of FPGA kit. Hence, the serial data is transmitted and received . Serial Communication Interface is Implemented on FPGA using VHDL.

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UART Implementation on FPGA using VHDL . UART Implementation on FPGA using VHDL . Presentation Transcript

  • A MAJOR PROJECT ON “UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER IMPLEMENTATION ON FPGA USING VHDL” GUIDED BY SUBITTED BY PROF. JAYA KOSHTA RANVEER KUMAR
  • CONTENTS  Introduction  Basics of Serial Communication -RS-232  Basic block diagram of UART  Transmitter block of UART  Receiver block of UART  Programming of UART using VHDL  UART implementation on FPGA  Transmission of data  Simulation  Applications  Advantages and Disadvantages  Reference
  • Introduction  It also called Serial Communication Interface(SCI)  full-duplex communication.  Asynchronous communication.  Compatible with PC .  The Standard baud rates are: 100, 200, 300, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 1 15200 bps.
  • BASIC OF SERIAL COMMUNCATION Frame  Frame : A frame is the unit of transmission in serial communications. A frame contains:  Start bit: To declare the start of transmission.  Data bits: 4,5,6,7, or 8 bits of useful data bits.  Parity bit : To check for transmission errors.  Stop bit: To declare end of frame.
  • Basics of serial communication Bit rate:  Number of bits sent every second (BPS) Baud rate:  Number of symbols sent every second, where every symbol can represent more than one bit. MODES  SIMPLEX MODE  HALF-DUPLEX MODE  FULL DUPLEX MODE
  • Basics of serial communication  Before transmission begins, transmitter and receiver must agree on :-  Baud rate (75, 150, 300, 600, etc)  1, 1.5 or 2 stop bits  5, 6, 7 or 8 data bits  even, odd or no parity  SERIAL COMMUNICATION PARALLEL COMMUNICATION
  • BLOCK DIAGRAM OF UART
  • RS -232 CABLE & PINS
  • Function of various pins on serial port Pin no. Pin Symbol Function 1 CD Carrier Detect: It is used by Modem to inform PC that it has detected Carrier on Phone Line. 2 RD Serial data is received on this line by PC. 3 TD Serial Data is transmitted on this pin by PC. 4 DTR Data Terminal Ready When terminal (computer) powers up it asserts DTR high. 5 SG It is signal ground with reference to which voltages are interpreted as high or low. 6 DSR Data Set Ready. When modem powers up it asserts DSR high. 7 RTS Request to Send. Request to send is sent from (DTE) terminal (PC) to modem (DCE) to inform it that PC wants to send some data to modem. 8 CTS Clear To Send. Upon received RTS from DTE (PC), the modem (DCE) asserts CTS high whenever it is ready to receive data. 9 RI Ring Indicator. It is set by modem to indicate the PC that a ringing signal has been detected on line.
  • BLOCK DIAGRAM OF FPGA KIT
  • FPGA – RS232 INTERFACE
  • UART TRANSMITTER UART0_DR_RWrite data 1 0 Stop Start Shift clock Data 7 6 5 4 3 2 1 0 U0Tx Transmit data register 16-element FIFO TXEF Fifo empty flag TXFF Fifo full flag Transmit shift register
  • UART TRANSMITTER  Tx Operation  Data written to UART0_DR_R  passes through 16-element FIFO  permits small amount of data rate matching between processor and UART  Shift clock is generated from 16x clock  permits differences in Tx and Rx clocks to be reconciled
  • UART RECEIVER UART0_DR_RRead data 1 0 Stop Start Shift clock Data 7 6 5 4 3 2 1 0 U0Rx Receive data register 12-bit, 16-element FIFO RXFE Fifo empty flag OE BE PE FE RXFF Fifo full flag Receive shift register
  • UART RECEIVER  Rx Operation  RXFE is 0 when data are available  RXFF is 1 when FIFO is full  FIFO entries have four control bits  BE set when Tx signal held low for more than one frame (break)  OE set when FIFO is full and new frame has arrived  PE set if frame parity error  FE set if stop bit timing error
  • TRANSMISSION OF DATA
  • SIMULATION
  • Applications  Communication between distant computers.  Serializes data to be sent to modem , serial cable.  De-serializes data received data from modem.  The UART is also responsible for baud rate generation.  This determines the speed at which data is transmitted and received. One baud is one symbol per second .  With modern UARTs, 230,400 baud can be achieved with a short cable length of a few feet.
  • ADVANTAGES  Cheaper than parallel communication as less wire is needed .  cable loss is not going to be as much of a problem for serial cables than they are for parallel.  Serial Communication reduces the pin count as Only two pins are commonly used, Transmit Data (TXD) and Receive Data (RXD) compared with at least 8 pins if you use a 8 bit Parallel method
  • DISADVANTAGES  Becoming much less common.  Largely been replaced by faster, more sophisticated interfaces like PCs: USB (peripherals), Ethernet (networking).  Still used today when simple low speed communication is needed.
  • REFERENCES  VHDL Programming By Example doughlas perry.  Circuit Design and Simulation with VHDL 2nd ed. - V. Pedroni ( MIT 2010)  VHDL-primer-by-j-bhasker