• Share
  • Email
  • Embed
  • Like
  • Save
  • Private Content
Dcis97
 

Dcis97

on

  • 568 views

 

Statistics

Views

Total Views
568
Views on SlideShare
568
Embed Views
0

Actions

Likes
0
Downloads
0
Comments
0

0 Embeds 0

No embeds

Accessibility

Categories

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Dcis97 Dcis97 Presentation Transcript

    • A Set of Tools to Help in the VHDL Design Flow of Complex Systems Y. Torroja, C. Lopez, T. Riesgo, J. Uceda E.T.S.I. Industriales - Universidad Politécnica de Madrid División de Ingeniería Electrónica c/ José Gutiérrez Abascal 2, 28006 Madrid e-mail: yago@upmdie.upm.es Abstract: • The ability of the vendors and users’ community to In this paper, a set of tools developed to help in the handle an increasing amount of Supercells VHDL design flow of complex systems on silicon is competing for the market. This translates into a presented. These tools cover different stages of the Management Environment able to deal with design process, from specification to logic design. multiple, continuously improving, and concurrent Some of the tools are oriented towards design versions. management and aim to improve the quality of the • The ability of the vendors and users community to design process. Other tools are oriented to measure analyse the quality of the products (Supercells) the quality of the design itself. These tools together with respect to different aspects. will help to improve the global quality of a design • The ability of the vendors and user community to and to reduce the development time. deal with ever more complex designs (Supercells In the paper, a practical view on how these tools or Supercells-based Systems) providing at the and methods will help designers or project same time high quality products and low time to managers to improve the quality of their designs is market. This means the need of good estimators given. The goal of each tool and its use in the design and methods to help the designer to choose the best flow are presented, and the main benefits problem solution in a fast and reliable way. highlighted. Besides, a more detailed description of the tools developed by the authors is given. All these 1.2 Design Process of Supercells or Supercell Based tools are being developed within the TOMI1 project. Systems The manufacturing of an ASIC is a non-return process 1. Introduction. The VHDL based design with high associated costs, not only regarding the cost process of complex systems of the prototypes or pieces but also due to the overall 1.1 Development and use of VHDL Supercells impact of the ASIC in the system in which it is The development of Supercells (macrocells included. So, it is not only necessary to have circuits containing from 20k to 100k gates) or Supercells thoroughly proved and verified but also to apply based systems is a highly complex task. The use of quality processes and reviews in the different design VHDL will help the designer offering, on one hand, stages. the ability to use a common framework along all The process of designing an design stages, from specifications to logic design. On Requirements integrated circuit, traditionally, the other hand, it provides a standard framework for has been divided into several the interchange of information and library Specifications stages. The step, from one stage components between designers, or design centres to the next, is allowed when the and customers. Architectural design passes a formal review, in Nowadays, the use of VHDL is re-launching the Design which accordance to the reusability concept [1-3]. Design centres may offer specification and quality criteria Logic models of their systems that a final user can simulate Design are proved. or even synthesise together with his/her own new These stages (see Figure 1) are development. This situation is shortening the Physical Design related to the level of abstraction development time so doing the market more used to describe the design. competitive and doing the open market idea almost a Manu- Traditionally these levels of reality. facturing abstraction are algorithmic, But the success of this approach depends on the behavioural, register transfer Figure 1: Design ability of the designers, vendors and user community level, structural, physical, etc., Stages to satisfy three major, interdependent pillars: and the stages are: • Establishment of requirements and feasibility 1 This work is partially funded by EC (ESPRIT #20724). studies. This stage covers the identification of the Partners: ES2, LEDA, TI+D, TGI and UPM operability required of the ASIC to be developed.
    • The study's conclusion will be drawn up in the 2. Contribution of TOMI tools to the VHDL Requirements Documents. based design process • ASIC Specifications. Detailed functionality of the ASIC is set and external interfaces defined. 2.1 VHDL Design Manager and VHDL Design Besides, development and validation plans are Studio elaborated. The ASIC is divided into functional In typical large designs based on VHDL, the number blocks and specification for each one is made. A of VHDL models that are written or simply (re)used preliminary model of the ASIC and the can be significantly large, ranging from dozens for environment may be developed. Library small chips to hundreds for large ASICs. If we take components may be selected upon a Supercell into account the different versions of a single VHDL catalog. model that are written and used within a single design • Architectural design. The main objective of this process, this number can be multiplied by a factor of stage is to obtain a Register Transfer Level 10 to 100. Among these models, some are especially description of the ASIC. In this level of developed for the design, some have been written description, designers define in detail the control within the company for another design, some are and the data flow of the circuit and all the general purpose models, some have been bought to functions performed by the ASIC. It is critical to model vendors, etc. validate thoroughly each part described, so some When the designer is faced to such a number and iteration will be performed until final model is variety of VHDL models, it becomes very difficult obtained. -sometimes impossible- to manually manage the use of • Logic design. During this stage a synthesisable these VHDL models. Figure 2 shows a typical description of the circuit is obtained and example of this situation. A particular module of the synthesized with a manufacturer library. So, design may suffer a lot of transformations during its almost real characteristics (such a loads, timings, development. First, as the module passes from etc) may be obtained and applied to the circuit specification to logic design its VHDL description will (although they are still estimations). Final be refined. Each refinement may produce several validation will prove that the circuit works versions until the result is appropriate. The module, in properly. During this stage test patterns should be its turn, may include library components or other generated also, and test circuitry inserted if modules that may be evolving, so it is necessary to needed. control which version is being used at any particular • Physical design and manufacturing. The layout moment. Besides this, several versions with different of the circuit is obtained and final simulations objectives may be produced, and its life and status with real characteristics are performed. The should be traced. circuit may be sent to the foundry for manufacturing. Requirements • Prototype validation. The final user will validate Library Library Module Module the prototypes of the circuit in the final system. Module B Syn B Sim • Production. Specifications A 1.0 VHDL Design Management & VHDL Design Studio Each stage may require several iterations to complete Module Module Architectural Module A Module 2.1 Module Module and, in some cases, it is possible that an iteration Design AAA A 5.1 A involve several stages. Although this scheme is very rigid in some occasions, and is usually modified to Logic Module Module Module A 3.1 Module Module Module Module Module A 6.1 Design A A 4.1 A A A A allow some stage overlapping, it can show very well where and how the tools developed in TOMI can be Physical ASIC FPGA Simulation used along the design process. Design version prototype model In the following section a brief description of the Figure 2: Use of the VHDL Design Manager & design process of complex Supercells or designs VHDL Design Studio containing Supercells, based on the use of VHDL and automatic synthesis tools is presented. The If we put all these versions together, and taking into description of the design stages and objectives will account the continuos tasks of editing, compiling and show, in a practical way, where and when the tools simulating, we can have a global idea of the designer developed in TOMI are used and what they offer to difficulties to manage this situation. In fact, it is not the VHDL based design process. A more extended unusual that a design fails due to errors in the design description of the tools developed by the authors library management. (VHDL Quality ToolKit and VHDL Validation The whole purpose of the VHDL Design Manager, Tool) will be provided. In the last section, the global and its graphical user-interface VHDL Design Studio, state of the work and future plans will be exposed. is to provide the designer with friendly tools that help him to efficiently and intuitively manage large libraries
    • of VHDL models. These tools include version 2.2.1 Design and Modelling Quality Checkers control managers, source file (before compilation) Quality review aims to detect design methods or and library unit (after compilation) managers, VHDL constructs that are likely to produce problems graphical browsers, VHDL subset detectors, in latter phases of the design. This normally implies a automatic model property extractors, etc. Currently, detailed analysis of the VHDL code in order to detect there are beta releases of both VDM and VDS these kind of problems and to obtain an overall view (developed by TGI and LEDA). of the design quality. This quality is measured based on its accordance with a set of rules, stated for expert 2.2 VHDL Supercells Quality Tool Kit designers, that will avoid unpleasant surprises at the end of the design process. Aspects related with code The Validation and Design Quality Tool Kit is layout, signal naming, signal initialisation, and many specially oriented towards the design of Supercells. others are normally covered. Although not difficult, The main objective of the tool kit is to provide the this is a tedious task. The use of the proposed Design designer with methods to increase the quality of the and Modelling Quality Checkers will greatly help in final design and to have automatic methods to help this task, doing these checks automatically. in the review of the architectural and logic design stages. But quality metrics are not only useful for reviewers but also for designers. These metrics will help the designer to produce better VHDL description and to Performance Specifications Estimation Tools reduce the number of iterations in the design process. Reusability is another important objective of every design. The high costs associated with a design is Architectural Functional Performance Quality Design Validation Estimations Control doing final customers and design centres to invest a lot of effort making designs reusable. This implies the design should satisfy certain requirements in order to Quality Architectural Quality Checkers do the design industrially reusable. The use of the Control Review Design Metrics & Design and Modelling Quality Checkers will help the Validation Metrics designer analyse his/her designs in order to fulfil some of these aspects. For the final users the checkers will help them to analyse the quality of the macrocells they Logic Functional & Quality are using without the need of a deep knowledge of Synthesis Design Timing Verification Control their functionality. 2.2.1.1 Tool Description Quality Logic Design Control Review Timing & Structural The Design and Modelling Quality Checks are Inspection Quality Tool implemented as a set of tools called VHDL Quality ToolKit (QTK). These tools have been implemented in Physical Design C on top of LEDA VHDL System Tools (LVS). LVS Post-Layout is a set of tools that provide access (through an Simulations application procedural interface) to the VHDL Manu- facturing intermediate format (VIF). The results of the checkers are presented to the user through a Graphical User Interface (GUI) developed in Tcl/Tk. Figure 4 shows Figure 3: Use of the VHDL Quality Tool Kit, Per- the basic schema of the QTK. formance Estimation Tools and Timing & Structural Inspection Quality Tool GUI in Tcl/Tk (UPM) & VHDL Design Studio (LEDA) At the end of each design step a formal review is DQM & VDM Checkers performed. In these reviews aspects related with C-Functions (UPM) project management and circuit functionality are covered. From the functionality point of view the C-Procedural interface review is usually composed of two items: review of & VIF (LEDA) the simulations of the circuit and design quality VHDL Supercell control. The VHDL Quality Tool Kit will include Description (User) checkers to deal with these two aspects of the review and the design process itself. Figure 3 shows graphically where the VHDL Quality Figure 4: VHDL Quality ToolKit Environment Tool Kit and VHDL Performance Estimators are Although the GUI has been developed as an used in the design process. independent package, it has been integrated in LEDA
    • VHDL Design Studio (VDS), that has also been cumbersome. This analysis will help designers by developed within TOMI. The integration with LEDA providing them with a classification of the unit VDS consists of two parts, the “icon integration” and checked according to the following possibilities: the “GUI integration”. In the “icon integration” the • Description with only component instantiations results of the checkers are provided to the user • Description with component instantiations and through icons associated to each VHDL design unit, simple signal assignments so the user can quickly identify those VHDL • Mixed descriptions with components and descriptions with problems. In the “GUI integration” behavioural statements the user can obtain, through a pop-up menu, • Behavioural descriptions. extended information on the results of the checkers. • Data-flow descriptions In the current release, the QTK provides the Object usage: While coding VHDL descriptions, following checkers to analyse the VHDL description: often more objects are declared than really used. This Sensitivity List Analysis: When developing VHDL aspect worsens not only code maintainability but also code, sometimes it is difficult for designers to be the detection of hidden errors (forgotten ports…). aware of errors or omissions in sensitivity lists. This Designers who want to avoid this problem find this causes unpleasant surprises that are only discovered task heavy and monotonous and not always successful; after synthesis, delaying the project development. therefore automatic search is needed. The Object The Sensitivity List Analysis points out those Usage Analysis searches thoroughly in design units for erroneous or to pay attention processes, providing unused objects, reporting declared and not used ports, the following results, depending on the signals read signals, variables and constants or generics. in the process: Hard Coded Integer Values: Code reusability • There is no sensitivity list requires hard code values in the description to be • There are only clock and reset in the sensitivity substituted by constants or generics. In this way, list modification of the module characteristics may be • Not all signals read in combinational or carried out easily. Integers hard coded in the VHDL sequential processes are in the sensitivity list descriptions are detected and highlighted. A “clever” • Reset signal is not appearing in the sensitivity list algorithm is used in order to report not all values but of a sequential process only those interesting for the designer. Figure 5: Outlook of the QTK integrated in VDS Architectural Description Style: the description Tri-State Signals: In some ASIC design methodolo- style has influence on code maintainability and gies or technologies the use of tri-state signals is not synthesis results. On the other hand, behaviour allowed or recommended. This analysis will highlight embedded in structural descriptions makes the code
    • those signals that are going to be synthesised as tri- Anyhow, at the moment, it has not been possible to state buffers. apply the checkers to a on-running project from the Clock and Reset Analysis: Clock and reset schemes beginning, nor a comparative method has been are one of the most critical issues in a design. For established to measure the save of design time or designers it is important to know not only which quality improvement due to the use of the checkers. signals are registered by a clock or initialised by a reset, but also whether the clock or reset may cause Design Type L.O.C.* Gates M R problems due to glitches, metastability, etc. Aerospace ASIC 6800 7000 VH VH For every clock described in the design this analysis Industrial ASIC 9200 25000 H VH points out: Aerospace ASIC 10200 4000 H VH • Whether the clock is driven from combinational Industrial FPGA 1200 900 H VH or sequential logic, or from a external port • Signals and variables triggered by the clock Academical FPGA 1700 10000 M VH signal Industrial Module Library 8000 200-3000 H M • Whether the clock drives combinational logic, Academical Module Library 6100 500-4000 L M data of flip-flops, etc. Industrial FPGA 4000 8000 H VL • Dependencies with other clocks Academical Module Library 8500 3000-8000 M VL For every reset described in the design this analysis points out: VH: Very High; H: High; M: Medium; L: Low; VL: Very Low *L.O.C (Lines Of Code) • Whether the reset comes from combinational or sequential logic, or from a external port Table 1: Results from QTK for some designs • Signals and variables initialised by the reset signal 2.2.2 Validation Quality Checkers • Whether the reset is source of combinational The goal of the review of the simulations of the circuit logic, data of flip-flops, etc. is not only to check that the functionality of the circuit • Dynamic or static initialisation is in accordance with the specifications, but also to analyse the quality of the test benches used in the Most of these checkers accept full VHDL, although simulations. Simulations that do not exercise all the the checkers that deals with clocks and reset only lines of the VHDL code are normally rejected. This consider the VHDL Synopsys subset and hardware quality criteria may not be enough to guarantee the semantic. There are other checkers that are under high quality needed in complex designs. The use of the development; these are checkers to detect inferred Validation Quality Checkers will allow not only to latches and redundant memory elements. check if all lines of VHDL code are exercised, but also The GUI shows the results of the checkers in a to check if the effects of the simulations may be compact tabular form with hypertext. This allow observed at the outputs of the blocks that are being Design Managers to quickly evaluate the quality of a analysed. VHDL description or library. The information, For the designer, the Validation Quality Checkers will warnings or source of problems provided by the help in the development of quality test benches mainly checkers is directly highlighted on the VHDL source during the architectural design phase. Anyhow, they code. Figure 5 shows the outlook of the QTK also will allow the designer to detect typical coding integrated in VDS. errors in any stage. This aspect is specially important 2.2.1.2 Results from the VHDL Quality Toolkit due to the great amount of modifications a VHDL The beta version of the QTK has been used to model may pass through (even if it is functionally analyse the quality of several industrial and correct). academical circuits developed in VHDL at UPM Currently, a prototype of the VHDL Validation labs. In order to have a global overview of the Quality Checker is under development. The prototype quality of a design, a preliminary global qualification is based on an error model and fault simulation has been obtained for every design taking into technique [9-12]. For the first prototype, anyhow, a account the results of all checkers. Values (see Table commercial VHDL simulator will be used. 1) have been obtained to evaluate maintainability The refinement process of a VHDL description (M) and reliability (R) of a design (or design requires each VHDL model to be validated with a test library). bench. After functional validation, some performance It is interesting to observe that designs with higher estimations may be done. This estimations will guide scores correspond to industrial designs with better the designer to choose the best implementation for a design methodologies (ESA, PRENDA) [4-8]. It module or, once an implementation has been selected, should also be noted that the prototypes of the to refine the VHDL description without the need of designs with very low values did not work properly synthesis. As stated before, quality control will allow for the analysed versions. the designers to improve their VHDL descriptions in
    • order to reduce the risk of problems in the following 3. Conclusions phases of the design. A general view of the use of the tools developed in 2.3 Timing and Structural Inspection Quality TOMI has been presented. As it can be seen, TOMI Tool tools are used in almost all stages of the design process from specification to logic design. The use of new design techniques to increase the speed and reduce the power consumption forces the Some of the tools are oriented towards design designers to include in their designs multiple management, and therefore they will help to improve clocking with different edge, gate clock and other the quality of the design process. Others tools are asyncrhonous statements that could produce hazards oriented to measure the quality of the design itself. and races. These tools together will greatly help to improve the global quality of a design and to reduce the Unfortunately this kind of design is really risky, and development time. This is not only important when it is necessary a tool in order to help the designers designing complex circuits, but also, and very with this kind of structures. This is the main goal of specially, when designing Supercells that are going to the Timing and Structural Quality Tool. be used by third parties. But not only risky designs need a checker to detect Currently, beta versions of almost all tools developed possible timing or structural problems. In many in TOMI are available. It is expected to have final occasions, conservative designs may produce risky versions available for evaluation by March 98. structures due to poor quality code, improper operation of the tools, or problems produced by the 4. Bibliography synthesis tools themselves. [1] M. Blüml, B. Kierdoff, M.Lenzen, A.Pawlak “A In other cases, it is not feasible, or even not possible, Methodology for the Develpment of High Quality to modify a design at the architectural level or logic Standard - Cell Models in VHDL”, VHDL Forum level in order to introduce some changes or special Spring’92, Santander, April 1992. structures (clock buffering, last-minute changes in [2] Y. Torroja, T. Riesgo, E. de la Torre, J. Uceda, logic levels, etc.). In these cases, the designer may quot;Design Reusability: Generic and Configurable have to do some modifications in the netlist that are Designsquot;, VHDL Forum in Europe, Toledo (Spain), April 1997. (invited paper) difficult to back-annotate in the previous phases in [3] ESIP, Deliverable #203: Standardisation order to pass quality controls. Activities. The Synthesis Package, ESIP (ESPRIT The Timing and Structural Quality Tool will detect no. 8370), July 1994 all the potentially problematic structures (mostly no [4] PRENDA, Metodología de diseño de ASICs, detected by simulation) once the design has been PRENDA Project, February 1996. synthesised. [5] OMI, OMI 326: VHDL Coding Standard, OMI Figure 3 shows graphically where the Timing and Standards (ESPRIT no. 7267) July 1995. Structural Inspection Quality Tool is used in the [6] ESA/ESTEC, VHDL Modelling Guidelines, design process. ESA/ESTEC, September 1995. [7] ECIP, Guidelines for VHDL Use (Row 22), ECIP Once the architectural design phase has been (ESPRIT no. 2072), July 1993 completed, the logic design is accomplished. During [8] Bern Cohen, VHDL Coding Styles and this phase, the VHDL descriptions are refined to Methodologies, Kluwer Academic Publishers, obtain an optimum synthesisable description. This 1995. description is then synthesise taking into account [9] S. Kang, S. A. Szygenda, “Design Validation: area, timing and power consumption constraints. The Comparing Theoretical and Empirical Results of process may need some iteration until desired results Design Error Modeling”, IEEE Design & Test of are obtained. A functional verification is needed in Computers, Spring 1994, pp. 18-26, 1994. order to verify that design functionality has not [10] T. Riesgo, Y. Torroja, C. Lopez, J. Uceda, changed. quot;Estimation of the Quality of Design Validation When designing Supercells, designers will use the Based on Error Modelsquot;, VHDL Forum in Europe, Toledo (Spain), April 1997. Timing and Structural Inspection quality Tool to [11] ESIP, Deliverable #216: Final Report on the verify that their designs do not contain problematic Achievements of the ESIP Fault Modelling and structures, and correct them if necessary. When Simulation Activity, ESIP (ESPRIT no. 8370), using Supercells previously designed, the quality October 1995. control of this cells will be performed during the [12] T. Riesgo, J. Uceda, “A Fault Model for VHDL review of the logic design stage. Descriptions at the Register Transfer Level”, Currently, there is a beta version of the VHDL Proceedings of EURO-DAC with EURO- Timing and Structural Inspection Quality Tool that VHDL’96, Geneva (Switzerland), September accepts VHDL flat structural descriptions (nestlists). 1996.