Isat06 Rev2

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Changing semiconductor industry and US role

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  • Isat06 Rev2

    1. 1. The New Semi Industry Meta Modeling for Trusted IP Rajesh Gupta University of California, San Diego. mesl . ucsd . edu
    2. 2. Take Away Messages <ul><li>#1 Shift to fabless aligns MIL interests even more to new Semi houses </li></ul><ul><ul><li>Domain-specific designs, IP protection, small volume manufacturing, ESL </li></ul></ul><ul><ul><li>Yet a huge gap in their R&D needs (see #3) </li></ul></ul><ul><li>#2 Ensuring Trust through technology leadership </li></ul><ul><ul><li>Create industry leverage points: EDA, 3D Packaging </li></ul></ul><ul><ul><li>Ownership of key (boutique) technologies: 3D, SIP, POP </li></ul></ul><ul><ul><ul><li>Own and embed key verification, certification pieces in-house </li></ul></ul></ul><ul><ul><li>Stewardship of a fledgling semi IP industry </li></ul></ul><ul><li>#3 Pre-competitive Consortia </li></ul><ul><ul><li>EDAtech initiative </li></ul></ul><ul><li>#4 MIL-SPEC updates for trust, reliability </li></ul><ul><ul><li>Meta-data spec, IP libraries </li></ul></ul><ul><li>#5 Shift to FPGAs is not an answer </li></ul><ul><ul><li>Rides a different technology curve </li></ul></ul>
    3. 3. US Leadership in 3D Packaging
    4. 4. A Changing Industry Technology and Business
    5. 5. Supply push from technology + Moore’s law, decreasing bom Demand pull from application + New sockets for chips
    6. 6. Increasing proliferation Share of semi content Vertical markets
    7. 7. Fabrication and Consumption Foundry Revenues Semi consumption
    8. 8. Alliances paint an interesting picture
    9. 9. Activity by region: 83.5% from vendors in US, 19% w/ Asia/Pacific
    10. 10. Chinese Engagements <ul><li>Incentives by the ministry to setup semi manufacturing </li></ul><ul><ul><li>20 fabs in next 4 years </li></ul></ul><ul><li>Example: Silicon Storage, Nanotech </li></ul><ul><ul><li>SST buys Ser B stake in Nanotech </li></ul></ul><ul><ul><li>Nanotech uses the money to build fab in Changzhou (0.25m) </li></ul></ul>
    11. 11. The Fabless <ul><li>Of the 72 distinct application markets that rely on value added IC designs (ASIC, ASSP, FPGA, SOC) </li></ul><ul><ul><li>over 50% are less than $500M </li></ul></ul><ul><ul><li>75% are less than $1B </li></ul></ul><ul><li>The rising fabless, fablite </li></ul><ul><ul><li>Domestic manufacturing declines to 17%, however </li></ul></ul><ul><ul><li>The US has 56% of over 1K design houses… </li></ul></ul><ul><ul><li>… and accounts for 76% of industry revenues </li></ul></ul><ul><ul><li>$24B going onto 50% of semis by 200X </li></ul></ul><ul><ul><li>Segments: Wireless 27%, networking 25%, consumer 20% </li></ul></ul><ul><li>Cost is increasingly the driver for fabless </li></ul><ul><ul><li>Only 17% of designs above 500 MHz </li></ul></ul><ul><ul><ul><li>67% of ASIC designs are 299 MHz and lower </li></ul></ul></ul><ul><ul><li>Sizes pretty much evenly distributed from 100K to 5M gates </li></ul></ul><ul><li>FPGAs and CPLDs making inroads into boxes </li></ul><ul><ul><li>61% of system cost is in FPGAs </li></ul></ul>Source: IBS
    12. 12. Swing to standardization <ul><li>Expensive first silicon </li></ul><ul><ul><li>(about 6X at 90nm than at 0.35nm) </li></ul></ul><ul><li>Product life span much shorter </li></ul><ul><ul><li>1-2 years compared to 3-5 years earlier </li></ul></ul><ul><li>Result: shrinking ASIC starts, increasing FPGA </li></ul>
    13. 13. Cambrian Explosion in  Systems <ul><li>We have the silicon capacity to do… </li></ul><ul><ul><li>Multiple cores </li></ul></ul><ul><ul><li>Multigrain “Programmable” circuit fabrics </li></ul></ul><ul><ul><li>Coprocessors and accelerators </li></ul></ul><ul><ul><li>Processor extensions: Short Vector SIMD, Media, Baseband, SDR, … </li></ul></ul><ul><li>Until, of course, you consider power </li></ul>16 64b SIMD Processing Elements API Interface OAK DSP 16 64b SIMD Processing Elements 16 64b SIMD Processing Elements API Interface API Interface OAK DSP
    14. 14. Computing Efficiencies <ul><li>Watt nodes: Home, Office, Car </li></ul><ul><ul><li>Compute intensive platforms </li></ul></ul><ul><ul><li>Reaching 1 Tops in 5-10W: 100-200 Gops/W </li></ul></ul><ul><ul><li>100-1000x more efficient that today’s PCs </li></ul></ul><ul><ul><li>Programmability must, innovation from domain knowledge </li></ul></ul><ul><li>MilliWatt nodes: Converged devices </li></ul><ul><ul><li>Wireless intensive: radios, networks, protocols, applications </li></ul></ul><ul><ul><li>Multimedia evolution to SVC leading to 9-36x more CPU than H.264 </li></ul></ul><ul><ul><li>10-hour battery operation, 1W for 10-100 Gops: 10-100 Gops/W </li></ul></ul><ul><ul><li>Combination of scaling and duty cycling, computing models </li></ul></ul><ul><ul><ul><li>Semi houses have to move from components to domain specialization </li></ul></ul></ul><ul><li>MicroWatt nodes: Immortal devices, ad hoc networks </li></ul><ul><ul><li>< 100 microwatts for scavenging, 10 Mops: very high peak efficiencies </li></ul></ul><ul><ul><li>Approach limits on computation and communication </li></ul></ul><ul><ul><li>Aggressive duty cycling (<1%, 1bps-10kbps). </li></ul></ul>
    15. 15. Intrinsic Power Efficiency of Silicon Substrates <ul><li>At 130 nm nodes (ISSCC99 T. Classen) </li></ul><ul><ul><li>MPU: 100 MOPS/W </li></ul></ul><ul><ul><li>FPGA: 1-2 GOPS/W </li></ul></ul><ul><ul><li>ASIC: 10-20 GOPS/W </li></ul></ul><ul><li>We are within 10x of efficiency requirements for custom ASICs (200 MOPS to 200 GOPS per Watt in 65nm) </li></ul><ul><ul><li>(hardware muxed datapaths with local storage and hw thread control) </li></ul></ul><ul><li>But 500x behind when dealing with SW programmable systems </li></ul><ul><ul><li>software development and software-dominated system design is the challenge </li></ul></ul><ul><ul><ul><li>Particularly for mW nodes where platform architecture uses a mixture of computing fabrics. </li></ul></ul></ul>
    16. 16. Shifts in PM and PL <ul><li>Thesis : A dramatic shift in PM is in progress! </li></ul><ul><li>Factors driving this shift </li></ul><ul><ul><li>Rich and diverse computing fabrics (in silicon) </li></ul></ul><ul><ul><li>Internet proliferation to end points: data and control integration over wide (and wireless) area with mobility </li></ul></ul>
    17. 17. 2. The Internet (= WAN) Influence <ul><li>Devices are becoming internet end points and accessing data through multi-level client-server hierarchies </li></ul><ul><li>Yet, it is a </li></ul><ul><ul><li>different kind of distributed system </li></ul></ul><ul><ul><li>different kind of data </li></ul></ul><ul><ul><li>different kind of database </li></ul></ul><ul><li>Effect: Explosion in APIs </li></ul><ul><ul><li>XML APIs: for data integration </li></ul></ul><ul><ul><li>Messaging APIs: for flow control across WAN </li></ul></ul><ul><ul><li>S&P APIs: for access control </li></ul></ul><ul><li>Typically, APIs migrate to PL extensions </li></ul><ul><ul><li>Though there are several emerging challenges and open questions on PL support for new data structures, control flows, assertions. </li></ul></ul>
    18. 18. Emerging Capabilities in Programming: Meta Data Handling <ul><li>Self-documenting/extensible “tags” </li></ul><ul><ul><li>Nested tags enable exchange of data (not just documents) </li></ul></ul><ul><ul><li>Data interchange is the basis for integration of services on the web </li></ul></ul><ul><li>There is no distinction between data and schema </li></ul><ul><ul><li>Simplest XML is a labeled ordered tree with labels on nodes, and possible data values at the leaves. </li></ul></ul><ul><li>Schema extracted through Data Type Definitions (DTDs) </li></ul><ul><ul><li>A DTD is an extended CFG with no terminals: </li></ul></ul><ul><ul><ul><li>Nonterminals are tags in the XML parse tree </li></ul></ul></ul><ul><ul><li>Not quite PL data type: Values are not constrained (all values as strings); Unordered things are difficult; Inability to separate type of an element from its name. </li></ul></ul><ul><li>New flexible/extensible types and schemas </li></ul><ul><ul><li>E.g., regular expressions over trees </li></ul></ul><ul><ul><li>Ability to talk “about” data / queries through reflection </li></ul></ul><ul><li>Example </li></ul><ul><ul><li><dealer> <UsedCars> <ad> <model>Honda</model><yr>92</yr> </ad></UsedCars> </li></ul></ul><ul><ul><li><NewCars> <ad> <model>Prius</model></ad></NewCars> </dealer> </li></ul></ul><ul><ul><li>root: dealer </li></ul></ul><ul><ul><li>dealer  UsedCars, NewCars </li></ul></ul><ul><ul><li>UsedCars  ad* </li></ul></ul><ul><ul><li>NewCars  ad* </li></ul></ul><ul><ul><li>ad  modelyear | model </li></ul></ul>
    19. 19. R Q A 1 1 2 2 1 3 1 2 2 1 1 C B A R 0 1 1 2 D C Q
    20. 20. IP Composition Need Introspection Capabilities <ul><li>Structural design </li></ul><ul><ul><li>#processes, triggering conditions, #ports, “plumbing” </li></ul></ul><ul><li>Behavioral design </li></ul><ul><ul><li>Model of computation, state machines, patterns of interaction </li></ul></ul><ul><li>Modeling dimensions </li></ul><ul><ul><li>Classes, and constructs for modeling semantics </li></ul></ul><ul><li>Runtime and tool infrastructure </li></ul><ul><ul><li>Static simulation information (setup, coordination/callbacks, tb) </li></ul></ul><ul><ul><li>Dynamic information (number and type of events in queue) </li></ul></ul><ul><li>… and so on. </li></ul><ul><li>Several ways to achieve it: </li></ul><ul><ul><li>Component design using patterns, subtyping, composition techniques, using IDLs </li></ul></ul>
    21. 21. Reflection and Introspection: <ul><li>Component: </li></ul><ul><ul><li>A unit of re-use with an interface and an implementation </li></ul></ul><ul><li>Meta-information: </li></ul><ul><ul><li>Information about the structure and characteristics of an object </li></ul></ul><ul><li>Reification: </li></ul><ul><ul><li>A data structure to capture the meta-information about the structure and the properties of the program </li></ul></ul><ul><li>Reflection: </li></ul><ul><ul><li>An architectural technique to allow a component to provide the meta- information to himself </li></ul></ul><ul><li>Introspection: </li></ul><ul><ul><li>The capability to query and modify the reified structures by a component itself or by the environment </li></ul></ul>5 ports adder
    22. 22. Our Approach <ul><li>Start with SystemC descriptions of IP blocks </li></ul><ul><ul><li>Multi-level (RTL, TL) descriptions </li></ul></ul><ul><li>Capture meta information of these IP into XML </li></ul><ul><ul><li>Mostly structural information for now. </li></ul></ul><ul><li>Generate library of ‘XMLized’ IP blocks </li></ul><ul><ul><li>Schema to match datatype and protocol type information across IP blocks </li></ul></ul><ul><ul><li>Create DOM model and constraints for the library </li></ul></ul><ul><li>Develop methods for IP selection, composition, verification, synthesis </li></ul><ul><ul><li>Automated methods for IP instantiation, interface generation </li></ul></ul><ul><li>IP Selection through an Introspective Composer </li></ul><ul><ul><li>IP matching and connection </li></ul></ul><ul><ul><li>Insertion of bridges </li></ul></ul><ul><ul><li>Validation of functionality </li></ul></ul><ul><ul><li>Create an executable specification </li></ul></ul>

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