Standard cell placement is a NP complete open problem. The main objectives of a placement algorithm are to minimize chip area and the total wire length of all the nets. Due to interconnect dominance, Deep Sub Micron VLSI design flow does not converge leading to iterations between synthesis and layout steps. We present a new heuristic placement algorithm called Sankeerna, which tightly couples synthesis and routing and produces compact routable designs with minimum area and delay. We tested Sankeerna on several benchmarks using 0.13 micron, 8 metal layer, standard cell technology library. There is an average improvement of 46.2% in delay, 8.8% in area and 114.4% in wire length when compared to existing placement algorithms. In this paper, we described the design and implementation of Sankeerna algorithm and its performance is illustrated through a worked out example.