DESIGN & DEVELOPMENT OF NANOELECTRONIC AOI & OAI DEVICES BASED ON CMOS AND QCA (QUANTUM-DOT CELLULAR AUTOMATA) NANOTECHNOLOGY
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DESIGN & DEVELOPMENT OF NANOELECTRONIC AOI & OAI DEVICES BASED ON CMOS AND QCA (QUANTUM-DOT CELLULAR AUTOMATA) NANOTECHNOLOGY

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Nanotechnology is derived from the evolution of microelectronics towards miniaturization. CMOS Technology has been targeted to integrate more and more Devices per unit area of Silicon-substrate,......

Nanotechnology is derived from the evolution of microelectronics towards miniaturization. CMOS Technology has been targeted to integrate more and more Devices per unit area of Silicon-substrate, but there is limitation in scaling-down CMOS Circuits/Devices. Like Nanotechnology, QCA (Quantum-Dot Cellular Automata) is another alternate Technology having ability to reduce the Device-sizes beyond the CMOS Devices. The QCA enables the Moore’s law to double the Devices every 18 months. The continued improvements in miniaturization, speed and power reduction in information processing devices, sensors, displays, logic devices, storage devices, transmission devices, communication devices, etc. will bring another Technical Revolution, which will change our life. The Design Strategies focus on CMOS Technology (<50 nanometer) and QCA Nanotechnology to achieve low power consumption, low voltage operation, high operating frequency, minimize number of transistors/gates/devices, reduced fabrication cost, high speed communication, flexibility, programmability, and service efficiency. In our Research Work, we would like to focus on Design & Development of Nanoelectronic AOI & OAI Devices based on CMOS and QCA (Quantum-Dot Cellular Automata) Nanotechnology as Building Blocks for constructing more complex Circuits/Devices, defining Finite-State-Machines and Binary Decision Trees for Features/Functionalities and monitoring Status of WiMAX/WiFi/Satellite and other Wireless Communication Systems.

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  • 1. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963 DESIGN & DEVELOPMENT OF NANOELECTRONIC AOI &OAI DEVICES BASED ON CMOS AND QCA (QUANTUM-DOT CELLULAR AUTOMATA) NANOTECHNOLOGY S. Devendra K. Verma1 & P. K. Barhai2 Birla Institute of Technology, Mesra, Ranchi, Jharkhand, IndiaABSTRACTNanotechnology is derived from the evolution of microelectronics towards miniaturization. CMOS Technologyhas been targeted to integrate more and more Devices per unit area of Silicon-substrate, but there is limitationin scaling-down CMOS Circuits/Devices. Like Nanotechnology, QCA (Quantum-Dot Cellular Automata) isanother alternate Technology having ability to reduce the Device-sizes beyond the CMOS Devices. The QCAenables the Moore’s law to double the Devices every 18 months. The continued improvements inminiaturization, speed and power reduction in information processing devices, sensors, displays, logic devices,storage devices, transmission devices, communication devices, etc. will bring another Technical Revolution,which will change our life. The Design Strategies focus on CMOS Technology (<50 nanometer) and QCANanotechnology to achieve low power consumption, low voltage operation, high operating frequency, minimizenumber of transistors/gates/devices, reduced fabrication cost, high speed communication, flexibility,programmability, and service efficiency. In our Research Work, we would like to focus on Design &Development of Nanoelectronic AOI & OAI Devices based on CMOS and QCA (Quantum-Dot CellularAutomata) Nanotechnology as Building Blocks for constructing more complex Circuits/Devices, defining Finite-State-Machines and Binary Decision Trees for Features/Functionalities and monitoring Status ofWiMAX/WiFi/Satellite and other Wireless Communication Systems.INDEX TERMS: Nanotechnology; Nanoelrctronic; Nanoelectromechanical Systems (NEMS); VLSI; MOSFET; NMOS;PMOS; CMOS; BiCMOS; QCA; AOI, OAI; WiMAX; WiFi; I. INTRODUCTIONEvolution of microelectronics towards miniaturization is one of the main motivations forNANOTECHNOLOGY. The famous empirical Moore’s Law states that number of Transistors perchip doubles every 18 months. The Semiconductor Industry Association (SIA) has developed aRoadmap for continued improvements in miniaturization, speed and power reduction, to overcomeCMOS Technology’s scaling limitations. Specifying Nanostructures (Transistors) within the size of 1-50 nanometers for simulation of Nanotechnology Devices, based on CMOS Technology and QCATechnology will be the initial approach, followed by enhancements/refinements.Rapid advancements in Nanotechnology, such as Nanomaterials, Nanometer CMOS Devices,Nanoelectronic, Nanoelectromechanical Systems (NEMS), Nanophotonic Devices, etc. are going tobring radical changes in the society and particularly in Wireless Communication, where small, smartand speedy systems are everyone’s first choice. This is possible as application of Nanotechnology istaking place in WiMAX/WiFi/Satellite and other Wireless Communication systems, which is ‘State-of-the-Art’ Technology at the moment. [4], [5], [7]. CMOS (Complementary metal–oxide–Semiconductor) is a technology for constructing integratedcircuits. CMOS technology is used in Microprocessors, Microcontrollers, Static RAM, and other 336 Vol. 6, Issue 1, pp. 336-345
  • 2. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963Digital Logic Circuits. CMOS technology is also used for several Analog Circuits such as ImageSensors (CMOS sensor), Data Converters, and highly integrated Transceivers for many types ofcommunication. CMOS circuits use a combination of p-channel and n-channel Metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement Logic Gates. CMOS also allows ahigh density of logic functions on a chip. It was primarily for this reason that CMOS became the mostused technology to be implemented in VLSI chips.WiMAX (World-wide Interoperability for Microwave access) will offer Broadband Wireless Accessat Data Rate of Multiple Mega Bits per Second to the End-user within a range of Several Kilometers.WiMAX supports a variety of Wireless Broadband Connections: High-bandwidth MANS(Metropolitan-Area Networks), Cellular Base Stations and Internet for WiFi. WIMAX is acomplement to Fixed, Portable and Mobile Access. The Multimode SMART WiMAX will allow EndUser Devices to support New High-speed Services in many Different Network Environments. Thiscan be achieved with Nanotechnology based WiMAX/WiFi Devices/Components. A WirelessCommunication System can be upgraded and deployed as ‘Mobile Ad Hoc Access Wireless System’and ‘Portable Internet’ with Nanotechnology based WiMAX/WiFi Communication System. [10],[17], [21], [22].WiMAX opens the Door to thousands of Applications to connect People together. With the high DataRate, Applications will include Video Transfer, Voice Calls, and many other Service. Development ofCommunication Devices based on NANOTECHNOLOGY and its Applications is one of the GrandChallenges for this Century. Devices developed for IT, Data Storage and Wireless Communicationswill have Potential Applications in Defence, Aerospace, Automotive, Consumer Technologies,Business, Education, Research and many more areas.The Paper is organized as follows, Section 2: CMOS & QCA Technologies; Section3: Methodology;Section 4: AOI & OAI; Section 5: Simulation Setup &Tools; Section 6: Simulation Models; Section7: Simulation Results; Section 8: Conclusion; Section 9: Future Work; and Section 10: References.II. CMOS & QCA TECHNOLOGY2.1 CMOS TechnologyCMOS Logic is a combination of NMOS and PMOS Logic. The MOS Process is categorized asNMOS, PMOS, and CMOS. The basic Devices in MOS Processes are the p-channel and n-channelMOSFETs. The p-channel MOSFETs are not as attractive as those of n-channel MOSFETs becausethe mobility of p-type material is poorer than of the n-type material. In CMOS (ComplementaryMetal-oxide Semiconductor) Technology, both N-Type and P-Type Transistors are used to realizeLogic Functions. It is the dominant Semiconductor Technology for Microprocessors, Memories andApplication Specific Integrated Circuits (ASICs). CMOS has advantages over NMOS and BipolarTechnology, as it has smaller power dissipation only when Circuit switches. It consumes very littlepower, particularly for Mobile Communication. This allows integration of many more CMOS Gateson an IC than NMOS or Bipolar Technology and fabricating VLSI Circuits with much betterperformance. [9], [12], [16].2.2 QCAT TechnologyQCA was first introduced in 1993 by Lent et al. It represents an emerging Technology at theNanotechnology level. QCA uses Quantum Wells with 4 Quantum-Dots having 2 mobile Electrons torepresent Logic States. The Electrons can move to different Quantum-Dots in the QCA Cell by meansof Electron Tunnelling and its position is determined based on the Columbic Force, positioning oneelectron from the other one in diagonally located Quantum-Dots. The Electrons are able to tunnelbetween the Dots. Based on the Electrons’ positions, there are two possible Polarizations -1 or +1,indicating Binary 0 and Binary 1. The Polarization of each Cell depends upon the Polarization of itsprevious neighboring Cell. The QCA Cell Architecture is shown in Fig. 1. 337 Vol. 6, Issue 1, pp. 336-345
  • 3. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963 Fig. 1: QCA Cell ArchitectureA Binary Wire and Inverter Chain is shown in Fig. 2. The Binary Wire is known as Logic SignalTransmission Channel, where the Cells transmit information in Coded form (0 or 1) from one Cell toanother without any current flow. Polarization of each Cell depends upon the polarization of itsprevious neighboring Cell only. In the Inverter Chain, the Code of the previous neighboring Cell isinverted and thus the transmission of Code takes place. In QCA, the Information propagates along aline of Cells due to Columbic Charge interaction, compared to conventional Electronic Current inCMOS Devices. The Columbic Force is responsible for all the Logic Operations and transfer of theStates from one location to another. Fig. 2: Binary Wire & Inverter ChainQCA is based on the encoding of Binary Information in the Charge configuration within Quantum-Dot Cells. QCA is implemented based on Majority Gate having three Input, one Output and oneCenter (Device) Cells. If A, B, C are Inputs then Output = M(A,B,C) = AB+BC+CA. If the inputpolarization of Control Input is fixed to +1 (logic 1), the OR logical operation is performed and in thecase of -1 (logic 0) the AND logical operation is performed. The NOT logical operation is performedwhen the Cells are placed diagonally. The Majority OR, AND, and NOT Gates are shown in Fig.3.[11], [13], [20], [3], [14], [18].A multizone Clock mechanism is required for proper Data Propagation in the QCA Circuit. FourClock Signals having 90 degree relative phase difference with each other, are used for the operation ofthe QCA Circuits. The four Clock Phases/States are identified as Switch, Hold, Release and RelaxStates and the four Clocking Zones are identifies as Zone 0, Zone 1, Zone 2 and Zone 3. Each Cell ina Clocking Zone is connected to one of four Phases of the QCA Clock. The polarization of the QCACell is determined in the Switch and Hold States depending on the polarization of the neighboringCell. The Release and Relax States are unpolarized. Each Cell is latched and unlatched with thechanging of the Clock Signal. The Clock synchronizes and controls the flow of information as well assupplies the necessary power to the Cells. The QCA Clock and QCA Clock Zones are shown in Fig.4. [15],[1], [2], [6], [8]. 338 Vol. 6, Issue 1, pp. 336-345
  • 4. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963 Fig. 3: QCA Cell Logic Gate Fig. 4: QCA Clock SignalIII. METHODOLOGYOur approach will be to design, develop and qualify a ‘Nanoelectronic AOI & OAI Device’ to thescale of < 50 nanometer, based on CMOS Technology, using CADENCE Software Tool. Reductionin the number of Components through integration and optimization of its performance is alsoexercised in this Design Simulation. Depending on the facility available, it seems that the ‘MolecularNanoelectronics’ Technology and the ‘Top-down’ approach is more suitable for obtainingNanostructure within the size of 1-50 nanometers scale and Voltage < 1.8V. A QCA DesignerSimulator is used to layout and verify QCA Logic Design for the AOI & OAI Devices to the scale of< 20 nanometer QCA Cell size and powered with Clock Signal. [19].IV. AOI & OAI4.1 AND-OR-INVERT (AOI)AOI Gate is suitable for SOP (Sum-of-Products) Function expressed as a Summation (OR) ofProducts (AND) terms. An AOI Logic Function is one that implements the operations in the orderAND then OR then NOT (INVERT). As for example; X = ((a.b.c.d) + (e.f.g.h)). 339 Vol. 6, Issue 1, pp. 336-345
  • 5. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-19634.2 OR-AND-INVERT (OAI)OAI Gate is suitable for POS (Product-of-Sums) Function, expressed as a Product (AND) ofSummation (OR) terms. An OAI Logic Function is one that implements the operations in the order ofOR then AND then NOT (INVERT). As for example: y = ((a+b+c+d). (e+f+g+h)).The inverting nature of CMOS Logic Circuits allows us to construct Logic Circuits for AOI and OAILogic Expressions using a Structured Approach.V. SIMULATION TOOLS & SETUP5.1 CADENCE SOFTWARECadence Software Tool is an Electronic Design Automation Software, known as Cadence Analog andDigital System Design Tools (GPDK46nm). It is used for CMOS Circuits Simulation. The ProcessGeometries include scales of 45nm and 65nm for length and width of a Transistor.5.2 QCADESIGNERQCADesigner Tool is used for QCA Circuits Simulation. It has CAD capabilities which helps tolayout and simulate QCA Circuits constructed with QCA Cells. Each Cell is 20nm in size.QCADesigner has three Simulation Engines to facilitate rapid and accurate simulation: a) DigitalLogic Simulation Engine, which determines Cells to be either null or fully polarized; b) NonlinearApproximation Simulation Engine, which determines the stable state of the Cells, depending on thenonlinear cell-to-cell response function; and c) Two-State Simulation Engine, which forms anapproximation of the full quantum mechanical model. The control of the flow of information in QCACircuits is performed using four Clock Signals: Clock Zone 0, Clock Zone 1, Clock Zone 2 and ClockZone 3.VI. SIMULATION MODELSWe have developed two Simulation Models: a) CMOS Model and b) QCA Model for the AOI & OAIand the Simulation Results are analysed accordingly.6.1 CMOS MODELUsing CADENCE Software Tool, a Model of the AOI & OAI is simulated and its performance isanalysed. A Model of AOI Logic Circuit is shown in Fig. 5. The Model has two AND Gates, eachhaving four inputs, and the outputs of the AND Gates are inputs of the OR Gate, and the output of theOR Gate is input to an INVERT Gate. A Model of OAI Logic Circuit is shown in Fig. 6. The Modelhas two OR Gates, each having four inputs, and the outputs of the OR Gates are inputs of the ANDGate, and the output of the AND Gate is input to an INVERT Gate. These Gates are detailed withCMOS Circuits. Fig. 5: AOI - Logic Circuit Fig. 6: OAI - Logic Circuit 340 Vol. 6, Issue 1, pp. 336-345
  • 6. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963A Models of AOI – CMOS Circuit and OAI – CMOS Circuit are shown in Fig. 7 and Fig. 8. TheModels are simulated using CADENCE Software Tool (for 1.8V and 45 nanometer scale). TheModels are analysed with two sets of Inputs and the Transient Responses are recorded accordingly.The Transient Responses for AOI – CMOS Circuit are recorded as shown in Fig. 9 and Fig. 10. TheTransient Responses for OAI – CMOS Circuit are recorded as shown in Fig. 11 and Fig. 12. Fig. 7: AOI – CMOS Circuit Fig, 8: OAI – CMOS Circuit Fig. 9: AOI – Transient Response-A Fig. 10: AOI – Transient Response-B Fig. 11: OAI – Transient Response-A Fig. 12: OAI – Transient Response-B6.2 QCA MODELThe QCA Models of the AOI & OAI are simulated and its performance is analysed. The Model ofAOI Logic Circuit has two AND Gates, each having four inputs, and the outputs of the AND Gates 341 Vol. 6, Issue 1, pp. 336-345
  • 7. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963are inputs of the OR Gate, and the output of the OR Gate is input to an INVERT Gate. The Model ofOAI Logic Circuit has two OR Gates, each having four inputs, and the outputs of the OR Gates areinputs of the AND Gate, and the output of the AND Gate is input to an INVERT Gate. These Gatesare detailed with QCA Circuits. The AOI – QCA Logic is shown in Fig. 13 and the OAI – QCA Logicis shown in Fig. 14.The AOI - QCA Logic is defined as follows:QCA AND Logic 1: x1 = m(a,b,c,d,0) = m(1,1,1,1,0) = 1; QCA AND Logic 2: x2 = m(e,f,g,h,0) =m(1,1,1,1,0) = 1QCA OR Logic 1: x = m(x1,x2,1) = m(1,1,1) = 1; QCA INVERT Logic 1: z = x’ = 0.The OAI - QCA Logic is defined as follows:QCA OR Logic 1: x1 = m(a,b,c,d,1) = m(1,1,1,1,1) = 1; QCA OR Logic 2: x2 = m(e,f,g,h,1) =m(1,1,1,1,1) = 1QCA OR Logic 1: x = m(x1,x2,0) = m(1,1,1) = 1; QCA INVERT Logic 1: z = x’ = 0. Fig. 13: AOI – QCA Logic Fig. 14: OAI – QCA LogicUsing QCADesigner Simulator, the Simulated Models of the ‘AOI – QCA’ and ‘OAI – QCA’ aredeveloped (<20 nanometer) and the Simulation Results are analysed. The as shown in Fig. 15 & Fig.16. The Simulation Results for AOI – QCA Simulated Model are shown in Fig. 17 and Fig. 18, andfor OAI –QCA Simulated Model are shown in Fig. 19 and Fig. 20. Fig. 15: AOI – QCA Simulated Model Fig. 16: OAI – QCA Simulation Model 342 Vol. 6, Issue 1, pp. 336-345
  • 8. International Journal of Advances in Engineering & Technology, Mar. 2013. ©IJAET ISSN: 2231-1963 Fig. 17: AOI – QCA Simulation Result Part-A Fig. 18: AOI – QCA Simulation Result Part-B Fig. 19: OAI – QCA Simulation Result Part-A Fig. 20: OAI – QCA Simulation Result Part-BVII. SIMULATION RESULTS The CMOS Model is simulated and qualified for 1.8V and 45 nanometer scale. The QCA Model is simulated and qualified for Cell size <20 nanometer with Scale factor of ‘1’ for all Cells. The Clock high 9.8e-22J and Clock low 3.8e-23J are recorded. It is verified that the QCA Circuits based on Majority Logic are similar to the CMOS Circuits and it minimizes the complexity, delay and size (comparing the number of Transistors and Cells and its sizes).VIII. CONCLUSION In our Research Work, we have focused on Design & Development of Nanoelectronic AOI & OAI Devices, based on CMOS & QCA Nanotechnology as Building Blocks for Communication Devices, and a comparative evaluation is performed. In CMOS Technology Transistors are used to construct Gates/Devices while in QCA Technology Cells are used to construct Gates/Devices. Our objective is to design and develop CMOS and QCA based Circuits/Devices as Building Blocks which can be used for constructing more complex Circuits/Devices, defining/verifying Features/Functionalities and monitoring Status of WiMAX/WiFi/Satellite and other Wireless Communication Systems. Applications of CMOS & QCA Nanotechnology in WiMAX/WiFi Wireless Communication will lead towards Architectural Innovation & Smart Devices, Value Added Services, Full Scale QoS (Quality of Service) and Higher Reliability and Security. Our Research Work will help in addressing Long term Technical Challenges pertaining to “Design, Development and Application of CMOS & QCA 343 Vol. 6, Issue 1, pp. 336-345
  • 9. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963Nanotechnology in WiMAX/WiFi/Satellite and other Wireless Communication Systems,” and providefeedback to ICs Designers/Managers, Wireless Standards Managers, Wireless and Internet ServiceProviders and other Interest Groups.IX. FUTURE WORKThe Future Work will be focused on auto-layout design for both CMOS and QCA Circuits and itscomparative analysis and optimization. Further efforts will be on scaling down and low voltageoperation and functional verification. Also, defining/designing Finite-State-Machines and BinaryDecision Trees based on AOI and OAI Circuits to incorporate Features/Functionalities andMonitoring Status for WiFi/WiMAX/Satellite and other Wireless Communication Systems/Services.REFERENCES[1] Agrawal, D. and Ghosh, B., 2012, “Quantum Dot Cellular Automata Memories,” IJCA Journal, Vol. 46, No. 5, May 2012.[2] Amiri, M. A., Mirzakuchaki, S., Mahdavi, M., 2010, “LUT-Based QCA Realization of a 4x4 S-Box,” Canadian Journal of Electrical and Electronics Engineering, Vol. 1, No. 3, April 2010.[3] Amlani, I. et al., 1999, “Digital logic using Quantum-dot Cellular Automata,” Science, vol. 284, pp. 289-291, Apr. 1999.[4] Atakan, B. and Akan, O. B., 2010, Middle East Technical University, “Carbon Nanotube-Based Nanoscale Ad Hoc Networks,” IEEE Communications Magazine, June 2010, pp.129-135.[5] Bourne, M., 2007, “A Consumer’s Guide to MEMS & Nanotechnology,” Scottsdale, AZ., 2007.[6] Chakrabarty, R., De, D., Ghosh, K. K., 2011, “Design and Analysis of Quantum-Dot Cellular Automata Johnson Counter,” IEMCON (collaboration with TEEE), Jan 2011.[7] Ellenbogen, J. C., 1998, The MITRE Corp., “A Brief overview of Nanoelectronic Devices,” MITRE MSR Program, Jan. 1998.[8] Ganesh, E. N., 2010, “Implementation and simulation of arithmetic logic unit, shifter and multiplier in Quantum cellular automata technology,” IJCSE Journal, Vol. 02, No. 05, 2010.[9] Geppert, L., 2004, “Chip Making’s West New World,” IEEE Spectrum, May 2004, pp. 21-25.[10] Ghosh et al., 2005, “Broadband Wireless Access with WiMAX/802.16: Current Performance Benchmarks and Future Potential,” IEEE Communications Magazine, Feb. 2005, pp. 129-136.[11] Ilanchezhian, P.and Parvathi, R. M. S., 2012, “Implementation of High Speed Reed Solomon Decoder using Nanotechnology based Quantum Dot Cellular Automata,” European Journal of Scientific Research, Vol. 77, No. 1, 2012, pp. 158-164.[12] Islam, M. A. and Waran, L., 2010, University of Califoria, Davis, “Nanotechnology Materials and Devices for Future Communication Networks,” IEEE Communications Magazine, June 2010, pp.112-120.[13] Keikha, A. et al, 2011, “A Novel Design of a Random Generator Circuit in QCA,” IJCA Journal, Vol. 35, No.1, 2011.[14] Lent, C. S. et al, 1993, “Quantum Cellular Automata,” Nanotechnology, Vol. 4, No. 1, 1993, pp. 49-57.[15] Lent, C. S. & Isaksen, B., 2003, “Clocked Molecular Quantum-Dot Cellular Automata,” IEEE Transaction on Electron Devices, Vol. 50, No. 9, Sept. 2003.[16] Nirmal, Kumar, V., Jabaraj, S., 2010, “NAND Gate using FINFRT for Nanoscale Technology,” IJEST Journal, Vol. 2(5), 2010.[17] Samee and Shukla S., 2006, “WiMAX: Latest Mobile Technology,” Telecommunications, Jan-Feb. 2006, pp. 77- 83.[18] Tougaw, P. D. & Lent, C. S., 1994, “Logical Devices Implemented Using Quantum Cellular Automata,” Journal of Applied Physics, Vol. 75, No. 3, 1994, pp. 1818-1825.[19] Verma, S. Devendra K. and Barhai, P. K., 2012, “Design & Development of Nanoelectronic Binary Decision Tree Device based on CMOS and QCA (Quantum-Dot Cellular Automata) Nanotechnology,” IJCA Journal, Vol. 7, No. 1, 2012.[20] Vijayalakshmi, P. and Kirthika, N., 2012, “Design for Hybrid Adder using QCA with Implementation of Wallace Tree Multiplier,” IJAET Journal, Vol. 3, No. 2, May 2912.[21] WiMAX Forum, 2006, “Mobile WiMAX – Part I: A Technical Overview and Performance Evaluation,” May 2006.[22] WiMAX Forum, 2006, “Mobile WiMAX – Part II: A Comparative Analysis,” June 2006.BIOGRAPHIESS. Devendra K. Verma BSc.EE (India), MSEE (USA), MBA (USA), MIEEE, FIEI. He hasBScEE (RIT Jamshedpur (now NIT), Ranchi University, India), MSEE (Columbia University,NY, USA), and MBA (Fairleigh Dickinson University, NJ, USA). He is having 20+ years ofTechnical/Management (R&D Environment) Experience in ECE (Electronics andCommunication Engineering) and ICT (Information Communication Technology in USA (atAT&T Bell Lab., NYNEX Science & Technology Inc. (R&D), Bell Communication Research 344 Vol. 6, Issue 1, pp. 336-345
  • 10. International Journal of Advances in Engineering & Technology, Mar. 2013.©IJAET ISSN: 2231-1963(Bellcore), and United Technologies), and 10+ years in Industries and Teachings. He has two Patents with theUSA Government. Excluding internal publications, He has about 25+ Technical Publications (mostly in USA,India, and a few in Europe and China). Research, Teaching and Management have been salient Features of hisresponsibility. Since 2006, he is associated with the B.I.T. Mesra (a Deemed University), Ranchi, India, as aFaculty (later Visiting Faculty) in the Dept. of E.C.E. He is a Sr. Member of IEEE (Communication Society), aFellow of the IEI, and actively involved in its Technical Activities.P. K. Barhai M.Sc. & Ph.D. (Dibrugarh University, India). He received the M.Sc. degree inphysics and the Ph.D. degree in Physical Sciences from Dibrugarh University, Dibrugarh, India,in 1970 and 1975, respectively. He is Vice Chancellor of the Birla Institute of Technology,Ranchi, India. He is also Dean, Sponsored Research & Collaborative Projects & Prof. andHead, Dept. of Applied Physics, B.I.T. Mesra, Ranchi, India. He is a Visiting Scientist at theUniversity of Duisburg, Duisburg, Germany, working on the development of NanocrystallineDiamond Films for Field-Emission Applications under an Indo-German Project funded underthe Indo-German Bilateral Cooperation on Science and Technology. 345 Vol. 6, Issue 1, pp. 336-345