Ultra-thin Body SOI MOSFETs<br />Prajon Raj Shakya<br />Master of Science in Electrical Engineering<br />Instructor: Dr. L...
SOI Technology	<br /><ul><li>Scaling requirements- improved performance.
Control over SCE (short-channel effect) and scaling device architecture.
Layered Si-Insulator-Si substrate in place of conventional Si.
SiO2, or SiGe: insulating material as BOX: improved performance  and reduced SCE.
New generation SOI as multiple gate, FinFETs, triple gate, GAA (Gate All Around).
UTB-SOI suppress SCE, scale gate length and reduce sub-threshold gate leakage current.
 For high density, high performance and low power  applications.</li></ul>Fig. 1: Schematic diagram of an UTB-SOI MOSFET [...
Performance of SOI devices<br />90% lower junction capacitance; near ideal sub-threshold swing; reduce device cross-talk; ...
UTB SOI MOSFET<br />SOI: PD-SOI (Partially depleted- SOI) and FD-SOI (Fully depleted-SOI)<br />FD-SOI: small and well-cont...
Effect on Inversion charge <br />Fig.2: Inversion charge density versus gate voltage for different buried oxide layer thic...
Effect of Body Doping<br /><ul><li>Effect of light channel doping causing shift in Vt w/o any SCE.
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Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics in Microelectronics with CAD

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This slide describes one of the technology n the field of semiconductor devices, Ultra thin body SOI (Silicon on Insulator) MOSFETs and its various uses and characteristics.

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  • Talking about the improved performance of the device :not susceptible to carrier freeze out and increased cross-talk as bulk Si devices
  • Threshold voltage fluctuation due to body thickness variation at UTB is approximately two times larger than at TBO under same body thickness fluctuation (1.5nm for 3 σ) but due to body thickness of UTB is 4 times thinner than TBO.
  • Fig. 2 shows the total inversion charge vs. gate voltage for three buried oxide thickness. Implies BOX : also has effect on sub-threshold slope of the deviceThicker he BOX layer, greater is the sub-threshold slope and even the driving current when the channel is scaled down to nano-scale size.Further; as from fig.3 effect of channel inversion charge on the Si body thickness as “Volume inversion”. ….shows that Si film thickness changes only the amount of sub-threshold inversion charge but has no effect on the strong inversion charge density that explains the “volume inversion” effect which can be used to control the sub-threshold leakage current of UTB-SOI MOSFET.
  • Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics in Microelectronics with CAD

    1. 1. Ultra-thin Body SOI MOSFETs<br />Prajon Raj Shakya<br />Master of Science in Electrical Engineering<br />Instructor: Dr. Long Que<br />Electrical Engineering Program<br />Louisiana Tech University<br />Ruston, LA 71272, USA<br />
    2. 2. SOI Technology <br /><ul><li>Scaling requirements- improved performance.
    3. 3. Control over SCE (short-channel effect) and scaling device architecture.
    4. 4. Layered Si-Insulator-Si substrate in place of conventional Si.
    5. 5. SiO2, or SiGe: insulating material as BOX: improved performance and reduced SCE.
    6. 6. New generation SOI as multiple gate, FinFETs, triple gate, GAA (Gate All Around).
    7. 7. UTB-SOI suppress SCE, scale gate length and reduce sub-threshold gate leakage current.
    8. 8. For high density, high performance and low power applications.</li></ul>Fig. 1: Schematic diagram of an UTB-SOI MOSFET [8]<br /> <br />
    9. 9. Performance of SOI devices<br />90% lower junction capacitance; near ideal sub-threshold swing; reduce device cross-talk; <br />Lower junction leakage -> low switching energy of the transistor<br /> No latch-up; Increased radiation hardness<br />Do not suffer from substrate reverse bias effects -> low-power devices.<br />Better electrostatic control: reduce S-D leakage and SCE.<br />Full dielectric isolation of the transistor <br />Reduced junction area<br />Impact ionization strongly balanced by thermal recombination.<br />Critical drawback as: floating body effects: body potential shifts –shift in V T , sub-threshold swing, and kink effects: minimized by thinner silicon.<br />
    10. 10. UTB SOI MOSFET<br />SOI: PD-SOI (Partially depleted- SOI) and FD-SOI (Fully depleted-SOI)<br />FD-SOI: small and well-controlled thickness channel; high series resistance<br />Higher trans-conductance and reduced floating body effects compared to PD-SOI.<br />Thin body thickness; reduced parasitic drain-to-body capacitance but drain field fringe increases DIBL (Drain Induced Barrier Lowering) and gate current worst at short-channel.<br />PDSOI: thicker body; high drain-body capacitance and degraded operating speed.<br />UTB concept evolve to control short-channel effect; along with TBO(Thin Buried Oxide)<br />UTB: Typical body thickness: 1/4th of gate length <br />While TBO: equivalent to gate length.<br />Variation of Vt due to variation of body thickness overcomes all other factors in UTB-SOI devices.<br />
    11. 11. Effect on Inversion charge <br />Fig.2: Inversion charge density versus gate voltage for different buried oxide layer thicknesses in undoped UTB-SOI MOSFETs<br />with the mid-gap gates for Vch = 0. [8]<br />Fig. 3: Inversion charge density versus gate voltage for different silicon film thicknesses in undoped UTB-SOI MOSFETs with the mid-gap gates for Vch = 0. [8]<br />
    12. 12. Effect of Body Doping<br /><ul><li>Effect of light channel doping causing shift in Vt w/o any SCE.
    13. 13. S,B and D: doped uniformly: DIBL and low-drain threshold rollofffs are defined with Vds=1V and 50mv, separately.
    14. 14. Substrate bias: 0 V to avoid threshold roll-off.
    15. 15. SCE reduced with high doping in silicon films (4-10nm) but high threshold voltage and low carrier mobility due to impurities.</li></ul>Fig.4: High drain threshold voltage roll-offs for SOI with varying <br />channel doping concentration [9]<br />
    16. 16. Effect of body doping (contd..)<br /><ul><li>Shows the simulated high-drain threshold voltage roll-offs in sub-0.15µm doped FDSOI MOSFETs for varying BOX thickness.
    17. 17. tBOX = 5nm has L min=38nm and increase with tBOX with L min=48nm for t BOX=100nm and 200nm.
    18. 18. S/D lateral field coupling in the BOX does not increase with BOX thickness after the </li></ul>tBOX is 2 times larger than the channel length of the device with 100mv threshold roll-off.<br />Fig.5: High drain threshold voltage rol-loffs for doped FDSOI with different <br />BOX thicknesses [9]<br />
    19. 19. Effect on Mobility<br /><ul><li>Increases with advancement in UTB SOI.
    20. 20. Limit of deca-nm regime.
    21. 21. 4-point method used to evaluate for µeffthickness from 44.5nm to 0.9nm.
    22. 22. Degradation of mobility below 3nm: due to influence of thickness/ surface roughness.</li></ul>Fig.6: Electron mobility vs. Ninv for body thicknesses from tSi=44.5nm down to 0.9nm and universal mobility after [10]<br />
    23. 23. Effect on Mobility (contd..)<br /><ul><li>Except for tSOI of 2.3nm; mobility – higher than universal curve of conventional (100) pMOSFETs.
    24. 24. Mobility degradation starts after 2.7nm
    25. 25. Mobility in DG-UTB MOSFET is higher than SG-UTB MOSFET.</li></ul>Fig.7: µeff – Ninvcharactersistics of (110) pMOSFETs at 300K [11] <br />
    26. 26. Conclusion<br />Different types of SOI and UTB-SOI as improvement of performance.<br />Various effects as of body doping, mobility enhancement and degradation and inversion charge.<br />Presents the concept of UTB-SOI in terms of device scaling with improved performance.<br />Further, various UTB-SOI as DG, SG, Fin-Fet, GAA and others are being developed for the better performance on various perspectives.<br />UTB-SOI with the adoption of high-k/metal technique are also being developed that acts on the performance of limitation of mobility.<br />Applications in high voltage and Smart Power ckt, RF ckt, Si-based optoelectronic devices, MEMS (Micro Electro Mechanical Systems), back-side illuminated image sensors etc.<br />
    27. 27. References<br />[1] B. G. Streetman and S. Banerjee, Solid State Electronic Devices, 5th ed. New Jersey: Prentice Hall, 2000.<br />[2] B.-Y. Nguyen, G. Celler, and C. Mazuré, “A Review of SOI Technology and its Applications,”Journal of Integrated Circuits and Systems, vol. 4, no.4, pp. 51-54, 19th August 2009.<br />[3] E. Sangiorgi, N. Barin, M. Braccioli, and C. Fiegna, “32nm Technology node Double-Gate SOI MOSFET using SiO2 gate stacks,” International Workshop on Nano CMOS, 2006, pp.38-42, Jan. 30 2006-Feb. 1 2006.<br />[4] A. Griffoni, S. Thijs, C. Russ, D. Tremouilles, D. Linten, M. Scholz, E. Simoen, C. Claeys, G. Meneghesso, and G. Groeseneken, “Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs,” IEEE Transactions on  Device and Materials Reliability, vol.10, no.1, pp.130-141, March 2010.<br />[5] C. Yang-Kyu, K. Asano, N. Lindert, V. Subramanian, K. Tsu-Jae, J. Bokor, and H. Chenming, "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," IEEE Electron Device Letters, vol. 21, pp. 254-255, 2000.<br />[6] S. A. Vitale, P. W. Wyatt, N. Checka, J. Kedzierski and C. L. Keast, "FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics," Proceedings of the IEEE , vol.98, no.2, pp.333-342, Feb. 2010.<br />[7] Y. Fu-Liang, H. Jiunn-Ren, and L. Yiming, "Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices," IEEE Custom Integrated Circuits Conference, 2006 (CICC '06), pp. 691-694, Sept. 2006.<br />[8] J. He, X. Zhang, G. Zhang, M. Chan and Y. Wang, "A carrier-based analytic model for undoped (lightly doped) ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs," 7th International Symposium on  Quality Electronic Design, 2006. (ISQED '06), pp.6 pp.-132, 27-29 March 2006.<br />[9] W. –Y. Lu, and Y. Taur, "Effect of Body Doping on the Scaling of Ultrathin SOI MOSFETs," International Conference on Simulation of Semiconductor Processes and Devices, 2006, pp.294-297, 6-8 Sept. 2006.<br />[10] M. Schmidt, M.C. Lemme, H.D.B. Gottlob, H. Kurz, F. Driussi, and L. Selmi, "Mobility extraction of UTB n-MOSFETs down to 0.9 nm SOI thickness," 10th International Conference onUltimate Integration of Silicon, 2009 (ULIS 2009), pp.27-30, 18-20th March 2009.<br />[11] T. Hiramoto, G. Tsutsui, K. Shimizu and M. Kobayashi, "Transport in ultra-thin-body SOI and silicon nanowire MOSFETs," InternationalSemiconductor Device Research Symposium, 2007, pp.1-2, 12-14 Dec. 2007. <br />
    28. 28. Thank you!!! <br />Any questions??<br />

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