EMBEDDED SYSTEMS 2&3

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EMBEDDED SYSTEMS 2&3

  1. 1. <ul><li>Microcontrollers – Internal Architecture </li></ul>
  2. 2. A Comparison of MCS51 Family members Comparisons of various MicroControllers in MCS51 Series
  3. 3. An Introduction to AT89C51 MicroController <ul><li>4 K Bytes ROM </li></ul><ul><li>128 Bytes RAM </li></ul><ul><li>Four 8-bit I/O Ports </li></ul><ul><li>Two 16 Bit Timers </li></ul><ul><li>Serial Interface </li></ul><ul><li>64 K External Code Memory Space </li></ul><ul><li>64 K External Data Memory Space </li></ul><ul><li>Boolean processor (operates on single bits) </li></ul><ul><li>210 Bit Addressable Locations </li></ul><ul><li>4 Microseconds Multiply / Divide </li></ul>AT89C51 Basic Features
  4. 4. An Introduction to AT89C51 ... Its Internal Architecture C51 Internal Architecture
  5. 5. An Introduction to AT89C51 ... Its Pin outs AT89C51 Pinouts Diagram
  6. 6. An Introduction to AT89C51 ... Pinouts Description A Brief Description of Pinouts of AT89C51 <ul><li>Pins 1-8 : </li></ul><ul><li>Pins 1 through 8 are the pins of Port 1 . Port 1 is a dedicated I/O port; so these pins are available for interfacing external devices as required. No alternate function is assigned to these pins. </li></ul><ul><li>Pin 9 : </li></ul><ul><li>Pin Number 9 is the system RESET ( RST ) of CPU of AT89C51. AT89C51 is reset by holding RST high for at least two machine cycles and then returning it low. The Reset may be manually activated using a switch, or may be activated upon power-up using RC network. After a system reset, Program Counter is loaded with 0000H. When RST returns low, program execution begins at the first location in code memory at address 0000H. The contents of on-chip RAM are not affected by a reset operation. </li></ul>...continued
  7. 7. An Introduction to AT89C51 ... Pinouts Description A Brief Description of Pinouts of AT89C51 … continued Below are the RC networks connected with RST pin:
  8. 8. An Introduction to AT89C51 ... Pinouts Description <ul><li>Pins 10-17 : </li></ul><ul><li>Pins’ numbers 10 through 17 constitute Port 3 which is a dual-purpose port. As well as general purpose I/O, these pins are multifunctional with each having an alternate purpose related to special features of C51. </li></ul><ul><li>These features along with pins are summarized in the coming table : </li></ul><ul><li> </li></ul>A Brief Description of Pinouts of AT89C51 … continued ...continued
  9. 9. An Introduction to AT89C51 ... Pinouts Description A Brief Description of Pinouts of AT89C51 … continued Symbols followed by Pound Sign(#) are “Low Enable”
  10. 10. An Introduction to AT89C51 ... Pinouts Description <ul><li>Pins 18-19 : </li></ul><ul><li>Pins’ numbers 18 and 19 comprise the inputs of crystal to be connected to the on-chip oscillator of AT89C51. Two Stabilizing capacitors of 30 pF each are also required. </li></ul><ul><li>Pin 20 : </li></ul><ul><li>It is the common ground of 89C51 and accompanying networks. </li></ul><ul><li>Pins 21-28 : </li></ul><ul><li>Pins 21 through 28 are of Port 2 . </li></ul><ul><li>Port 2 is a also a dual purpose port. It can serve as a general purpose I/O port or as the high byte of the address bus for designs with external code memory or more than 128 bytes of data memory. </li></ul><ul><li> </li></ul>A Brief Description of Pinouts of AT89C51 … continued
  11. 11. An Introduction to AT89C51 ... Pinouts Description <ul><li>Pin 29 and Pin 31 : </li></ul><ul><li>These pins are used in conjunction with external code memory being used or else. On Pin number 29 is a control signal PSEN# ( Program Store Enable ) that enables external code (Program) memory. It is usually connected to an EEPROMs Output Enable </li></ul><ul><li>(OE#) pin to permit reading of program bytes. Pin 31 i.e. EA# ( External Access ) is either tied high (+5V) or low (ground). If high, the C51 executes programs from internal ROM otherwise from external code memory (and then PSEN# comes into play). </li></ul><ul><li>Pins 32 - 39 and Pin Number 30: </li></ul><ul><li>Pins 32 through 39 make up Port 0 . Port 0 ,in addition to being </li></ul>A Brief Description of Pinouts of AT89C51 … continued ...continued
  12. 12. An Introduction to AT89C51 ... Pinouts Description used as an I/O port, has the capacity to act as multiplexed data and address bus. The discrimination of data and address is provided through ALE ( Address Latch Enable ) which is Pin number 30 . A Brief Description of Pinouts of AT89C51 … continued
  13. 13. An Introduction to AT89C51 ... Its RAM AT89C51 RAM
  14. 14. An Introduction to AT89C51 ... Its SFRs Special Function Registers ( SFR ) of C51
  15. 15. An Introduction to AT89C51 ... SFRs description A Brief Description of SFR s of C51 <ul><li>Program Control Register … PSW </li></ul><ul><li>( P rogram S tatus W ord) </li></ul><ul><li>General Purpose Registers … ACC ( ACC umulator) and B Registers </li></ul><ul><li>Ports’ Registers … P0 , P1 , P2 and P3 </li></ul><ul><li>Data Flow Register … DPH and DPL or DPTR (the only 16 bit register) ( D ata P oin T e R </li></ul><ul><li>… addressable as 16 bit) </li></ul>
  16. 16. An Introduction to AT89C51 ... SFRs description <ul><li>Stack Operation Register … SP ( S tack P ointer) </li></ul><ul><li>Power Control Register … PCON ( P ower CON trol) </li></ul><ul><li>Timer/Counter Registers … TCON ( T imer CON trol) , </li></ul><ul><ul><ul><ul><ul><li>TMOD ( T imer MOD e), </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Timer #0 Registers TL0 & TH0 </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Timer #1 Registers TL1 & TH1 </li></ul></ul></ul></ul></ul><ul><li>Serial Interface Registers … SCON ( S erial CON trol) </li></ul><ul><ul><ul><ul><ul><li> SBUF ( S erial BUF fer) </li></ul></ul></ul></ul></ul>A Brief Description of SFR s of C51 … continued
  17. 17. An Introduction to AT89C51 ... SFRs description <ul><li>Interrupt System Registers … IE ( I nterrupt E nable) </li></ul><ul><li> IP ( I nterrupt P riority) </li></ul>A Brief Description of SFRs of C51 … continued <ul><li>The incoming slides discusses SFRs in a little more detail: </li></ul>
  18. 18. SFRs description ... PSW PSW ( P rogram S tatus W ord) Symbol Address Meaning PSW Bit No P D0 H Even P arity Flag PSW.0 - D1 H Reserved Flag PSW.1 OV D2 H OV erflow Flag PSW.2 RS0 D3 H R egister Bank S elect #0 PSW.3 RS1 D4 H R egister Bank S elect #1 PSW.4 F0 D5 H F lag 0 for user apply PSW.5
  19. 19. SFRs description ... PSW PSW ( P rogram S tatus W ord) … continued Symbol Address Meaning PSW Bit No AC D6 H A uxiliary C arry Flag PSW.6 CY D7 H C arr Y Flag PSW.7
  20. 20. SFRs description ... ACC and B Registers ACC ( ACC umulator) & B Registers ACC ( ACC umulator) and B Registers are general purpose Registers; their combined use lies mostly in Arithmetic Instructions while ACC being used in most of the other instructions (like Logic and Program Flow Control Instructions) of C51 Instruction Set. Both registers are Bit-Addressable . ACC is at address E0 H while B Register is at address F0 H.
  21. 21. SFRs description ... Port Registers Ports’ Registers… P0, P1, P2 and P3 Ports’ Registers P0 for Port #0; P1 for Port #1; P2 for Port #2 and P3 for Port #3; are used in accordance with the functionality used in these ports. Writing data to any Port Registers causes an immediate transfer of the data to the respective port while reading data from any Port Register is analogues to reading the data from the respective physical port. All of the four registers are Bit-Addressable . P0 is at 80 H, P1 at 90 H, P2 at A0 H and P3 at B0 H.
  22. 22. SFRs description ... DPTR DPTR ( D ata P oin T e R ) Register DPTR is the only Register in AT89C51 which is accessible as 16 bit register. It is also byte addressable as DPL ( D ata P ointer L ow Byte) and DPH ( D ata P ointer H igh Byte). DPTR is mostly used in addressing blocks of data I.e. as a pointer for a large block of data in Instructions like MOVX . DPTR is Not-Bit-addressable
  23. 23. SFRs description ... SP Pushing data onto the stack increments the SP . Likewise, popping data from the stack, decrements the SP . If the application software does not re-initialize the SP , then register bank 1 (and perhaps 2 and 3) is not available, since this area of internal RAM is in stack. SP ( S tack P ointer) Register
  24. 24. SFRs description ... PCON PCON ( P ower CON trol) Register Symbol Meaning PCON Bit No IDL IDLe mode, set to active Idle mode PCON.0 PD P ower D own, set to active power down mode PCON.1 GF0 G eneral Purpose F lag bit 0 PCON.2 GF1 G eneral P urpose F lag bit 1 PCON.3 - Not Defined PCON.4 - Not Defined PCON.5
  25. 25. SFRs description ... PCON PCON ( P ower CON trol) Register … continued Symbol Meaning PCON Bit No - Not Defined PCON.6 SMOD Double Baud Rate Bit; when set Baud Rate is PCON.7 - doubled in Serial Port Modes 1,2 or 3. -
  26. 26. Timer/Counter Operation of AT89C51 Timer/Counter Operation & its Registers The Data Registers for the two timers are TL0 and TH0 for Timer #1 while TL1 and TH1 for the other one. TMOD and TCON control their operation and modes. There are four modes of operation of the two timers set by TMOD. A description of TMOD and TCON follows :
  27. 27. Timer/Counter Operation of AT89C51... TMOD Timer/Counter Operation & its Registers … continued TMOD : Symbol Meaning TMOD Bit No M0 Timer #0 M ode Select Bit # 0 TMOD.0 M1 Timer #0 M ode Select Bit # 1 TMOD.1 C/T# Timer #0 C ounter/ T imer (Low Enable) Select Bit TMOD.2
  28. 28. Timer/Counter Operation of AT89C51 ... TMOD Timer/Counter Operation & its Registers … continued TMOD Register : Symbol Meaning TMOD Bit No GATE Timer #0 GATE Bit , set, timer only rubs INT1 is high TMOD.3 M0 Timer #1 M ode Select Bit # 0 TMOD.4 M1 Timer #1 M ode Select Bit # 1 TMOD.5 C/T# Timer #1 C ounter/ T imer (Low Enable) Select Bit TMOD.6 GATE Timer #1 GATE Bit, set, timer only rubs INT1 is high TMOD.7
  29. 29. Timer/Counter Operation of AT89C51 ... Modes of Operation Timer/Counter Operation & its Registers … continued TMOD Register : M1 Mode Description M0 0 0 13 -bit T imer M ode 0 1 1 16 -bit T imer M ode 0 1 3 S plit T imer M ode; TL0 8-bit timer by its 1 - - mode bits, TH0 same except by - 0 2 8 -bit A uto- R eload M ode 1 - - timer 1 mode bits ,Timer 1 stopped -
  30. 30. Timer/Counter Operation of AT89C51 ... TCON Timer/Counter Operation & its Registers … continued TCON Register :
  31. 31. Timer/Counter Operation of AT89C51 ... Example An Example of Timer Operation ; A Program to generate 10 kHz Square wave on P1.0 ORG 0H MAIN: MOV TMOD,#02H ; 8-bit Auto-Reload-Mode MOV TH0,#-50 ; -50 reload value in TH0 SETB TR0 ; start timer LOOP: JNB TF0,LOOP ; wait for overflow CLR TF0 ; clear timer overflow flag CPL P1.0 ; toggle port bit SJMP LOOP ; repeat END
  32. 32. Serial Interface of C51 Serial Interface of C51 & its Registers <ul><li>The 89C51 include an on-chip serial port that can operate in several modes over a wide range of frequencies. The essential functions of the serial port is to perform parallel-to-serial data conversion for output data, and serial-to-parallel conversion for input data . The serial port features Full Duplex Mode (simultaneous transmission and reception of data). </li></ul><ul><li>Hardware access to the serial port is through TxD and RxD pins already described in previous section on “ Pinouts of 89C51 ”. </li></ul><ul><li>Two SFRs provide software access to serial port viz.., SBUF and SCON . SBUF at 99 H holds the serial data. </li></ul>
  33. 33. Serial Interface of C51 ... SCON Serial Interface of C51 & its Registers … continued SCON Register :
  34. 34. Serial Interface of C51 ... Modes of Operation Serial Interface of C51 & its Registers … continued Modes of SCON Register : 0 0 13 -bit T imer M ode 0 1 1 16 -bit T imer M ode 0 1 3 S plit T imer M ode; TL0 8-bit timer by its 1 - - mode bits, TH0 same except by - 0 2 8 -bit A uto- R eload M ode 1 - - timer 1 mode bits ,Timer 1 stopped - M1 Mode Description M0
  35. 35. Interrupt Mechanism of C51 Interrupt System of C51 & its Registers <ul><li> </li></ul><ul><li>An interrupt is the occurrence of a condition, an event, that causes a temporary suspension of a program while the condition is serviced by another program. </li></ul><ul><li>When an interrupt occurs and is accepted by the CPU, the main program is interrupted. The following actions occur: </li></ul><ul><li>The current instruction completes execution </li></ul><ul><li>The P rogram C ounter ( PC ) is saved on the stack </li></ul><ul><li>The current interrupt status is saved internally </li></ul><ul><li>The interrupts are blocked at the level of the interrupt </li></ul><ul><li>The PC is loaded with the vector address of the ISR </li></ul><ul><li>The ISR executes </li></ul>...continued
  36. 36. Interrupt Mechanism of C51 Interrupt System of C51 & its Registers … continued The ISR executes and takes in action in response to the interrupt. The ISR finishes with a RETI (return from interrupt) instruction. The retrieves the old value of the PC from the stack and restores the old interrupts status. Execution of the main program contains where it left. >> I nterrupt S ervice R outine ( ISR )is the program that deals with an interrupt. >> When an interrupt is accepted, the value loaded into PC is called the interrupt vector . It is the address of the start of ISR for the interrupting source.
  37. 37. Interrupt Mechanism of C51 Interrupt System of C51 & its Registers … continued <ul><li>There are five sources of interrupt in 89C51 . </li></ul><ul><li>TF0 and TF1 ( TCON register) are generated when the associated counter overflows </li></ul><ul><li>INT0# and INT1# (P3.2 and P3.3) constitute two external interrupts </li></ul><ul><li>RI and TI of SCON register </li></ul><ul><li>IE ( I nterrupt E nable register) at address A8 H is used to mask individual interrupts. </li></ul><ul><li>IP ( I nterrupt P riority) at address B8 H assigns different level of priorities to the above mentioned five interrupts of 89C51 . </li></ul>
  38. 38. Interrupt Mechanism of C51 ... Interrupt Vector Table Interrupt System of C51 & its Registers … continued Interrupt Source Symbol ISR Address Default Priority System Reset RST 00 H 0 (Highest) External Int. #0 IE0 03 H 1 Timer #0 TF0 0B H 2 External Int. #1 IE1 13 H 3 Timer #1 TF1 1B H 4 Serial Port Int. RI/TI 23 H 5 (Lowest)
  39. 39. Interrupt Mechanism of C51 ... IE Register Interrupt System of C51 & its Registers … continued IE Register :
  40. 40. Interrupt Mechanism of C51 ... IP Register Interrupt System of C51 & its Registers … continued IP Register :
  41. 41. Interrupt Mechanism of C51 ... Program Design Interrupt System of C51 & its Registers … continued Program Design using Interrupts : 02F H 000 H 030 H FFF H Main Program Reset and Interrupt Entry Points
  42. 42. Interrupt Mechanism of C51 ... External Interrupts Interrupt System of C51 & its Registers … continued External Interrupts : <ul><li>There are two sources of External ( Hardware ) Interrupts in case of 89C51 : </li></ul><ul><li>INT0# at P3.2 affects IE0 flag in TCON register. </li></ul><ul><li>INT1# at P3.3 affects IE1 flag in TCON register. </li></ul><ul><li>Moreover two t yp es of Interrupt Mechanisms exist. These are explained in coming slide : </li></ul>
  43. 43. Interrupt Mechanism of C51 ... Types of Interrupt Mechanisms Interrupt System of C51 & its Registers … continued Low-Level Activated IT1 = O (TCON) Negative-Edge Activated Interrupt IT1 = 1 (TCON) External Interrupt 1 is triggered ) by a detected low at the INTI if successive samples of INTI pin show a high in one cycle and low in the next, the interrupt request flag IEI in TCON is set. 12 oscillator periods low High for 1 cycle Low for 1 cycle. Types of Interrupt Mechanisms
  44. 44. Traffic Lights System Demonstration ... Block Diagram Case Study :: Discussion Traffic Lights System Demonstration Micro- Controller Buf- fer DataLines
  45. 45. <ul><ul><ul><ul><li>THANK YOU </li></ul></ul></ul></ul>Data Tranfer Instructions ... Data Movement Instructions

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