DVLSI CAT GUESS PAPER Page 1 of 1
CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING
Note: The inversion of any signal A is repr...
Page 2 of 2
19. To minimize the power consumption in CMOS
1. Increase the load capacitance, voltage and
reduce the operati...
Page 3 of 3
3. doping of the emitter is much larger than the
doping of the base
4. None of the above
41. In collector-emit...
Page 4 of 4
Section II : Question No 61 to 80 weightage 2 Marks each (40 Marks)
61. To which gates are the following circu...
Page 5 of 5
1. It is a sequential circuit.
2. It is combinational circuit.
3. It can be sequential or combinational depend...
Page 6 of 6
71.
We have a 4 bit ripple carry adder. If the full adder block has the following delay properties:
Ai Si=6ns
...
Page 7 of 7
77.
The above circuit is equivalent to
1. T Flip flop
2. D flip flop with preset
3. D flip flop with clock ena...
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DVLSI Guess paper for CDAC CCAT Jun- Jul 2013 Enterence examination

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DVLSI Guess paper for CDAC CCAT Jun- Jul 2013 Enterence examination

  1. 1. DVLSI CAT GUESS PAPER Page 1 of 1 CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING Note: The inversion of any signal A is represented here as /A or A' Section I : Question No 1 to 60 weightage 1 Mark each (60 Marks) 1. 8085 is 1. Big endian 2. Little endian 3. Depends on instruction 4. None of the above 2. 8 bit computer means 1. 8 bit data line and any bit address line 2. 8 bit address line and any bit data line 3. 8 bit data and address line 4. not depend on data and address line 3. Recovery and Removal time is related to 1. Synchronous input 2. Asynchronous input 3. both inputs 4. None of the above 4. Slack is 1. Arrival Time – Recovery Time 2. Recovery Time - Settling time 3. Required time - Arrival Time 4. Arrival Time – Required Time 5. Clock Skew is 1. clock arrives at different components at different time 2. clock arrives at same component at different time 3. clock arrives at different component at same time 4. None of the above 6. 5 bit Johnson counter will have 1. 16 states 2. 32 states 3. 8 states 4. 10 states 7. For Basic NOR latch circuit 1. both input should not be 1 2. both input should not be 0 3. both input should be 1 4. None of the above 8. A master-slave flip-flop has the characteristic that 1. change in the input is immediately reflected in the output 2. change in the output occurs when the state of the slave is affected 3. change in the output occurs when the state of the master is affected 4. both the master and slave states are affected at the same time 9. The band gap of silicon at room temperature is 1. 1.3 eV 2. 0.7 eV 3. 1.4 eV 4. 1.1 eV 10. A digital-to-analog converter with a full-scale output voltage of 3.5V has a resolution close to 14mV. Its bit size is 1. 4 2. 8 3. 16 4. 12 11. The 8085 assembly language instruction that stores the content of H and L registers into the memory location 2050H and 2051H, respectively is 1. SPHL 2050H 2. SPHL 2051H 3. SHLD 2050H 4. STAX 2050H 12. Consider the following statements S1 and S2. S1: The Threshold voltage (VT) of MOS Transistor decreases with increase in gate oxide thickness S2: The Threshold voltage (VT) of MOS Transistor decreases with increase in substrate doping concentration Which one of the following is correct? 1. Both S1 and S2 are TRUE 2. Both S1 and S2 are FALSE 3. S1 is FALSE and S2 is TRUE 4. S1 is TRUE and S2 is FALSE 13. The impurity commonly used for realizing the base region of a silicon n-p-n transistor is 1. Boron 2. Phosphorous 3. Gallium 4. Indium 14. A MOS transistor made up of p substrate is in the accumulated mode. The dominant charge in the channel is due to the presence of 1. positively charged ions 2. negatively charged ions 3. holes 4. electrons 15. Match item from Group 1 with Group 2 Group 1 Group 2 1. FM P. Slope Detector 2. DM Q. m-law 3. PSK R. Envelope detector 4. PCM S. Capture Effect T. Hilbert Transform U. Matched filter 1. 1-T, 2-P, 3-U, 4-S 2. 1-S, 2-P, 3-U, 4-Q 3. 1-S, 2-U, 3-P, 4-T 4. 1-U, 2-R, 3-S, 4-Q 16. The address in Program Counter (PC) register of the 8086 after rebooting is 1. 0000FH 2. 00000H 3. FFFF0H 4. FFFFFH 17. Latch up is 1. caused due to parasitic thyristor 2. caused due to parasitic transistor 3. caused due to burn out 4. None of the above 18. Consider the following statement S1 and S2 S1: NAND gate have more symmetric high-to-low and low-to-high delay S2: NOR is faster than NAND 1. Both S1 and S2 are FALSE 2. Both S1 and S2 are TRUE 3. S1 is FALSE and S2 is TRUE 4. S1 is TRUE and S2 is FALSE DVLSI CCAT GUESS PAPER for Jun-Jul 2013
  2. 2. Page 2 of 2 19. To minimize the power consumption in CMOS 1. Increase the load capacitance, voltage and reduce the operating frequency 2. Increase the load capacitance and decrease the voltage and operating frequency 3. Reduce the load capacitance, voltage and operating frequency 4. Increase the load capacitance, voltage and operating frequency 20. To avoid charge sharing problem 1. Load capacitance should be larger than input capacitance 2. Load capacitance should be smaller than input capacitance 3. Load and input capacitance should be equal 4. None of the above 21. Hold time can be reduced to zero by 1. By adding buffer inside the FLOP on output side 2. By adding buffer in data path 3. both 1 and 2 4. None of the above 22. To not to loose current in substrate connect substrate in 1. NMOS to VDD and PMOS to GND 2. NMOS and PMOS to VDD 3. NMOS and PMOS to GND 4. NMOS to GND and PMOS to VDD 23. The difference between MOSFET and BJT is 1. MOSFET is current controlled and BJT is voltage controlled 2. MOSFET is voltage controlled and BJT is current controlled 3. MOSFET can be current or voltage controlled and BJT is voltage controlled 4. None of the above 24. Latch and FF are 1. Latch is level sensitive and FF is edge sensitive 2. Latch is edge sensitive and FF is level sensitive 3. Latch and FF both are edge sensitive 4. Both are level sensitive 25. Output of the Moore is depend on 1. current state and input 2. output and current state 3. current state only 4. input only 26. For synchronization in Clock domain crossing, we use 1. FIFO 2. cascaded Flop 3. Handshaking signals 4. All of the above 27. FPGA stands for 1. Field Programmable Gate Array 2. For Programming Gate in Abundance 3. Field Programmable Gated Array 4. None of the above 28. Processor address Cache memory using 1. Logical Address 2. Virtual Address 3. Physical Address 4. All of the above 29. What is Avalanche breakdown? 1. It is caused due to thermally generated carriers 2. It is caused due to reverse voltage applied at the junction 3. It is caused due to high forward current. 4. It is caused duet to high reverse current. 30. How many 2:1 mux will be needed to make one 8:1 mux? 1. 9 2. 8 3. 6 4. 7 31. Shift left by 1 can be achieved by 1. Adder 2. FLIP-FLOP circuit 3. Mux 4. All of the above 32. Drift current is 1. transport of charges due to non uniform concentration gradient 2. transport of charges due to influence of an electric field 3. Both of the above 4. None of the above 33. The tri-state means 1. Sinking of the current 2. Sourcing of the current 3. Neither sinking nor sourcing current 4. Not fully sinking or sourcing current 34. Thermistors has 1. Positive coefficient of the resistance 2. Negative coefficient of the resistance and much smaller than metal 3. Negative coefficient of the resistance 4. Positive coefficient of the resistance and much smaller than metal 35. Recombination means 1. electron moves from higher conduction band to lower conduction band 2. electron moves from valence band of one atom to valence band of the other atom 3. electron moves out of the valence band 4. electron moves from conduction band to valence band of the same atom 36. Total current (I) flowing through the a pn junction is 1. Idiifusion + I drift 2. Idiffusion – Idrift 3. Idrift – Idiffusion 4. Idrift 37. Diodes which are designed with adequate power- dissipation capability to operate in the breakdown region are known as 1. Avalanche diode 2. Breakdown diode 3. Zener Diode 4. All of the above 38. Avalanche multiplication causes due to 1. high voltage + high doping 2. high voltage + low doping 3. low voltage + low doping 4. low voltage + high doping 39. The diode which shows negative and positive resistance during forward voltage is known as 1. Zener diode 2. Tunnel Diode 3. Avalanche diode 4. None of the above 40. In a commercial transistor 1. doping of the base is much larger than the doping of the emitter 2. doping of the base and emitter is same DVLSI CAT GUESS PAPER
  3. 3. Page 3 of 3 3. doping of the emitter is much larger than the doping of the base 4. None of the above 41. In collector-emitter configuration 1. collector junction is forward biased and emitter junction is reverse biased 2. both junctions are reverse biased 3. both junctions are forward biased 4. collector junction is reverse biased and emitter junction is forward biased 42. The failure of the transistor to respond to the trailing edge of the driving pulse is due to 1. saturation charges of excess minority carriers stored in the base 2. saturation charges of excess majority carriers stored in the base 3. Both 1 and 2 4. None of the above 43. Which logic family has noise immunity low? 1. CMOS 2. TTL 3. ECL 4. RTL 44. Which logic family has fastest working frequency 1. RTL 2. TTL 3. HTL 4. DTL 45. For fixed drain-to-source voltage and fixed gate voltage, the factor that influence the level of drain current are 1. dielectric constant of the gate insulator 2. the carrier mobility 3. the channel width 4. All of the above 46. Width of Transistor can be defined as 1. the distance between drain to source 2. the distance between gate to source 3. the total length of drain 4. None of the above 47. For equal fall and rise time of CMOS inverter 1. width of NMOS < the width PMOS 2. width of NMOS > the width PMOS 3. width of NMOS = the width PMOS 4. None of the above 48. Body effect in CMOS is the voltage difference between 1. drain and substrate 2. gate and substrate 3. source and substrate 4. source and gate 49. The dynamic dissipation is due to A. Current pulse from VDD to VSS while switching B. Current required for charging and discharging of the output capacitive load C. Current flowing from VDD to output capacitive load D. Current flowing from Vss to output capacitive load 1. only A is correct 2. only A and B is correct 3. all A B C D are correct 4. only A B C are correct 50. Find out the odd one 1. BiCMOS 2. CMOS 3. Clocked CMOS 4. pass Transistor logic 51. A half adder has 1. one input and one output 2. two input and one output 3. two input and two output 4. three input and two output 52. Which of the following do not have race problem? 1. Master-slave flip-flop 2. T flip-flop 3. D flip-flop 4. All of the above 53. For the logic circuit the output Y is equal to 1. /(ABC) 2. /A + /B + /C 3. ABC 4. AB + /(CB) 54. In sequential circuit the output at any instant of time depends on 1. only on the inputs at that time. 2. on past output and present input 3. only on past and present inputs 4. only on the past outputs 55. The decimal equivalent of the binary number 101011011011 is 1. 2779 2. 2679 3. 2769 4. 2659 56. If state machine with 9 states is one hot encoded, it will require 1. 4 flip-flop 2. 6 flip-flop 3. 9 flip-flop 4. 3 flip-flop 57. Which one of the following has maximum jitter in the output 1. Clock buffer output 2. oscillator module 3. Crystal oscillator 4. PLL 58. An P type semiconductor has excess of 1. electron 2. hole 3. impurities 4. none 59. Number of transistors in single bit DRAM are 1. 2 2. 4 3. 6 4. 1 60. In a microprocessor wait state are used to 1. make processor wait during interrupt processing 2. make the processor during power down mode 3. interface the processor with slow peripherals 4. make the processor wait during DMA operations DVLSI CAT GUESS PAPER
  4. 4. Page 4 of 4 Section II : Question No 61 to 80 weightage 2 Marks each (40 Marks) 61. To which gates are the following circuits functionally equivalent to? (a and b are inputs) 1. AND, OR, INVERTER, XOR 2. OR, AND, XOR, INVERTER 3. AND, INVERTER, XOR, OR 4. AND, OR, XOR, INVERTER 62. What is the function of following circuit? (c is carry out, s is sum) 1. A/2 + B/2 2. B/2 + A 3. B + A/2 4. to count the total number of 1’s in the inputs A and B 63. What is the minimum number of flip flops required to design a Finite state machine which detects the sequence 10110? 1. 3 2. 5 3. 4 4. 6 64. If A?B=C and C?A=B then what is the boolean operator ‘?’ 1. NAND 2. XNOR 3. XOR 4. NOR 65. c s sc c s sc Full Adder Full Adder Full Adder Full Adder Y2 Y1 Y0 B2 B1 B0 A2 A1 A0 1 b a b a b a b 1 0 0 1 0 0 0 1 1 1 DVLSI CAT GUESS PAPER
  5. 5. Page 5 of 5 1. It is a sequential circuit. 2. It is combinational circuit. 3. It can be sequential or combinational depending on inputs. 4. It is both sequential as well as combinational circuit. 66. A power system is providing 200 VAC at 25 A. The phase angle between current and voltage is 25 o . Assume sin(25) = 0.4226, & cos(25) = 0.906. What is the true power used by the system? 1. 2,113 W 2. 11,831W 3. 5,517 W 4. 4,531 W 67. A communication channel has 8 Mbps line rate (link speed). The packets on this channel is sent serially, one bit at a time. Packets have header overhead of 6-bytes and 92 bytes of data. The inter packet gap is 2 bytes. What is the maximum bandwidth (in Mbytes per sec) you’ll get out of this channel? 1. 0.52 2. 0.92 3. 1.0 4. 0.72 68. Refer to Figure D. A voltage level of 20 V is measured at the output of the power supply with no load attached. Which of the following is the probable cause? 1. R1 shorted 2. C1 open 3. D1 shorted 4. D3 open 69. A 500MHZ non-pipelined machine takes 3 clock cycles for every instruction. You wish to make sure that your program completes in less than 15 microseconds. How many instructions should you limit your program to? 1. 2500 2. 5000 3. 7500 4. 4500 70. Which gate is implemented above show circuit? 1. AND 2. NOR 3. EXOR 4. NAND DVLSI CAT GUESS PAPER
  6. 6. Page 6 of 6 71. We have a 4 bit ripple carry adder. If the full adder block has the following delay properties: Ai Si=6ns Bi Si=6ns Ai Ci=3ns Bi Ci=3ns Ci-1 Si=3ns Ci-1 Ci=2ns What is the worst case propagation delay for the 4 bit ripple carry adder? 1. 24 ns 2. 12 ns 3. 20 ns 4. 10 ns 72. The initial contents of 4-bit serial-in-parallel-out, right-shift, shift register shown in fig is 0110. After 3 clock cycles are applied, the contents of shift register will be 1. 0000 2. 0101 3. 1010 4. 1111 73. You are given a 100MHz clock source. How many flip-flops will be required to generate 12 MHz clock from 100MHz? 1. 5 2. 4 3. 6 4. 3 74. How many 1-bit full adders will be required to implement 4X+1 where X is 4-bit input? 1. 2 2. 0 3. 3 4. 1 75. How many flip flops will be required to convert a 4 bit up counter into a 4 bit down counter? 1. 1 2. 2 3. 0 4. 3 76. Consider the design of a “one-hot” counter that outputs the following sequence: 0001,0010,0100,1000,0001………..What is the minimum number of flip flops that will be required to construct this counter using only counter and decoder elements? 1. 4 2. 2 3. 3 4. 5 Serial in Clock 0 011 DVLSI CAT GUESS PAPER
  7. 7. Page 7 of 7 77. The above circuit is equivalent to 1. T Flip flop 2. D flip flop with preset 3. D flip flop with clock enable 4. T flip flop with clock enable 78. Which gate is implemented in the below CMOS circuit? 1. XOR 2. AND 3. NAND 4. NOR 79. In the following circuit, the 8x3 bit SRAM starts with all zeros stored in its memory. The up counter is enabled and counts normally. Assume that the clock period is long compared to any SRAM timing constraints. What value will stored at location 5 of the SRAM after 64 clock cycles. 1. 5 2. 4 3. 0 4. 6 80. The below circuit is equivalent to (The clock to out propagation delay of the flip-flop is 1 ns(Max) and the propagation delay of the inverter as 2 ns(max)). 1. A single D flip-flop with large propagation delay (clock to out) 2. 2-bit counter. 3. A single D flip-flop which works on both the edges. 4. A T flip-flop with clock enable OutD Flip Flop Clock In D Flip Flop D Flip Flop Clock Clear Input Output DVLSI CAT GUESS PAPER

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