Cloud Computing for Chip Design“What Can FPGA Designers Do With     Personal Data Centers?”   Harnhua Ng, Plunify Pte Ltd ...
Agenda     § FPGA Design Data Center        § Specific Areas of Note     § FPGA Timing Closure        § Current Approa...
“Personal Data Center for FPGA Design”                         Simulation                                      Routing/   ...
Confidentiality, Ease of UsePrecedents: Foundry <-> foundry customer interaction                                          ...
FPGA Timing ClosureCurrent Limitations              Costly Delays                                  “Timing Experiments”   ...
Cloud Closure            Data Center Approach                                    §  Run iterations in parallel           ...
Design – OR1200 32-bit processor core                                        § 32-bit RISC                               ...
Target Chip & Software     § Altera Stratix III L50        § 65-nm technology        § Logic elements: 47.5K        § ...
Timing Problem              Timing Aspect    Slack (ns)            Worst Setup Time     -0.519Page § 9
Cloud Approach               Run in Parallel                                      •  Calculate various parameters         ...
Result: Timing Solutions Found             Set    Timing Aspect     Slack (ns)             19    Worst Setup Time     0.09...
EDAxtend PlatformComplete design tool flow                                        Cloud Test                              ...
Next Steps   §  Support more FPGA processes      § IP cores      § Complementary tasks e.g. multi-vendor flows   §  Ex...
Test Drive & Feedback   §  Web account: register at www.plunify.com   §  Desktop plugin: contact us at      tellus@pluni...
Cloud-Accelerated FPGA Design   §  Secure, easy to use      § Demo: Timing closure   §  Shorten Time-To-Market   §  Re...
Upcoming SlideShare
Loading in...5
×

What Can FPGA Designers Do With Personal Data Centers?

1,406
-1

Published on

These are the slides presented by Plunify during the event, "Accelerate Time-To-Market Using Cloud Computing", held on 14th Oct 2011, organized by the Singapore Semiconductor Industry Association.

Published in: Technology, Design
0 Comments
2 Likes
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total Views
1,406
On Slideshare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
Downloads
9
Comments
0
Likes
2
Embeds 0
No embeds

No notes for slide

What Can FPGA Designers Do With Personal Data Centers?

  1. 1. Cloud Computing for Chip Design“What Can FPGA Designers Do With Personal Data Centers?” Harnhua Ng, Plunify Pte Ltd October 14, 2011
  2. 2. Agenda § FPGA Design Data Center § Specific Areas of Note § FPGA Timing Closure § Current Approach § Demonstration § Cloud Approach § Going ForwardPage § 2
  3. 3. “Personal Data Center for FPGA Design” Simulation Routing/ SynthesisPage § 3
  4. 4. Confidentiality, Ease of UsePrecedents: Foundry <-> foundry customer interaction Audited Security Standards §  AES encryption §  SSL transmission §  Asymmetric keys •  Secure and Encrypted End-to-End Transfers •  Plugins to Existing Tools •  Distributed File Uploads / DownloadsPage § 4
  5. 5. FPGA Timing ClosureCurrent Limitations Costly Delays “Timing Experiments” §  Case 1: Miss timing by a bit §  Change a setting, repeat till successful §  Case 2 : Timing is way off §  Back to drawing board – path restructuring, pipelining etc. N hrs per iteration Drawbacks M iterations -  Takes time to re-iterate one at a time -  Usually at a later design stage Total: N x M hours -  Randomness: *Fingers crossed* -  Requires communication between “tools people” and “design people” ≈ days, weeks…Page § 5
  6. 6. Cloud Closure Data Center Approach §  Run iterations in parallel §  Save time wasted from waiting for each iteration §  Save time on re-engineering the design §  Use generated results from iterations to troubleshoot better X servers N hrs per iteration Total: N hoursPage § 6
  7. 7. Design – OR1200 32-bit processor core § 32-bit RISC § Harvard architecture § 5-stage pipeline § Virtual memory § Basic DSP capabilities § Implemented in various commercial ASICs & FPGAsPage § 7
  8. 8. Target Chip & Software § Altera Stratix III L50 § 65-nm technology § Logic elements: 47.5K § Package: F780 § Speed Grade: Commercial 2 § Altera Quartus II § Version 10.0 SP1Page § 8
  9. 9. Timing Problem Timing Aspect Slack (ns) Worst Setup Time -0.519Page § 9
  10. 10. Cloud Approach Run in Parallel •  Calculate various parameters §  “Seeds” §  Placement optimizations §  Routing optimizations §  Register-to-register timing §  Effort levels §  Schedule and run in parallel Multiple parallel runsPage § 10
  11. 11. Result: Timing Solutions Found Set Timing Aspect Slack (ns) 19 Worst Setup Time 0.093 26 Worst Setup Time 0.011Page § 11
  12. 12. EDAxtend PlatformComplete design tool flow Cloud Test Cloud Explore Cloud Closure IP Libraries Place Timing/ Design Design Simulate Synthesis and Power Rule Entry Route Analysis Checking •  Aldec Riviera Pro •  Altera Quartus II •  Magma •  Mentor Graphics •  Simucad Modelsim•  Sigasi HDT •  Altera Quartus II •  Altera Quartus II•  TransEDA Cloud Compile - Cloud CollabPage § 12
  13. 13. Next Steps §  Support more FPGA processes § IP cores § Complementary tasks e.g. multi-vendor flows §  Extend features to broader EDA tasks § E.g. Simulator, DFM, Verification toolsPage § 13
  14. 14. Test Drive & Feedback §  Web account: register at www.plunify.com §  Desktop plugin: contact us at tellus@plunify.com §  What would you like to see in the cloud?Page § 14
  15. 15. Cloud-Accelerated FPGA Design §  Secure, easy to use § Demo: Timing closure §  Shorten Time-To-Market §  Reduce overheads and development costsPage § 15
  1. A particular slide catching your eye?

    Clipping is a handy way to collect important slides you want to go back to later.

×