OMEGA PROJECT : Validation test report

TEST REPORT
(OMEGA PROJECT)
project n° 28599

ref.: XXXXX

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Reference : / 99

Date :

Issue : 01

Written by : EMC group

Visa :

Approved by ...
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Edition

Date

Description

01

XXXXX

New document File

ref.: XXXXX

Modificatio...
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REFERENCE’S DOCUMENTS

Reference

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Title

Origin

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CONTENTS

1.

PURPOSE ...............................................................
OMEGA PROJECT : Validation test report
4.4.2

Functional configurations .....................................................
OMEGA PROJECT : Validation test report

7.

ANNEXE : ........................................................................
OMEGA PROJECT : Validation test report

ABREVIATIONS LIST

BMC

Backplane Mother Board

CAD

Computer Aided Design

EMC

E...
OMEGA PROJECT : Validation test report

1. Purpose
This document is the final tests report which is owed in the framework ...
OMEGA PROJECT : Validation test report

2. Recall of the validation objectives
The main objective of this validation :


...
OMEGA PROJECT : Validation test report

3. Recall of the user's requirements to be validated
The User’s requirements valid...
OMEGA PROJECT : Validation test report

4. Validation process
4.1 Testing equipments


Specific avionics test benches and...
OMEGA PROJECT : Validation test report
-

at each end of clock signal nets

-

at each end of control, data and address si...
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4.2.3 Synthesis of Results acquired with a normally routed CPU board
The details o...
OMEGA PROJECT : Validation test report
a) Clock signal

Signal

Test

Ref

name

point

page

Simul

Meas

IC72-11

80

?
...
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?:

can't be estimated (not found in the .wave file)
appreciable differences betwee...
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b) Control signal

Signal

Test

Ref

name

point

page

Simul

Meas

diff (%)

Si...
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?:

can't be estimated (not found in the .wave file)

X:

not measured
appreciable ...
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c) Data and address signal

Signal

Test

Ref

Tr (ns)

name

point

page

Simul

...
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d) Investigations
The differences noted between simulation and measurement results...
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The multiple oscillations present at the signal low level seem to be due to the com...
OMEGA PROJECT : Validation test report

CLK40_flash simulation : IC 72 pin 23
(clock frequency : 32 Mhz)

 12 ns
 5 ns

...
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 9 ns
 8 ns

Figure 4-1 :

comparison between simulation and measurement results...
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CLK40_flash measurement : IC 72 pin 23
(clock frequency : 24 Mhz)

 12 ns

Figure...
OMEGA PROJECT : Validation test report

4.2.3.2 Noise on Vcc power plane
The graphs are presented § 7.2 page 148 .
The mea...
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n° 3

all nets selected

plane model
50:1

180 mV pp

200 mV pp

900 mV pp

Measure...
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b) Comments
It is difficult to compare the simulation results to the measurements ...
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4.2.3.3 Noise on GND power plane
The test points and the related graphs are presen...
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MEASUREMENT

GND plane wave shape noise level
(Max peak-to-peak level)

Configurati...
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b) Comments

 The ground noise level simulated does not match the measured one. I...
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4.2.4 Synthesis of Results acquired with a willingly degraded CPU board (TBC)

The...
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The analysis of the results shows good coherence between measurements and simulatio...
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4.3 Validation on a multiboard system

4.3.1 Aims to be achieved

a)

Validation o...
OMEGA PROJECT : Validation test report
 J81-B6 (IO1) and J71-B6 (CPU);
 J91-B6 (IO2) and J71-B6 (CPU);
 J101-B6 (SPARE)...
OMEGA PROJECT : Validation test report

4.3.3 Synthesis of Results acquired with a normally backplane

The results can be ...
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The difference noticed should became from the component models used for the simulat...
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simulation on REQ_L2 : J72-C2

measurement on REQ_L2 : J72-C2

ref.: XXXXX

39 /39...
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Figure 4-3: Comparison between simulation and measurement on REQ_L2 signal

ref.: ...
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simulation on REQ_L2 : J72-C2

measurement on REQ_L2 : J72-C2

ref.: XXXXX

41 /39...
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Figure 4-4: Comparison between simulation and measurement on tfall for REQ_L2 sign...
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measurement on SCSB_AD(12) : J71-A5

Figure 4-5: Comparison between simulation and ...
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simulation on SCSB_AD(12) : J71-A5

measurement on SCSB_AD(12) : J71-A5

ref.: XXX...
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Figure 4-6: Comparison between simulation and measurement on tfall for SCSB_AD(12)...
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4.3.4 Synthesis of Results acquired with a degraded backplane

The bakcplane has b...
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f)

signal integrity on SCSB data and address nets at CPU level (entrée connecteur ...
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4.3.5 Optimisation of the design

The tool has been used to determine the impacts ...
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



f)

simulation and measurements (mesures obtenues au § Errore. L'origine rife...
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c)

signal integrity on clock nets at IO level (entrée connecteur ou carte : donne...
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

b)

noises on backplane ground plane (non perfect planes modelling )

Verificati...
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4.4 Simulation of the radiated emission of a breadboard

The test support used for...
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

the total soft routine duration is equal to 2300 ns

2.5 Mhz / 400ns

1

2

3

5...
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b)

BUFFER configuration
In this configuration, ports T and J of the micro control...
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4.4.3 Test fixture

The test fixtures for radiated emission measurements are descr...
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4.4.4 Comparison between simulations result and measurements

4.4.4.1 LOAD configu...
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4.4.4.2 BUFFER configuration



Example of measurement results in buffer configur...
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4.4.5 Conclusion

The result analysis show outstanding differences between measure...
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4.5 Validation of Mask definition and assignment requirement

ref.: XXXXX

60 /398...
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4.6 Validation of the Quick file automatic transmission

4.6.1 Description

The fi...
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The automatic transmission of a Quiksim file flow runs correctly
We have done a go ...
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5. PCB design methodology
5.1

Current status of a PCB design process

The EMC des...
OMEGA PROJECT : Validation test report

5.2.1 Diagram of a design flow after integration of the simulation tool

The integ...
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5.2.2 Engineering design phase

REQUIREMENTS
 operational, technical and electric...
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5.2.3 CAD (Computer Aided Design) phase

component placing

thermal simulations

E...
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ref.: XXXXX

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5.3 Significant benefits of the tool

5.3.1 in a PCB design process purpose

Signa...
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 System design

 Board zoning

 Part selection

 Component placing

 Schemati...
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5.3.1.1 Benefits at Pre-layout phase

PRESTO MBMS 1.0 is not a router and does not...
OMEGA PROJECT : Validation test report

c) The tool PRESTO will give helpful assistance to find other types of problems th...
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5.3.1.3 Benefits at Post-layout phase

As the tool allows us to eliminate the EMC ...
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5.3.1.4 Saving of time estimated

The save of time due to the use of PRESTO in our...
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 reduce time to market delay

EMC validation test phase

 ensure that timing budg...
OMEGA PROJECT : Validation test report

5.3.2 In a research development purpose

To carry out EMC research studies on new ...
OMEGA PROJECT : Validation test report

6. Limitations to be improved in the simulation
6.1 Radiated emission simulation

...
OMEGA PROJECT : Validation test report

7. ANNEXE :
Synthesis of Results acquired with a normally routed
CPU board
ref.: X...
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7.1 Signal Integrity check

7.1.1 Clock signal

a) Example 1: CLK20



Functional...
OMEGA PROJECT : Validation test report



simulation set up




no Xtalk



no what-if analysis



tstart : 2000 ns

...
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CLK 20 simulation : IC 72 pin 11

CLK 20 measurement : IC 72 pin 11

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...
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CLK 20 simulation : R1048-2

CLK 20 measurement : R1048-2

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CLK 20 simulation : IC 195 pin 154

CLK 20 measurement : IC 195 pin 154

ref.: XXX...
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b) Example 2: CLK40_RAM



Functional configuration

89

IC162

CLK40_RAM net
19
...
OMEGA PROJECT : Validation test report



simulation set up




no Xtalk



no what-if analysis



tstart : 2000 ns

...
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CLK40_RAM simulation : IC 72 pin 19

CLK40_RAM measurement : IC 72 pin 19

ref.: X...
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CLK40_RAM simulation : IC 163 pin 89

CLK40_RAM measurement : IC 163 pin 89

ref.:...
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CLK40_RAM simulation : IC 162 pin 89

CLK40_RAM measurement : IC 162 pin 89

ref.:...
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c) Example 3 : CLK40_FLASH



Functional configuration

IC154

FLASH memories

IC...
OMEGA PROJECT : Validation test report



simulation set up




no Xtalk



no what-if analysis



tstart : 2000 ns

...
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CLK40_flash simulation : IC 72 pin 23

CLK40_flash measurement : IC 72 pin 23

ref...
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CLK40_flash simulation : IC 155 pin 29

-

CLK40_flash measurement : IC 155 pin 29...
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ref.: XXXXX

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CLK40_flash simulation : IC 158 pin 29

CLK40_flash measurement : IC 158 pin 29

r...
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CLK40_flash simulation : IC 161 pin 29

CLK40_flash measurement : IC 161 pin 29

r...
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7.1.2 Control signal nets

d) Example 4: flash memories control net signal integri...
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

simulation set up




no Xtalk



no what-if analysis



tstart : 2000 ns

...
OMEGA PROJECT : Validation test report

CS_flash simulation : IC 154 pin 2

CS_flash measurement : IC 154 pin 2

ref.: XXX...
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tr = 11.6 ns
tf = 5.34 ns

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This document should be very interesting to an engineer because it reports a not biased experimental validation of a predictive tool carried out by a customer for an actual multiboard avionics design. The general considerations are reported at the beginning of the document...the conclusion is that a tool like PRESTO can save up to a 30% in the development time of a system like this . I have other papers reporting validations but these refers to specific non production test vehicules. Then if you give a quick look to the rest of the doc you will have an idea of what is the level of compliance between measurements and predictions...some results are very close together and other shows differences up to 70% or so...but we as engineers we have always to consider the min-max spread of technical specs for digital components may be in order of 100% or more of typical value so it is a nonsense trying to achieve better compliance. Moreover the digital test patterns involved are not the actual ones , and this can make a significant difference, even if Presto was provided with a feature allowing the user to put in the model actual test patterns as input stimuli. Presto was a state-of-the art post -layout tool at this time and this thanks to both the simulation engine (SPRINT, the predecessor of DWS) and to the modeling techniques including PD planes. Extracted nets of up to hundreds of thousands of lines (circuital elements) were simulated in some tens of minutes on machines that were 1000 times slower than today PCs. A true CO-SIMULATION of SI , PI and EMC was performed...no other commercial tool was able to achieve this performance level.
This can give you an idea of the capabilties of both DWS and related modeling methods like BTM ...the PI/SI examples I'm building up for Spicy SWAN are only a very small subset of the complexity Presto was able to deal with.

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Omega test report

  1. 1. OMEGA PROJECT : Validation test report TEST REPORT (OMEGA PROJECT) project n° 28599 ref.: XXXXX 1 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  2. 2. OMEGA PROJECT : Validation test report Reference : / 99 Date : Issue : 01 Written by : EMC group Visa : Approved by : Ph. BOITEUX Visa : REVIEW CONTENTS ref.: XXXXX 2 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  3. 3. OMEGA PROJECT : Validation test report Edition Date Description 01 XXXXX New document File ref.: XXXXX Modifications 3 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  4. 4. OMEGA PROJECT : Validation test report ref.: XXXXX 4 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  5. 5. OMEGA PROJECT : Validation test report REFERENCE’S DOCUMENTS Reference ref.: XXXXX Title Origin 5 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  6. 6. OMEGA PROJECT : Validation test report ref.: XXXXX 6 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  7. 7. OMEGA PROJECT : Validation test report CONTENTS 1. PURPOSE ........................................................................................................................................ 11 2. RECALL OF THE VALIDATION OBJECTIVES ....................................................................................... 12 3. RECALL OF THE USER'S REQUIREMENTS TO BE VALIDATED ............................................................ 13 4. VALIDATION PROCESS .................................................................................................................... 14 4.1 TESTING EQUIPMENTS .................................................................................................................. 14 4.2 VALIDATION ON A STAND ALONE CPU CARD...................................................................................... 14 4.2.1 Aims to be achieved .......................................................................................................... 14 4.2.2 Test points ........................................................................................................................ 14 4.2.3 Synthesis of Results acquired with a normally routed CPU board ...................................... 16 4.2.4 Synthesis of Results acquired with a willingly degraded CPU board (TBC) ......................... 33 4.2.5 Conclusion ........................................................................................................................ 33 4.3 VALIDATION ON A MULTIBOARD SYSTEM........................................................................................... 35 4.3.1 Aims to be achieved .......................................................................................................... 35 4.3.2 Simulation configurations .............................................. Errore. Il segnalibro non è definito. 4.3.3 Net tested ......................................................................................................................... 35 4.3.4 Synthesis of Results acquired with a normally backplane .................................................. 37 4.3.5 Synthesis of Results acquired with a degraded backplane ................................................. 46 4.3.6 Optimisation of the design ................................................................................................ 48 4.3.7 Conclusion ........................................................................................................................ 50 4.4 SIMULATION OF THE RADIATED EMISSION OF A BREADBOARD ............................................................... 52 4.4.1 Aims to be achieved .......................................................................................................... 52 ref.: XXXXX 7 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  8. 8. OMEGA PROJECT : Validation test report 4.4.2 Functional configurations ................................................................................................. 52 4.4.3 Test fixture ........................................................................................................................ 55 4.4.4 Comparison between simulations result and measurements ............................................. 56 4.4.5 Conclusion ........................................................................................................................ 59 4.5 VALIDATION OF MASK DEFINITION AND ASSIGNMENT REQUIREMENT ..................................................... 60 4.6 VALIDATION OF THE QUICK FILE AUTOMATIC TRANSMISSION ................................................................ 61 5. PCB DESIGN METHODOLOGY.......................................................................................................... 63 5.1 CURRENT STATUS OF A PCB DESIGN PROCESS .................................................................................... 63 5.2 INTEGRATION OF THE SIMULATION TOOL .......................................................................................... 63 5.2.1 Diagram of a design flow after integration of the simulation tool ..................................... 64 5.2.2 Engineering design phase ................................................................................................. 65 5.2.3 CAD (Computer Aided Design) phase................................................................................. 67 5.3 SIGNIFICANT BENEFITS OF THE TOOL ................................................................................................ 69 5.3.1 Benefits at Pre-layout phase ............................................................................................. 71 5.3.2 Benefits at Layout phase ................................................................................................... 71 5.3.3 Benefits at Post-layout phase ............................................................................................ 73 5.3.4 Saving of time estimated .................................................................................................. 75 6. LIMITATIONS TO BE IMPROVED IN THE SIMULATION ..................................................................... 78 6.1 RADIATED EMISSION SIMULATION ................................................................................................... 78 6.2 COMPONENT MODEL PARAMETERS .................................................................................................. 78 6.3 PRE-LAYOUT ANALYSIS OPTION ....................................................................................................... 78 ref.: XXXXX 8 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  9. 9. OMEGA PROJECT : Validation test report 7. ANNEXE : ....................................................................................................................................... 79 SYNTHESIS OF RESULTS ACQUIRED WITH A NORMALLY ROUTED CPU BOARD...................................... 79 7.1 SIGNAL INTEGRITY CHECK .............................................................................................................. 80 7.1.1 Clock signal ....................................................................................................................... 80 7.1.2 Control signal nets .......................................................................................................... 106 7.1.3 Data and address signal nets .......................................................................................... 126 7.2 NOISE ON VCC PLAN .................................................................................................................. 148 7.3 NOISE ON GROUND PLAN ............................................................................................................ 164 8. ANNEXE : ...................................................................................................................................... 176 SYNTHETIS OF RESULTS ACQUIRED WITH A MULTIBOARD SYSTEM .................................................... 176 8.1 CONFIGURATION WITH A CPU BOARD AND AN IO BOARD INTERCONNECTED THROUGH A BACKPLANE NORMALLY ROUTED.................................................................................................................................. 177 8.1.1 Signal integrity check ...................................................................................................... 179 8.1.2 Noise on the backplane logical ground ........................................................................... 372 8.2 CONFIGURATION WITH A CPU BOARD AND AN IO BOARD INTERCONNECTED THROUGH A BACKPLANE WILLINGLY DEGRADED............................................................................................................................... 264 ref.: XXXXX 9 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  10. 10. OMEGA PROJECT : Validation test report ABREVIATIONS LIST BMC Backplane Mother Board CAD Computer Aided Design EMC ElectroMagnetic Compatibility EMIR EMIssion Radiated GUI Graphic User Interface HDT High Design Technology IBIS Input/output Buffer Information Specification OMEGA Optimisation of Multi board systems under Emc Guidelines for Avionics PCB Printed Circuit Board PRESTO Post-layout Rapid Exhaustive Simulation and Test of Operation SSN Simultaneous Switching Noise SCSB Standard Computer System Bus TDR Time Domain Reflectometer XTALK traces cross-TALK Xsection Cross section ref.: XXXXX 10 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  11. 11. OMEGA PROJECT : Validation test report 1. Purpose This document is the final tests report which is owed in the framework of the project OMEGA and which closes the task 4. It presents the philosophy of the validation test, all the results analysis details and the investigation led to understand the differences between simulations and experiments. ref.: XXXXX 11 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  12. 12. OMEGA PROJECT : Validation test report 2. Recall of the validation objectives The main objective of this validation :  is to test the PRESTO_MBMS V1.1 tool functional features through the users requirements retained for the task 4 of the Omega project and presented in the document referenced 399.0026/99.  to verify and to evaluate the capability of the tool to improve a PCB design (changes in the layout design or changes in component values) by means of a what-if analysis The philosophy of PRESTO_MBMS V1.1 validation is essentially based on the comparison between simulation results and lab measurements. Mismatched results (differences between the two results) are investigated and if necessary, the validation test is carried on with interactive modifications between simulations and experiments. The different phases followed during this validation plan are :  Phase 1 : Simulations and lab measurements on PCB cards routed with avionics rules. This validation test is performed on a single CPU card and on a multi-board system made up of a CPU card and a I/O cards interconnected through a backplane (BMC).  Phase 2 : Simulations and lab measurements on PCB cards willingly degraded. This validation test is performed on a single willingly degraded CPU card and on a multi-board system made up of a CPU and a I/O cards interconnected through a willingly degraded backplane (BMC).  Phase 3 : Optimisation of the degraded card design  Phase 4 : This phase is specific to the radiation simulations and measurements carried out on a single bread board ref.: XXXXX 12 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  13. 13. OMEGA PROJECT : Validation test report 3. Recall of the user's requirements to be validated The User’s requirements validated during the task 4 of the OMEGA project are the following ones : 1. Simulation of interconnected boards 2. Automatic transmission from a QUICKSIM ASCII file into PRESTO and BIDIR/Tristate interfaces management 3. Mask definition and assignment 4. Noise on ground and power planes (planes modelling) 5. PCB modelling : 6 signals layers between two planes 6. radiated emission of a PCB ref.: XXXXX 13 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  14. 14. OMEGA PROJECT : Validation test report 4. Validation process 4.1 Testing equipments  Specific avionics test benches and software are used to test the functionality of the different pcbs (single CPU pcb or multiboard system). In addition to this, a software has been specially developed so as to have the same functional configurations between lab measurements and simulations : same data flow sense or same percentage of simultaneous switching drivers.  All measurements are performed in the time domain by means of sample numerical oscilloscopes with a bandwidth greater than 400 Mhz.  Differential active probes are used to pick-up the waveforms on the different test points previously identified 4.2 Validation on a stand alone CPU card 4.2.1 Aims to be achieved  Validation of the following requirements :  non perfect planes modelling for inner voltages and SSN computation (noises on ground and power planes)  bi-directional interfaces management  Coherence between simulation results and lab measurements related to :  clock net signal integrity  control net (RD_FLASH, CS_FLASH, OE_RAM, RW), data and address bus signal integrity  noises on Vcc and ground planes  Verification of the tool capability to improve the degraded CPU card design by optimising the decoupling capacitor values 4.2.2 Test points The reference of the test points (component pin-out, capacitor or resistor) are presented on each graph. Simulations and measured waveforms are visualised at the following points of the board .  For signal integrity ref.: XXXXX 14 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  15. 15. OMEGA PROJECT : Validation test report - at each end of clock signal nets - at each end of control, data and address signal nets  For noise on power and ground planes - either between the two nodes of a decoupling capacitor or between the Vcc and Ground nodes of a given component (micro-processor, buffers, RAM or clock generator) - between two points of the CPU logical ground to evaluate the non perfect ground effects on the noise level ref.: XXXXX 15 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  16. 16. OMEGA PROJECT : Validation test report 4.2.3 Synthesis of Results acquired with a normally routed CPU board The details of the comparison results between simulation and measurements are presented in Annex 7 :  § 7.1 page 80 : signal integrity check  § 7.2 page 148 : noise on Vcc plan  § 7.3 page 164 : noise on Ground plan 4.2.3.1 signal integrity check The graphs are presented § 7.1 page 80 and are completed by the following tables which compare the different parameter values got by simulation and measurements. To compare the simulation results to the measure, the following acceptance criteria are used including different type of errors (measurements, simulation, analysis...) :  on rise and fall time value, the difference (diff (%) ) shall be less than 20%  on signal amplitude value, the difference (diff (V) ) shall be less than 0.3 V From the comparison results analysis, the following observations can be drawn : - There are appreciable differences between simulation and measurement on rise time and fall time values (see following tables) - The line reflections and the oscillations sur-imposed on the signal are very different in some cases (ex : CLK40_RAM and CLK40_FLASH nets in annex 7 § b) page 88 and § c) page 96) - simulation results are very close to the measurement ones when the signal frequency is low (ex : CLK20 net and CLK40_RAM net in annex 7 § a) page 80 and § b) page 88). - the differences between simulations and measurements are particularly highlighted with high frequency signals (ex : CLK40_RAM and CLK40_FLASH nets in annex 7 paragraph b) page 88 and paragraph c) page 96)) and specially on the line reflections. ref.: XXXXX 16 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  17. 17. OMEGA PROJECT : Validation test report a) Clock signal Signal Test Ref name point page Simul Meas IC72-11 80 ? 2.6 R1048-2 80 1.8 2.6 IC195-154 80 0.93 2.1 IC72-19 88 ? 3.8 IC163-89 88 0.8 2.2 CLK20 CLK40RAM Tr (ns) diff (%) Simul Meas. ? 1.38 1.4 56 0.6 1 ? 1.2 64 Fall Edge Overshoot (V) Amplitude (V) 88 0.9 2 IC72-23 96 ? 7.39 IC155-29 96 3 3.3 IC158-29 96 3.9 3.46 ref.: XXXXX 55 0.6 1.1 ? diff (V) Simul Meas. diff (V) Simul Meas 3.8 3.8 0 -0.5 -0.4 0.1 3.8 3.8 found 1.4 4 3.9 -0.1 -0.5 -0.4 0.1 3.8 3.8 found 40 4.1 3.8 -0.3 -1.1 -0.7 0.4 3.9 3.8 found 5.1 4.6 -0.5 ? -0.6 ? 4.4 different 5.4 4.6 -0.8 -2 -1.4 ? 4.5 different 4.5 different at signal top level 4.15 9 2.6 2.31 -13 3 2.56 17 /398 Oscilation Meas 67 0.6 45 -0.7 -2.6 -1.4 1.2 diff (V) Reflection Simul 2 0.4 diff (%) 1.2 31 Rise Edge Overshoot (V) ? IC162-89 CLK40FLASH Tf (ns) 5.3 4.6 ? 5.2 -13 4.6 4.7 0.1 -0.9 -0.8 0.1 ? 4.5 slightly different at signal top level -17 4.7 4.7 0 -1 -0.8 0.2 ? 4.7 different at signal top level 0 XXX Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. different
  18. 18. OMEGA PROJECT : Validation test report ?: can't be estimated (not found in the .wave file) appreciable differences between simulation and measurement ref.: XXXXX 18 /398 XXX Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval.
  19. 19. OMEGA PROJECT : Validation test report b) Control signal Signal Test Ref name point page Simul Meas diff (%) Simul Meas. diff (%) Simul Meas diff (V) Simul Meas. diff (V) Simul Meas diff (V) Oscilation IC154 - 2 106 24 11.6 -107 7.5 5.3 -42 3.2 3.2 0 -0.5 -0.3 0.2 3.2 3.2 0 found IC195 - 53 106 3.2 3.2 0 -0.3 -0.2 0.1 3.2 3.2 0 found CS FLASH Tr (ns) Tf (ns) X Rise Edge Overshoot (V) X Fall Edge Overshoot (V) Amplitude (V) Reflection 106 12.7 9.5 -34 2.6 1.8 IC161 - 54 106 12.6 X 2.1 IC195 - 26 IC163 - 86 120 5.6 5.5 -2 1.3 1.6 RW IC163 - 87 120 5.6 4.5 -24 1.6 1.6 3.2 -0.2 -0.8 -0.5 0.3 3.3 3.2 -0.1 3.5 3.2 -0.3 -0.8 -0.6 0.2 3.3 3.2 -0.1 different at signal top level 3.2 -0.1 -0.3 -0.2 0.1 3.2 3.2 0 found 19 3.3 3.2 -0.1 -0.8 -0.5 0.3 3.3 3.2 -0.1 found 0 3.3 3.2 -0.1 -0.8 -0.5 0.3 3.3 3.2 -0.1 found 106 OE RAM 3.4 3.3 IC157 - 54 slightly different at signal top level -44 X Read FLASH ref.: XXXXX 19 /398 XXX Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval.
  20. 20. OMEGA PROJECT : Validation test report ?: can't be estimated (not found in the .wave file) X: not measured appreciable differences between simulation and measurement ref.: XXXXX 20 /398 XXX Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval.
  21. 21. OMEGA PROJECT : Validation test report c) Data and address signal Signal Test Ref Tr (ns) name point page Simul Meas IC195 - 120 126 ? IC154 - 28 126 IC154 - 26 Address bus Tf (ns) Fall Edge Overshoot (V) Reflection Meas diff (V) Simul Meas. diff (V) Simul Meas. diff (V) Oscilation 7.6 3.2 3 -0.2 -0.3 -0.1 0.2 3.2 3 -0.2 found ? 2.68 3.2 3 -0.2 -0.7 -0.4 0.3 3.2 3 -0.2 Slightly different 4.17 ? 3.47 3.4 3.1 -0.3 -0.7 0 0.7 3.3 3.1 -0.2 different ? 4.7 ? 3.8 3.4 3 -0.4 -0.2 0 0.2 3.3 3 -0.3 different 126 ? 5.7 ? 5.4 3.8 3.6 -0.2 -0.5 -0.4 0.1 3.3 3.1 -0.2 found 126 ? 7.7 ? 7.6 3.3 3.2 -0.1 -0.1 -0.1 0 3.2 3.1 -0.1 found Simul Meas. 13.3 ? ? 9.16 126 ? IC181 - 52 126 IC194 - 319 ?: X: diff (%) can't be estimated (not found in the .wave file) not measured appreciable differences between simulation and measurement ref.: XXXXX Amplitude (V) Simul diff (%) IC181 - 5 A_F1 Rise Edge Overshoot (V) 21 /398 XXX Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval.
  22. 22. OMEGA PROJECT : Validation test report d) Investigations The differences noted between simulation and measurement results are though to be due : - to the model of components used in the simulation and which is not representative of the real case (ex : package and RLC bonding parameters, default models used for component not modelled...) and which can leads to an excess of amount of capacitor on the net - to the way the tool uses the IBIS models V(t) ramp parameters (rise and fall time...) which are generally associated to a load circuit depending on the technology of the buffer (ex : 500 Ohms / 30pF) These different factors could explain some appreciable differences noted between simulation results and measurements. The results obtained on the net CLK40_FLASH is used for investigation. At the signal top level - When we compare the results of Figure 4-1 page 25, the signal waveform seems to be very different in a first approach. But when we analyse the result, we can note that this difference is due to the value of the rise time simulated (12ns) which is greater than the measured one ( 9ns). The consequence is that on a signal pulse width of 17 ns, it remains no sufficient time (5 ns including the signal fall time instead of 8 ns) to show the line reflection simulated by the tool. This difference of 3ns corresponds approximately to the half period of the reflection wave (3.5 ns) - To highlight the impact of the rise time on the signal wave shape, the test on the pentium board has been performed on the same net with a lower frequency (24 Mhz). The results are presented on Figure 4-2 page 26 The simulation seems to be more representative of the measurement. The only difference is that the pulse width is more important (the oscillation sur-imposed on the signal are represented) and the impact of the rise become less important. However, it shall be noted that a half period of the reflection wave is missing (2 oscillations at the signal top level instead of 3 measured). At the signal low level ref.: XXXXX 22 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  23. 23. OMEGA PROJECT : Validation test report The multiple oscillations present at the signal low level seem to be due to the component and the ground plane models. There is a resonance At 32 Mhz which is not present at 24 Mhz (see Figure 4-2 page 26) ref.: XXXXX 23 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  24. 24. OMEGA PROJECT : Validation test report CLK40_flash simulation : IC 72 pin 23 (clock frequency : 32 Mhz)  12 ns  5 ns CLK40_flash measurement : IC 72 pin 23 (clock frequency : 32 Mhz) ref.: XXXXX 24 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  25. 25. OMEGA PROJECT : Validation test report  9 ns  8 ns Figure 4-1 : comparison between simulation and measurement results at CLK40_FLASH driver output CLK40_flash simulation : IC 72 pin 23 (clock frequency : 24 Mhz) ref.: XXXXX 25 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  26. 26. OMEGA PROJECT : Validation test report CLK40_flash measurement : IC 72 pin 23 (clock frequency : 24 Mhz)  12 ns Figure 4-2 : comparison between simulation and measurement results at CLK40_FLASH driver output (signal frequency : 24 Mhz)  9 ns ref.: XXXXX  10 ns  13 ns 26 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  27. 27. OMEGA PROJECT : Validation test report 4.2.3.2 Noise on Vcc power plane The graphs are presented § 7.2 page 148 . The measurement is performed with an active probe between the two nodes of a 5V decoupling capacitor or between the Vcc and Ground nodes of noisy components selected on the board as micro controller and buffers. For measurement with functional activity on the CPU board, this activity consist in a reading of a data in RAM memories with a repetitive cycle of 1 µs. It shall be noted that between the reading cycle, the CPU goes on with its own instructions. a) Comparison results  On 5Vcc plane : It is not possible to compare the simulation result to the measurement due to the switching frequency of the DC/DC converter on the pentium board This case is presented in § 7.2 c) page 162. As the noise sources are not only generated by the switching of the I/O outputs, it is not easy to compare the simulation results to the measure in terms of noise spectrum and amplitude  On 2.5 Vcc and 3.3 Vcc planes Simulation 2.5 V planes 3.3 V planes Configuration IC194-19 (Vcc) and IC194-1 (Gnd) IC194-223 (Vcc) and IC194-321 (Gnd ) IC178-7 (Vcc) and IC178-11 (Gnd) 25 mV pp 18 mV pp 80 mV pp 80 mV pp 63 mV pp 180 mV pp differential mode simulation n° 1 only CLK nets plane model 50:1 n° 2 all CLK + all address (A_xx)+ Ram control nets (CS-OE) plane model 50:1 ref.: XXXXX 27 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  28. 28. OMEGA PROJECT : Validation test report n° 3 all nets selected plane model 50:1 180 mV pp 200 mV pp 900 mV pp Measurements 2.5 V planes 3.3 V planes Configuration between IC194-19 (Vcc) and IC194-1 (Gnd) between IC194-223 (Vcc) and IC194-321 (Gnd) between IC178-7 (Vcc) and IC178-11 (Gnd) n° 1 with reduced activity 30 mV pp 4 mV pp 20 mV pp n° 2 with functional activity 100 mV pp 80 mV pp 400 mV pp ref.: XXXXX 28 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  29. 29. OMEGA PROJECT : Validation test report b) Comments It is difficult to compare the simulation results to the measurements to the extent that the real internal activity of the micro processor is not well known and has a great impact on the noise spectra (see graphs at § 7.2 a) page 150 and § 7.2 b) page 154 in functional activity configuration). We can see on these graphs the soft routine frequency and its harmonics (ex: 2.5 VCC at pin IC194-223 ). Nevertheless, the simulation results show the general trend of the noise level seen in measurements :  The 2.5 V plane is more polluted than the 3.3 Vcc plane around IC 194  The area of the 3.3 Vcc plane around IC194-223 is less disturbed than the area of the 3.3 Vcc plane around IC178-50  The order of magnitude of the noise level is comparable ref.: XXXXX 29 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  30. 30. OMEGA PROJECT : Validation test report 4.2.3.3 Noise on GND power plane The test points and the related graphs are presented in annex 7 § 7.3 page 164. The points are selected in order to have a zoning of the ground plane noise. The measurement is performed with a functional activity on the CPU board, this activity consist in a reading of a data in RAM memories with a repetitive cycle of 1 µs. In the simulation, this configuration with a repetitive 1µs cycle wasn’t used. The driver switching frequency wasn’t a multiple of the main frequency clock frequency with a 50% duty cycle. The objective is to compare the peak-to-peak noise level induced in the ground impedance An active probe is used to measure the ground noise between the nodes selected a) Comparison results SIMULATION Configuration GND plane wave shape noise level C66 – C361 C63 – C66 C63 – C311 C63 – C64 C313 – C157 C66 – C243 plane model 50:1  22 mVpp  34 mVpp  26 mVpp  28 mVpp  14 mVpp  35 mVpp plane model 50:1  192 mVpp  315 mVpp  128 mVpp X  70 mVpp  224 mVpp differential mode simulation n° 1 n° 2 all CLK + all address (A_xx)+ Ram control nets (CS-OE) all nets ref.: XXXXX 30 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  31. 31. OMEGA PROJECT : Validation test report MEASUREMENT GND plane wave shape noise level (Max peak-to-peak level) Configuration C66 – C361 C63 – C66  80 mVpp  325 mVpp C63 – C311 C63 – C64 C313 – C157 C66 – C243 differential mode measurement n° 1 read Ram memories configuration ref.: XXXXX  50 mVpp  70 mVpp  60 mVpp 31 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval.  140 mVpp XXX
  32. 32. OMEGA PROJECT : Validation test report b) Comments  The ground noise level simulated does not match the measured one. In the same configuration (read Ram memories configuration), the simulation shows a peak-to-peak noise level lower than the measure.  the differences between the simulation and the measurement are too important and it seems that the way the planes are modelled have a non negligible impact on the simulation result accuracy.  The simulation results which give significant results compared to the measure ones are the simulation with all nets. It can be noted that the general trend of the noise level on the ground plane is given by the simulation. c) remark It shall be noted that all on the simulation result acquired in the time window from 4µs to 5µs (ex : see graph in §7.3 f) page 174 ) show a spike which can not be explained with the functional activity of the pentium board... ref.: XXXXX 32 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  33. 33. OMEGA PROJECT : Validation test report 4.2.4 Synthesis of Results acquired with a willingly degraded CPU board (TBC) The decoupling capacitor of noisy components (definir le composant) have been reduced from (donner la valeur initiale) to a value of (donner la valeur finale) in order to induce significant noise on the power distribution rails. The admissible value has been determined by simulation . The simulations and the measurements have been performed in the worst case configuration previously determined ( 100 %data drivers simultaneous commutation). The results are presented below : a) noise on Vcc net   b) simulation and measurements comparison between lab and simulation noise on the logical ground   c) simulation and measurements comparison between lab and simulation clock signal integrity  simulation and measurements  comparison between lab and simulation 4.2.5 Conclusion a) User's requirements validation "non perfect planes modelling" and "bidir management" requirements are compliant to what have been specified by the user b) Coherence between simulation results and lab measurements related to :  ref.: XXXXX Clock net signal integrity 33 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  34. 34. OMEGA PROJECT : Validation test report The analysis of the results shows good coherence between measurements and simulation. However the representativeness of the component models used has a great impact on the accuracy of the simulation, specially on rise and fall times or on line reflection. This is particularly apparent on high frequency signals (> 40 Mhz)  Non perfect planes modelling for inner voltages and SSN computation  Noises on power planes The simulation results show the general trend of the noise level seen in measurements. The order of magnitude of the noise level is comparable although it is difficult to simulate the real internal activity of the micro processor  Noises on ground planes In a similar configuration, The order of magnitude of the noise level is not comparable : the simulation results show a level of noise clearly less important than the measure. It seems that the model used for the ground plane has a great impact on the simulation accuracy c) Verification of the tool capability to improve the degraded CPU card design by optimising the decoupling capacitor values ref.: XXXXX 34 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  35. 35. OMEGA PROJECT : Validation test report 4.3 Validation on a multiboard system 4.3.1 Aims to be achieved a) Validation of the following requirements :   noises on the ground plane (non perfect planes modelling for SSN computation)  b) possibility to perform simulation with several board interconnected PCB modelling : 6 signals layers between two planes Coherence between simulation results and lab measurements related to :   c) signal integrity with SSN and cross-talk disturbances noise on the back-plane ground with SSN cross-talk disturbances Verification of the tool capability to improve the degraded back-plane design by optimising ground net layout 4.3.2 Net tested Simulations and measured waveforms are firstly performed on the critical nets of the SCSB bus detected by the cross talk coupling conditions and secondly on the backplane logical ground net. All the measurements have been made at the interface of the CPU connector (J71), IO1 connector (J82), IO2 connector (J92), SPARE connector (J102) a) Signal integrity controlled at the inputs of the SCSB bus receivers at I/O card connector level.  clock net : CLK_L2  control signal : REQ_L2, RDY_L2  data and address bus :SCSB_AD(0),SCSB_AD(12),SCSB_AD(22), SCSB_AD(35) b) between two points of the logical ground of the mother board : the differential voltage markers will be set between a ground pin of the CPU connector and a ground pin of the IO connector : ref.: XXXXX 35 /398 XXX Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval.
  36. 36. OMEGA PROJECT : Validation test report  J81-B6 (IO1) and J71-B6 (CPU);  J91-B6 (IO2) and J71-B6 (CPU);  J101-B6 (SPARE) and J91-B6 (CPU);  J82-B8 (IO1) and J71-B6 (CPU);  J92-B8 (IO2) and J71-B6 (CPU);  J102-B8 (SPARE) and J71-B6 (CPU);  J82-B8 (IO1) and J72-B8 (CPU);  J92-B8 (IO2) and J72-B8 (CPU);  J102-B8 (SPARE) and J72-B8 (CPU);  J71-B6 (CPU) and J72-B8 (CPU) ref.: XXXXX 36 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  37. 37. OMEGA PROJECT : Validation test report 4.3.3 Synthesis of Results acquired with a normally backplane The results can be viewed on annex 8.1 page 177. The first version of the multiboard tool does not include the waveform postprocessor option used on the single board. So it’s not possible today to present a result comparative board between simulation and measurements on the signal integrity parameters : trise/tfall time, overshoot and undershoot levels. The comparison is only based on the different curves obtained in simulation and in lab measurements. 4.3.3.1 Control signal integrity check It can be noted on the graphs presented in annex 8.1.1.1 page 179 that the simulation results match the measurements with a good approximation:  the oscillations and the line reflections on the signal are found  the fall edge and rise edge overshoot amplitude are similar We can conclude that the signal integrity of the control nets is well simulated by the tool. Examples are given Figure 4-3 and Figure 4-4. 4.3.3.2 Adress/data signal integrity check The results are presented in § 8.1.1.2 page 218. From the comparison results analysis, the following observations can be drawn :  there are appreciable differences between simulation and measurement on rise and fall time  the line reflections and the oscillations sur-imposed on the signal are very different Examples are given Figure 4-5 and Figure 4-6 to emphasise these differences. 4.3.3.3 Observation Note that the signal controls and data/address bus are not driven by the same component. The control signal are driven by an Actel component (A42MX16) for the REQ_L2 signal and by buffer component (74ALVCH162260) for data/address bus. ref.: XXXXX 37 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  38. 38. OMEGA PROJECT : Validation test report The difference noticed should became from the component models used for the simulation. ref.: XXXXX 38 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  39. 39. OMEGA PROJECT : Validation test report simulation on REQ_L2 : J72-C2 measurement on REQ_L2 : J72-C2 ref.: XXXXX 39 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  40. 40. OMEGA PROJECT : Validation test report Figure 4-3: Comparison between simulation and measurement on REQ_L2 signal ref.: XXXXX 40 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  41. 41. OMEGA PROJECT : Validation test report simulation on REQ_L2 : J72-C2 measurement on REQ_L2 : J72-C2 ref.: XXXXX 41 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  42. 42. OMEGA PROJECT : Validation test report Figure 4-4: Comparison between simulation and measurement on tfall for REQ_L2 signal simulation on SCSB_AD(12) : J71-A5 ref.: XXXXX 42 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  43. 43. OMEGA PROJECT : Validation test report measurement on SCSB_AD(12) : J71-A5 Figure 4-5: Comparison between simulation and measurement on SCSB_AD(12) signal ref.: XXXXX 43 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  44. 44. OMEGA PROJECT : Validation test report simulation on SCSB_AD(12) : J71-A5 measurement on SCSB_AD(12) : J71-A5 ref.: XXXXX 44 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  45. 45. OMEGA PROJECT : Validation test report Figure 4-6: Comparison between simulation and measurement on tfall for SCSB_AD(12) signal ref.: XXXXX 45 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  46. 46. OMEGA PROJECT : Validation test report 4.3.4 Synthesis of Results acquired with a degraded backplane The bakcplane has been willingly degraded as follow :  The clock traces is not buried between 2 ground planes  The ground net is routed by means of an area filled trace less than 1mm in width.  The nets RDY_L2 and REQ_L2 are routed as closed as possible with the clock net CLK_L2 in parallel straight traces. The simulations and the measurements are presented in § 8.2 page 264 The results are presented below : a) noise on the backplane logical ground   b) simulation and measurements comparison between lab and simulation signal integrity on clock nets at CPU level (entrée connecteur + carte : donner le cas le plus intéressant)   c) simulation and measurements comparison between lab and simulation signal integrity on clock nets at IO level (entrée connecteur + carte : donner le cas le plus intéressant)   d) simulation and measurements comparison between lab and simulation signal integrity on control signal nets at CPU level (entrée connecteur + carte : donner le cas le plus intéressant)   e) simulation and measurements comparison between lab and simulation signal integrity on control signal nets at IO level (entrée connecteur + carte : donner le cas le plus intéressant)   ref.: XXXXX simulation and measurements comparison between lab and simulation 46 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  47. 47. OMEGA PROJECT : Validation test report f) signal integrity on SCSB data and address nets at CPU level (entrée connecteur + carte : donner le cas le plus intéressant)   g) simulation and measurements comparison between lab and simulation signal integrity on SCSB data and address nets at IO level (entrée connecteur + carte : donner le cas le plus intéressant)   ref.: XXXXX simulation and measurements comparison between lab and simulation 47 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  48. 48. OMEGA PROJECT : Validation test report 4.3.5 Optimisation of the design The tool has been used to determine the impacts of the backplane ground net modifications on the signal integrity. The simulations are performed in the worst case configuration previously determined (100 % data drivers simultaneous commutation). 4.3.5.1 Simulations results with a ground defined as an ideal plane a) noise on the backplane logical ground   b) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on clock nets at CPU level (entrée connecteur ou carte : donner le cas le plus intéressant)   c) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on clock nets at IO level (entrée connecteur ou carte : donner le cas le plus intéressant)   d) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on control signal nets at CPU level (entrée connecteur ou carte : donner le cas le plus intéressant)   e) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on control signal nets at IO level (entrée connecteur ou carte : donner le cas le plus intéressant) ref.: XXXXX 48 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  49. 49. OMEGA PROJECT : Validation test report   f) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on SCSB data and address nets at CPU level (entrée connecteur + carte : donner le cas le plus intéressant)   g) simulation and measurements comparison between lab and simulation signal integrity on SCSB data and address nets at IO level (entrée connecteur + carte : donner le cas le plus intéressant)  simulation and measurements  comparison between lab and simulation 4.3.5.2 Simulations results with the ground net defined as a non perfect plane a) noise on the backplane logical ground   b) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on clock nets at CPU level (entrée connecteur ou carte : donner le cas le plus intéressant)   ref.: XXXXX simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation 49 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  50. 50. OMEGA PROJECT : Validation test report c) signal integrity on clock nets at IO level (entrée connecteur ou carte : donner le cas le plus intéressant)   d) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on control signal nets at CPU level (entrée connecteur ou carte : donner le cas le plus intéressant)   e) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on control signal nets at IO level (entrée connecteur ou carte : donner le cas le plus intéressant)   f) simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non è stata trovata.) comparison between lab and simulation signal integrity on SCSB data and address nets at CPU level (entrée connecteur + carte : donner le cas le plus intéressant)   g) simulation and measurements comparison between lab and simulation signal integrity on SCSB data and address nets at IO level (entrée connecteur + carte : donner le cas le plus intéressant)  simulation and measurements  comparison between lab and simulation 4.3.6 Conclusion a) Coherence between simulation results and lab measurements related to :  ref.: XXXXX signal integrity including SSN and cross talk disturbances noises 50 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  51. 51. OMEGA PROJECT : Validation test report  b) noises on backplane ground plane (non perfect planes modelling ) Verification of the tool capability to improve the degraded backplane ground layout design ref.: XXXXX 51 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  52. 52. OMEGA PROJECT : Validation test report 4.4 Simulation of the radiated emission of a breadboard The test support used for this validation is a breadboard specially developed and including a microcontroller. The measurement is performed in a semi-anechoid chamber with :  a whip antenna in the frequency range from 100 Khz to 30 Mhz  a bicolog antenna in the frequency range from 30 Mhz to 1Ghz 4.4.1 Aims to be achieved Validation of the tool capability to predict the radiated emissions of a non complex PCB. 4.4.2 Functional configurations Two running functional modes have been used to activate the I/O ports of the micro-controller. a) Load configuration In this configuration, each output of the port B drives a capacitance load of 50 pF. PB0 50 pF µcontroller PB7 50 pF The 8 outputs of this port are switched simultaneously according to the following bit sequences :  4 cycles with 400 ns time duration and 50 % duty cycle  a fifth cycle with (500ns + 200ns) time duration ref.: XXXXX 52 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  53. 53. OMEGA PROJECT : Validation test report  the total soft routine duration is equal to 2300 ns 2.5 Mhz / 400ns 1 2 3 500 ns 4 200 ns 5 2300 ns ref.: XXXXX 53 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  54. 54. OMEGA PROJECT : Validation test report b) BUFFER configuration In this configuration, ports T and J of the micro controller drive the inputs of a buffer type FCT16543. PT0 PT7 µcontroller FCT16543 PJ0 PJ7 The outputs of port T (or port J) are switched simultaneously according to the following bit sequences :  4 cycles with 816 ns time duration and 50 % duty cycle  a fifth cycle with (702 ns + 408 ns) time duration  the total soft routine duration is equal to 4374 ns A delay of 200 ns is inserted between the simultaneous commutation of the outputs of port T and the simultaneous commutation of the outputs of port J 1,225 Mhz / 816 ns Port T 1 2 3 702 ns 4 408 ns 5 4374 ns Port J delay ref.: XXXXX 200 ns 54 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  55. 55. OMEGA PROJECT : Validation test report 4.4.3 Test fixture The test fixtures for radiated emission measurements are described in the following figure. The measurement is performed for each rotation of the PCB around its radial axis shielded box UUT antennae 1m copper plan * 10 cm semi anechoid chamber 1m * the copper plan is connected to the mechanical ground ref.: XXXXX 55 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  56. 56. OMEGA PROJECT : Validation test report 4.4.4 Comparison between simulations result and measurements 4.4.4.1 LOAD configuration  Example of measurement results in load configuration Level [dBµV/m] Level [dBµV/m] measure with a whip antenna 40 measure with a bicolog antenna 40 2.5 Mhz 30 30 430 khz 20 20 10 10 0 150k 300k 500k 1M 2M 3M 4M 5M Frequency [Hz] 7M 10M 30M 0 30M 40M 50M 70M 100M 200M Frequency [Hz] 300M 400M 600M * 430 Khz and its harmonics are related to the soft routine cycle * 2,5 Mhz and its harmonics are related to the port B outputs switching frequency  Corresponding simulation result ref.: XXXXX 56 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX 1G
  57. 57. OMEGA PROJECT : Validation test report ref.: XXXXX 57 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  58. 58. OMEGA PROJECT : Validation test report 4.4.4.2 BUFFER configuration  Example of measurement results in buffer configuration Level [dBµV/m] Level [dBµV/m] measure with a whip antenna 40 1,225 Mhz 30 30 230 Khz 20 20 10 0 measure with a bicolog antenna 40 10 150k 300k 500k 1M 2M 3M 4M 5M Frequency [Hz] 7M 10M 30M 0 30M 40M 50M 70M 100M 200M Frequency [Hz] 300M 400M 600M * 230 Khz and its harmonics are related to the soft routine cycle * 1,225 Mhz and its harmonics are related to the port T  J outputs switching frequency  Corresponding simulation result ref.: XXXXX 58 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX 1G
  59. 59. OMEGA PROJECT : Validation test report 4.4.5 Conclusion The result analysis show outstanding differences between measurement and simulation :  at low frequency (< 30 Mhz), we can noted the lack of frequency rays above 0 dbµV/m with the simulation when the measurement reveal the switching frequency of the outputs and the routine loop frequency with a consequent level above the noise.  at high frequency ( > 30 Mhz), the wave shape of the radiation spectrum are not comparable these differences are though to be due to :  the assumption of being in far field conditions is not respected with the electromagnetic formulation. The tool is only able to perform radiated simulation for far field (d>3m or f=30Mhz), which are not compatible with Aeronautical CEM test conditions (d=1m and 10Khz<f<400Mhz).  the inability of the tools to simulate the radiated emission from multi-clock signals  the impact of the broadband noises on the spectrum radiation ref.: XXXXX 59 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  60. 60. OMEGA PROJECT : Validation test report 4.5 Validation of Mask definition and assignment requirement ref.: XXXXX 60 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  61. 61. OMEGA PROJECT : Validation test report 4.6 Validation of the Quick file automatic transmission 4.6.1 Description The file which describe the simulation waveforms is a .log format file. This file is converted by the tool in an interpretable format by Presto. The flow is described below Simulation waveforms .log QUICKSIM TRANSLATOR file The Quicksim sequence is translated in a Presto sequence, .qseq file .qseq file QUICKSIM SELECTOR allows selection net for simulation 4.6.2 Results ref.: XXXXX 61 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  62. 62. OMEGA PROJECT : Validation test report The automatic transmission of a Quiksim file flow runs correctly We have done a go no go test on a clock signal, the Quicksim simulation waveform has been translated and visualise on Sights (waveform viewer of Presto). More test will be achieved subsequently. ref.: XXXXX 62 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  63. 63. OMEGA PROJECT : Validation test report 5. PCB design methodology 5.1 Current status of a PCB design process The EMC design manager operates in different phases of an avionics equipment design process :  at pre design step with functional architecture and technological choices in collaboration with the electronic functional designer  at main design step with schematics analysis and EMC requirements writing  at physical PCB design step with component placing, layout and routing analysis and verification of the taking into consideration of EMC constraints in collaboration with the PCB layout design engineer 5.2 Integration of the simulation tool The simulation tool is inserted in the existing design flow at PCB layout and routing phase and is applied only on the numerical functional parts of the PCB  In the engineering design phase, the EMC manager will enquire about the availability of the EMC models of all logical component used in the design. The creation of new EMC component models (by component models provider) will be initialised in the same way as for models used in numerical simulation  In CAD (computer aided design) phase, the CAD file extracted from the PCB layout is provided as input data for simulation. This file will be stored in a specific directory in order to be used by the EMC engineer without interrupting the PCB design progress. Therefore, the simulation will be performed outside the design flow.  At the beginning of the CAD design phase, the EMC manager shall specify if the simulation tool will be used or not according to the complexity of the PCB. To limit the number of iterations between simulations and CAD data extraction, break points for the generation of the cadif file will be defined in the PCB design flow by the EMC manager. These break points will be determined in collaboration with the PCB layout designer . ref.: XXXXX 63 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  64. 64. OMEGA PROJECT : Validation test report 5.2.1 Diagram of a design flow after integration of the simulation tool The integration of PRESTO in AEROSPATIALE design methodology is described in the following bloc diagram. The coloured blocs define the operations related to the use of the simulation tool in the existing design process. ref.: XXXXX 64 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  65. 65. OMEGA PROJECT : Validation test report 5.2.2 Engineering design phase REQUIREMENTS  operational, technical and electrical constraints  environment conditions (ex : electromagnetic environment and lightning requirements) preliminary electrical design - working frequency plan - component pre nomenclature analysis - electrical architecture definition  EMC, and component technology preanalysis selection first list of components to be modelled and developed for simulation  EMC protection pre assessment no results analysis ? yes detailed electrical design functional simulations - list of components - schematics EMC design rule and requirement no ref.: XXXXX additional list of components to be modelled and developed for simulation EMC analysis results analysis ? yes EMC and functional constraints for CAD and PCB layout (NCC) 65 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  66. 66. OMEGA PROJECT : Validation test report ref.: XXXXX 66 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  67. 67. OMEGA PROJECT : Validation test report 5.2.3 CAD (Computer Aided Design) phase component placing thermal simulations EMC requirement fulfilment controls  PCB zoning and component segregation  compliance with : - trace length constraints - decoupling capacitor constraints no control results ok ? - I/O component constraints yes - etc... PCB layout and routing physical PCB design control  layout and routing  signal segregation  no cross-talk risks control results ok ?  etc... yes Cadif file : extraction of layout information's simulation with PRESTO  evaluation of cross-talk coupled sections  verification of the integrity of critical signals (clock, control, write and read, data and address bus)  what-if no analysis simulations results ok?  etc... yes ref.: XXXXX compliance matrix related/398 67 to NCC constraints (DCC) Issue 1 no non Il ne peut être accepted Ce document est la propriété d’AEROSPATIALE.compliance communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. ? This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. yes data transfer to PCB production XXX
  68. 68. OMEGA PROJECT : Validation test report ref.: XXXXX 68 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  69. 69. OMEGA PROJECT : Validation test report 5.3 Significant benefits of the tool 5.3.1 in a PCB design process purpose Signal-integrity, crosstalk, and EMC analysis are significant components of successful high-speed PCB design particularly as IC switching speeds increase. Taking them into consideration early in the design process allows the user to:  generate constraints for PCB router  avoid costly PCB turns  reduce time to market delay  ensure that timing budgets are met  produce higher-quality boards  avoid long lab sessions searching for intermittent failures  avoid embarrassing and costly test failures However these benefits are not present at each design step of a PCB. The main steps followed by the development of an avionic PCB are described below: Pre-layout ref.: XXXXX Layout Post layout 69 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  70. 70. OMEGA PROJECT : Validation test report  System design  Board zoning  Part selection  Component placing  Schematic entry Full board placing and routing Prototype  critical nets routing EMC and timing pre-analysis ref.: XXXXX SI, Xtalk, EMC analysis Post layout EMC verification functional and EMC validation test 70 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  71. 71. OMEGA PROJECT : Validation test report 5.3.1.1 Benefits at Pre-layout phase PRESTO MBMS 1.0 is not a router and does not offer pre-layout analysis option, so Signal-integrity, crosstalk and EMC analysis can not begin before the PCB is laid out. The saving of time is therefore negligible at this step and the direct benefits expected are limited. 5.3.1.2 Benefits at Layout phase The saving of time is negligible at this step. However, the use of the tool at this stage will allow a better prediction of EMC problems on the PCB, will bring appropriate solutions where it is less costly and more efficient and in fine it will give greatest chances of producing a successful first-prototype board. a) Best PCB design With the simulation tool PRESTO MBMS 1.0, mistakes on the PCB will early be caught and overprotected design or inadequate EMC solutions (which are generally expensive) will be avoided. This will help us:   to correctly examine the effects of grounded guard traces and to compare their usage in order to increase trace separation  b) to correctly study the trade-offs between different routing topologies, board layer stackups and even IC driving technologies before the full board is laid out. to optimally terminate transmission line for high speed signals Accurate constraints for optimum reduction of coupling including :  minimum trace-to-trace separation  maximum parallel run lengths  maximum driver IC slew rate  stackup layer thickness and position ref.: XXXXX 71 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  72. 72. OMEGA PROJECT : Validation test report c) The tool PRESTO will give helpful assistance to find other types of problems that can only be found after PCB layout. For example, even a properly designed net can be negatively affected by the layout process, e.g., if the trace's length is not constrained properly during routing, or if a net wanders too many times between board layers. Also, it is sometimes difficult to pre-plan nets beyond the truly critical ones on a board. ref.: XXXXX 72 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  73. 73. OMEGA PROJECT : Validation test report 5.3.1.3 Benefits at Post-layout phase As the tool allows us to eliminate the EMC problems early in the design, we will be able to : a) Enhance the old PCB design by anticipating the effects of technology changes earlier in the design process or the emergence of new technologies with very high frequencies b) Avoid costly PCB turns Getting the PCB right the first time means a shorter design cycle and thus significant cost saving c) Reduce budget overruns Making design changes before prototypes are built, is far less costly than making changes after fabrication and this limits budget overruns. d) Produce higher-quality boards The result is cleaner boards, reduced time in the lab test sessions, fewer PCB revisions, fewer signal-quality, delay, crosstalk test failures and significantly lower product-development costs. This increases the gain in productivity and the reduces the cost / performance ratio. e) Reduce time to market delay By getting the avionics card right the first time with a high quality will greatly reduce the time to market delay. f) Avoid long lab sessions searching for intermittent failures The tool can be used for emergencies to pull us through a problem found in validation/integration phase. The tool gives helpful assistance for investigation by let us trying several solutions quickly and choosing the most appropriate one. g) Avoid costly validation/qualification test failures h) Reduce costly time consuming EMC test sessions for minor modifications The only way today to suitable evaluate the potential EMC risk on electronic equipment or avionic card and to check their compliance with EMC constraints is to perform EMC tests on a prototype. This approach requires the development of a prototype and important EMC facilities which unfortunately represents a costly investment for minor modifications or evolution on the card ref.: XXXXX 73 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  74. 74. OMEGA PROJECT : Validation test report ref.: XXXXX 74 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  75. 75. OMEGA PROJECT : Validation test report 5.3.1.4 Saving of time estimated The save of time due to the use of PRESTO in our design flow is very appreciable at post layout phase when the prototype undergoes all the tests necessary for it certification Related to the time to market delay, the dead loss of time induced by EMC failures is estimated as follow :  12% when the EMC failures occur at functional validation test phase  25% when the EMC failures occur at EMC validation test phase  30% when the EMC failures occur at EMC qualification test phase For minor modifications or evolution in the design (new components, technology changes, etc...), the save of time is estimated to 25 % specially due to the fact that PRESTO is used as a valuable EMC analysis means which avoid costly re-validation and re-qualification tests. From this analysis, we can say that the sooner the mistakes are caught, the less time and money are spent : it costs many times more to fix a mistake after PCB layout than before, and another many times more to fix it after prototyping than before. In terms of real total cost, the impact of EMC failures at post layout phase is very important and can represent 30% of the final product. Synthesis Step benefits expected saving of time Pre layout  helpful assistance to generate routing constraint (no pre layout analysis option in PRESTO) 0%  better PCB design 0% Layout  better prediction of EMC problems Post layout  Anticipating the effects of technology  12% when the EMC failures occur at changes functional validation test phase  25% when the EMC failures occur at  avoid costly PCB turns ref.: XXXXX 75 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  76. 76. OMEGA PROJECT : Validation test report  reduce time to market delay EMC validation test phase  ensure that timing budgets are met  produce higher-quality boards  30% when the EMC failures occur at EMC qualification test phase  avoid long lab sessions searching for intermittent failures  reduce costly time consuming EMC test sessions for minor modifications ref.: XXXXX 76 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  77. 77. OMEGA PROJECT : Validation test report 5.3.2 In a research development purpose To carry out EMC research studies on new high speed electronic designs or on PCB enhancement, it is necessary up to now to develop a prototype card including the different functional configurations to be analysed from the EMC viewpoint. This approach unfortunately represents a non negligible investment cost for PCB manufacturing and components purchase. With the simulation tool it shall be possible to perform the same EMC analysis on a virtual prototype PCB and tis process based on a simulation approach will allow a great flexibility :  to study the trade-offs between different routing topologies  to anticipate the effects of technology changes or the emergence of new technologies with very high frequencies  to accurately examine the effects of a transmission line ending impedance on the line reflection  to correctly reduce the coupling section between parallel traces In fine, this will end by a better specification of EMC constraints for future PCB design ref.: XXXXX 77 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  78. 78. OMEGA PROJECT : Validation test report 6. Limitations to be improved in the simulation 6.1 Radiated emission simulation  Moreover the limitations identified in the user’s requirement document (the striplines radiations can’t be simulated), the tool is limited for far field simulation. It allows a simulation with antenna distance d>3m and a signal frequency>30 Mhz. These conditions are not compatible with Aeronautical EMC test specification (d=1m and spectral frequency range between 10Khz and 400Mhz). 6.2 component model parameters  models representativeness at high frequency : impact of trise/tfall parameters on signal integrity.  pin to pin connector model can’t be used with ground pins.  Ground plane modelling shall be more accurate to present a greater representativeness of the results. 6.3 pre-layout analysis option no pre layout option available in MBMS version. ref.: XXXXX 78 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  79. 79. OMEGA PROJECT : Validation test report 7. ANNEXE : Synthesis of Results acquired with a normally routed CPU board ref.: XXXXX 79 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  80. 80. OMEGA PROJECT : Validation test report 7.1 Signal Integrity check 7.1.1 Clock signal a) Example 1: CLK20  Functional configuration R1048 11 27.4  CLK20 154 2 IC72 IC195 ROBOCLOCK A42MX16 CPU BOARD ref.: XXXXX 80 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  81. 81. OMEGA PROJECT : Validation test report  simulation set up   no Xtalk  no what-if analysis  tstart : 2000 ns  tstop : 2500 ns  resolution : 2048  planes modelled (10 : 1)   no SSN nets selected : only clock nets comparison between simulation and measurements See following curves ref.: XXXXX 81 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  82. 82. OMEGA PROJECT : Validation test report CLK 20 simulation : IC 72 pin 11 CLK 20 measurement : IC 72 pin 11 ref.: XXXXX 82 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  83. 83. OMEGA PROJECT : Validation test report ref.: XXXXX 83 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  84. 84. OMEGA PROJECT : Validation test report CLK 20 simulation : R1048-2 CLK 20 measurement : R1048-2 ref.: XXXXX 84 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  85. 85. OMEGA PROJECT : Validation test report ref.: XXXXX 85 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  86. 86. OMEGA PROJECT : Validation test report CLK 20 simulation : IC 195 pin 154 CLK 20 measurement : IC 195 pin 154 ref.: XXXXX 86 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  87. 87. OMEGA PROJECT : Validation test report ref.: XXXXX 87 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  88. 88. OMEGA PROJECT : Validation test report b) Example 2: CLK40_RAM  Functional configuration 89 IC162 CLK40_RAM net 19 RAM IC72 ROBOCLOCK 89 IC163 RAM CPU BOARD ref.: XXXXX 88 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  89. 89. OMEGA PROJECT : Validation test report  simulation set up   no Xtalk  no what-if analysis  tstart : 2000 ns  tstop : 2500 ns  resolution : 2048  planes modelled (10 : 1)   no SSN nets selected : only clock nets comparison between simulation and measurements See following curves ref.: XXXXX 89 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  90. 90. OMEGA PROJECT : Validation test report CLK40_RAM simulation : IC 72 pin 19 CLK40_RAM measurement : IC 72 pin 19 ref.: XXXXX 90 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  91. 91. OMEGA PROJECT : Validation test report ref.: XXXXX 91 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  92. 92. OMEGA PROJECT : Validation test report CLK40_RAM simulation : IC 163 pin 89 CLK40_RAM measurement : IC 163 pin 89 ref.: XXXXX 92 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  93. 93. OMEGA PROJECT : Validation test report ref.: XXXXX 93 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  94. 94. OMEGA PROJECT : Validation test report CLK40_RAM simulation : IC 162 pin 89 CLK40_RAM measurement : IC 162 pin 89 ref.: XXXXX 94 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  95. 95. OMEGA PROJECT : Validation test report ref.: XXXXX 95 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  96. 96. OMEGA PROJECT : Validation test report c) Example 3 : CLK40_FLASH  Functional configuration IC154 FLASH memories IC155 IC156 29 IC157 ROBOCLOCK 29 IC158 IC72 29 CLK40_FLASH IC1549 23 29 IC160 29 IC161 29 29 CPU BOARD ref.: XXXXX 29 96 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  97. 97. OMEGA PROJECT : Validation test report  simulation set up   no Xtalk  no what-if analysis  tstart : 2000 ns  tstop : 2500 ns  resolution : 2048  planes modelled (10 : 1)   no SSN nets selected : only clock nets comparison between simulation and measurements ref.: XXXXX 97 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  98. 98. OMEGA PROJECT : Validation test report CLK40_flash simulation : IC 72 pin 23 CLK40_flash measurement : IC 72 pin 23 ref.: XXXXX 98 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  99. 99. OMEGA PROJECT : Validation test report ref.: XXXXX 99 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  100. 100. OMEGA PROJECT : Validation test report CLK40_flash simulation : IC 155 pin 29 - CLK40_flash measurement : IC 155 pin 29 ref.: XXXXX 100 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  101. 101. OMEGA PROJECT : Validation test report ref.: XXXXX 101 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  102. 102. OMEGA PROJECT : Validation test report CLK40_flash simulation : IC 158 pin 29 CLK40_flash measurement : IC 158 pin 29 ref.: XXXXX 102 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  103. 103. OMEGA PROJECT : Validation test report ref.: XXXXX 103 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  104. 104. OMEGA PROJECT : Validation test report CLK40_flash simulation : IC 161 pin 29 CLK40_flash measurement : IC 161 pin 29 ref.: XXXXX 104 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  105. 105. OMEGA PROJECT : Validation test report ref.: XXXXX 105 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  106. 106. OMEGA PROJECT : Validation test report 7.1.2 Control signal nets d) Example 4: flash memories control net signal integrity  Functional configuration IC154 FLASH IC155 2 54 IC156 2 ACTEL FPGA 54 IC195 Rd-FLASH IC157 2 26 54 IC158 2 54 CS-FLASH 53 IC159 2 54 IC160 2 54 IC161 2 54 2 CPU BOARD 54 ref.: XXXXX 106 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  107. 107. OMEGA PROJECT : Validation test report  simulation set up   no Xtalk  no what-if analysis  tstart : 2000 ns  tstop : 2500 ns  resolution : 2048  planes modelled (10 : 1)   no SSN nets selected : all nets comparison between simulation and measurements See following curves The differences noted on the pulse width duration between simulation and measurement are due to the fact that the measurement takes into account the real activity of the CPU board although the simulation is performed with one pattern selected among several. ref.: XXXXX 107 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  108. 108. OMEGA PROJECT : Validation test report CS_flash simulation : IC 154 pin 2 CS_flash measurement : IC 154 pin 2 ref.: XXXXX 108 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX
  109. 109. OMEGA PROJECT : Validation test report tr = 11.6 ns tf = 5.34 ns ref.: XXXXX 109 /398 Issue 1 Ce document est la propriété d’AEROSPATIALE. Il ne peut être communiqué à des tiers et/ou reproduit sans autorisation écrite préalable d’AEROSPATIALE. This document is the property of AEROSPATIALE. It cannot be disclosed and/or reproduced without AEROSPATIALE written approval. XXX

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